April 2019 - U-Boot

[U-Boot] [PATCH] bootm: Simplying cache flush code
by Trent Piepho 24 Apr '19

24 Apr '19

The cache flush of the kernel load area needs to be aligned outward to the DMA cache alignment. The operations are simpler if we think of this as aligning the start down, ALIGN_DOWN(load, ARCH_DMA_MINALIGN), and aligning the end up, ALIGN(load_end, ARCH_DMA_MINALIGN), and then find the length of the flushed region by subtracting the former from the latter. Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bryan O'Donoghue <bryan.odonoghue(a)linaro.org> Signed-off-by: Trent Piepho <tpiepho(a)impinj.com> --- common/bootm.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/common/bootm.c b/common/bootm.c index 8bf84ebcb7..8af8efd169 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -453,7 +453,6 @@ static int bootm_load_os(bootm_headers_t *images, int boot_progress) ulong image_start = os.image_start; ulong image_len = os.image_len; ulong flush_start = ALIGN_DOWN(load, ARCH_DMA_MINALIGN); - ulong flush_len; bool no_overlap; void *load_buf, *image_buf; int err; @@ -468,11 +467,7 @@ static int bootm_load_os(bootm_headers_t *images, int boot_progress) return err; } - flush_len = load_end - load; - if (flush_start < load) - flush_len += load - flush_start; - - flush_cache(flush_start, ALIGN(flush_len, ARCH_DMA_MINALIGN)); + flush_cache(flush_start, ALIGN(load_end, ARCH_DMA_MINALIGN) - flush_start); debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, load_end); bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED); -- 2.14.5

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[U-Boot] [PATCH] malloc: Fix memalign not honoring alignment prior to full malloc init
by Andreas Dannenberg 24 Apr '19

24 Apr '19

When using memalign() in a scenario where U-Boot is configured for full malloc support with simple malloc not explicitly enabled and before the full malloc support is initialized, a memory block is being allocated and returned without the alignment parameter getting honored. Fix this issue by replacing the existing memalign pre-full malloc init logic with a call to memalign_simple() this way ensuring proper alignment of the returned memory block. Fixes: ee038c58d519 ("malloc: Use malloc simple before malloc is fully initialized in memalign()") Signed-off-by: Andreas Dannenberg <dannenberg(a)ti.com> --- common/dlmalloc.c | 3 +-- include/malloc.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/common/dlmalloc.c b/common/dlmalloc.c index edaad299bb..6f12a18d54 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1893,8 +1893,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; #if CONFIG_VAL(SYS_MALLOC_F_LEN) if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) { - nb = roundup(bytes, alignment); - return malloc_simple(nb); + return memalign_simple(alignment, bytes); } #endif diff --git a/include/malloc.h b/include/malloc.h index b714fedf45..5efa6920b2 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -878,7 +878,6 @@ extern Void_t* sbrk(); #define memalign memalign_simple static inline void free(void *ptr) {} void *calloc(size_t nmemb, size_t size); -void *memalign_simple(size_t alignment, size_t bytes); void *realloc_simple(void *ptr, size_t size); void malloc_simple_info(void); #else @@ -914,6 +913,7 @@ int initf_malloc(void); /* Simple versions which can be used when space is tight */ void *malloc_simple(size_t size); +void *memalign_simple(size_t alignment, size_t bytes); #pragma GCC visibility push(hidden) # if __STD_C -- 2.17.1

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[U-Boot] [PATCH v2] spl: spl_nand.c: Add NAND loading message
by Stefan Roese 24 Apr '19

24 Apr '19

This patch adds a short message to the SPL NAND loader, which displays the source and destinations addresses including the size of the loaded image, like this: U-Boot SPL 2019.04-rc3-00113-g486efd8aaf (Mar 15 2019 - 14:18:02 +0100) Trying to boot from NAND Loading U-Boot from 0x00040000 (size 0x000a0000) to 0x22900000 I find this message quite helpful - hopefully others do so as well. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- v2: - Remove #idef as its not needed. With CONFIG_SPL_SERIAL_SUPPORT disabled, all printf's are removed automatically common/spl/spl_nand.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 6eb190f1ea..e2bcefb111 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -17,6 +17,10 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, { nand_init(); + printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n", + CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, + CONFIG_SYS_NAND_U_BOOT_DST); + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, (void *)CONFIG_SYS_NAND_U_BOOT_DST); -- 2.21.0

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[U-Boot] [PATCH v3 0/7] Add support for MT8516 SoC
by Fabien Parent 24 Apr '19

24 Apr '19

This patch series adds basic boot support on eMMC for the MediaTek MT8516 SoC based boards. This series adds the clock, pinctrl drivers and the SoC initialization code. Fabien Parent (7): mmc: mtk-sd: add source_cg clock support mmc: mtk-sd: add support for MT8516 mmc: mtk-sd: fix configuration option check clk: mediatek: add support for SETCLR_INV and NO_SETCLR flags clk: mediatek: add driver for MT8516 pinctrl: add driver for MT8516 ARM: MediaTek: Add support for MT8516 SoC arch/arm/dts/mt8516-u-boot.dtsi | 25 + arch/arm/dts/mt8516.dtsi | 136 +++++ arch/arm/mach-mediatek/Kconfig | 10 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8516/Makefile | 3 + arch/arm/mach-mediatek/mt8516/init.c | 120 ++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8516.c | 701 ++++++++++++++++++++++ drivers/clk/mediatek/clk-mtk.c | 12 + drivers/mmc/mtk-sd.c | 23 +- drivers/pinctrl/mediatek/Kconfig | 4 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8516.c | 391 ++++++++++++ include/dt-bindings/clock/mt8516-clk.h | 230 +++++++ 14 files changed, 1654 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/mt8516-u-boot.dtsi create mode 100644 arch/arm/dts/mt8516.dtsi create mode 100644 arch/arm/mach-mediatek/mt8516/Makefile create mode 100644 arch/arm/mach-mediatek/mt8516/init.c create mode 100644 drivers/clk/mediatek/clk-mt8516.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8516.c create mode 100644 include/dt-bindings/clock/mt8516-clk.h -- 2.20.1

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[U-Boot] [PATCH V2 1/8] led: add initial support for bcm6858
by Philippe Reynes 24 Apr '19

24 Apr '19

The driver add the support of the led IP on bcm6858. This led IP can drive up to 32 leds, and can handle blinking. Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- Changelog: v2: - use const for array bcm6858_flash_rate (thanks Daniel) - use int for array bcm6858_flash_rate (thanks Daniel) doc/device-tree-bindings/leds/leds-bcm6858.txt | 51 +++++ drivers/led/Kconfig | 7 + drivers/led/Makefile | 1 + drivers/led/led_bcm6858.c | 250 +++++++++++++++++++++++++ 4 files changed, 309 insertions(+) create mode 100644 doc/device-tree-bindings/leds/leds-bcm6858.txt create mode 100644 drivers/led/led_bcm6858.c diff --git a/doc/device-tree-bindings/leds/leds-bcm6858.txt b/doc/device-tree-bindings/leds/leds-bcm6858.txt new file mode 100644 index 0000000..ea2fe23 --- /dev/null +++ b/doc/device-tree-bindings/leds/leds-bcm6858.txt @@ -0,0 +1,51 @@ +LEDs connected to Broadcom BCM6858 controller + +This controller is present on BCM6858, BCM6328, BCM6362 and BCM63268. +In these SoCs it's possible to control LEDs both as GPIOs or by hardware. + +Required properties: + - compatible : should be "brcm,bcm6858-leds". + - #address-cells : must be 1. + - #size-cells : must be 0. + - reg : BCM6858 LED controller address and size. + +Optional properties: + - brcm,serial-led-msb-first : Boolean, msb data come out first on serial data pin + Default : false + - brcm,serial-led-en-pol : Boolean, serial led polarity (true => active high) + Default : false + - brcm,serial-led-clk-pol : Boolean, serial clock polarity (true => active high) + Default : false + - brcm,serial-led-data-ppol : Boolean, serial data polarity (true => active high) + Default : false + - brcm,serial-shift-inv : Boolean, led test mode + Default : false + +Each LED is represented as a sub-node of the brcm,bcm6858-leds device. + +LED sub-node required properties: + - reg : LED pin number (only LEDs 0 to 32 are valid). + +LED sub-node optional properties: + - label : see Documentation/devicetree/bindings/leds/common.txt + - active-low : Boolean, makes LED active low. + Default : false + +Examples: +BCM6328 with 2 GPIO LEDs + leds0: led-controller@ff800800 { + compatible = "brcm,bcm6858-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xff800800 0x0 0xe4>; + + led@2 { + reg = <2>; + label = "green:inet"; + }; + + led@5 { + reg = <5>; + label = "red:alarm"; + }; + }; diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 5da5c4a..4c8582d 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -28,6 +28,13 @@ config LED_BCM6358 LED HW controller accessed via MMIO registers. HW has no blinking capabilities and up to 32 LEDs can be controlled. +config LED_BCM6858 + bool "LED Support for BCM6858" + depends on LED && ARCH_BCM6858 + help + This option enables support for LEDs connected to the BCM6858 + HW has blinking capabilities and up to 32 LEDs can be controlled. + config LED_BLINK bool "Support LED blinking" depends on LED diff --git a/drivers/led/Makefile b/drivers/led/Makefile index 160a8f3..3654dd3 100644 --- a/drivers/led/Makefile +++ b/drivers/led/Makefile @@ -6,4 +6,5 @@ obj-y += led-uclass.o obj-$(CONFIG_LED_BCM6328) += led_bcm6328.o obj-$(CONFIG_LED_BCM6358) += led_bcm6358.o +obj-$(CONFIG_LED_BCM6858) += led_bcm6858.o obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o diff --git a/drivers/led/led_bcm6858.c b/drivers/led/led_bcm6858.c new file mode 100644 index 0000000..27a76fc --- /dev/null +++ b/drivers/led/led_bcm6858.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Philippe Reynes <philippe.reynes(a)softathome.com> + * + * based on: + * drivers/led/led_bcm6328.c + * drivers/led/led_bcm6358.c + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <led.h> +#include <asm/io.h> +#include <dm/lists.h> + +#define LEDS_MAX 32 +#define LEDS_WAIT 100 + +/* LED Mode register */ +#define LED_MODE_REG 0x0 +#define LED_MODE_OFF 0 +#define LED_MODE_ON 1 +#define LED_MODE_MASK 1 + +/* LED Controller Global settings register */ +#define LED_CTRL_REG 0x00 +#define LED_CTRL_MASK 0x1f +#define LED_CTRL_LED_TEST_MODE BIT(0) +#define LED_CTRL_SERIAL_LED_DATA_PPOL BIT(1) +#define LED_CTRL_SERIAL_LED_CLK_POL BIT(2) +#define LED_CTRL_SERIAL_LED_EN_POL BIT(3) +#define LED_CTRL_SERIAL_LED_MSB_FIRST BIT(4) + +/* LED Controller IP LED source select register */ +#define LED_HW_LED_EN_REG 0x08 +/* LED Flash control register0 */ +#define LED_FLASH_RATE_CONTROL_REG0 0x10 +/* Soft LED input register */ +#define LED_SW_LED_IP_REG 0xb8 +/* Soft LED input polarity register */ +#define LED_SW_LED_IP_PPOL_REG 0xbc + +struct bcm6858_led_priv { + void __iomem *regs; + u8 pin; +}; + +#ifdef CONFIG_LED_BLINK +/* + * The value for flash rate are: + * 0 : no blinking + * 1 : rate is 25 Hz => 40 ms (period) + * 2 : rate is 12.5 Hz => 80 ms (period) + * 3 : rate is 6.25 Hz => 160 ms (period) + * 4 : rate is 3.125 Hz => 320 ms (period) + * 5 : rate is 1.5625 Hz => 640 ms (period) + * 6 : rate is 0.7815 Hz => 1280 ms (period) + * 7 : rate is 0.390625 Hz => 2560 ms (period) + */ +static const int bcm6858_flash_rate[8] = { + 0, 40, 80, 160, 320, 640, 1280, 2560 +}; + +static u32 bcm6858_flash_rate_value(int period_ms) +{ + unsigned long value = 7; + int i; + + for (i = 0; i < ARRAY_SIZE(bcm6858_flash_rate); i++) { + if (period_ms <= bcm6858_flash_rate[i]) { + value = i; + break; + } + } + + return value; +} + +static int bcm6858_led_set_period(struct udevice *dev, int period_ms) +{ + struct bcm6858_led_priv *priv = dev_get_priv(dev); + u32 offset, shift, mask, value; + + offset = (priv->pin / 8) * 4; + shift = (priv->pin % 8) * 4; + mask = 0x7 << shift; + value = bcm6858_flash_rate_value(period_ms) << shift; + + clrbits_32(priv->regs + LED_FLASH_RATE_CONTROL_REG0 + offset, mask); + setbits_32(priv->regs + LED_FLASH_RATE_CONTROL_REG0 + offset, value); + + return 0; +} +#endif + +static enum led_state_t bcm6858_led_get_state(struct udevice *dev) +{ + struct bcm6858_led_priv *priv = dev_get_priv(dev); + enum led_state_t state = LEDST_OFF; + u32 sw_led_ip; + + sw_led_ip = readl(priv->regs + LED_SW_LED_IP_REG); + if (sw_led_ip & (1 << priv->pin)) + state = LEDST_ON; + + return state; +} + +static int bcm6858_led_set_state(struct udevice *dev, enum led_state_t state) +{ + struct bcm6858_led_priv *priv = dev_get_priv(dev); + + switch (state) { + case LEDST_OFF: + clrbits_32(priv->regs + LED_SW_LED_IP_REG, (1 << priv->pin)); +#ifdef CONFIG_LED_BLINK + bcm6858_led_set_period(dev, 0); +#endif + break; + case LEDST_ON: + setbits_32(priv->regs + LED_SW_LED_IP_REG, (1 << priv->pin)); +#ifdef CONFIG_LED_BLINK + bcm6858_led_set_period(dev, 0); +#endif + break; + case LEDST_TOGGLE: + if (bcm6858_led_get_state(dev) == LEDST_OFF) + return bcm6858_led_set_state(dev, LEDST_ON); + else + return bcm6858_led_set_state(dev, LEDST_OFF); + break; +#ifdef CONFIG_LED_BLINK + case LEDST_BLINK: + setbits_32(priv->regs + LED_SW_LED_IP_REG, (1 << priv->pin)); + break; +#endif + default: + return -EINVAL; + } + + return 0; +} + +static const struct led_ops bcm6858_led_ops = { + .get_state = bcm6858_led_get_state, + .set_state = bcm6858_led_set_state, +#ifdef CONFIG_LED_BLINK + .set_period = bcm6858_led_set_period, +#endif +}; + +static int bcm6858_led_probe(struct udevice *dev) +{ + struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev); + + /* Top-level LED node */ + if (!uc_plat->label) { + void __iomem *regs; + u32 set_bits = 0; + + regs = dev_remap_addr(dev); + if (!regs) + return -EINVAL; + + if (dev_read_bool(dev, "brcm,serial-led-msb-first")) + set_bits |= LED_CTRL_SERIAL_LED_MSB_FIRST; + if (dev_read_bool(dev, "brcm,serial-led-en-pol")) + set_bits |= LED_CTRL_SERIAL_LED_EN_POL; + if (dev_read_bool(dev, "brcm,serial-led-clk-pol")) + set_bits |= LED_CTRL_SERIAL_LED_CLK_POL; + if (dev_read_bool(dev, "brcm,serial-led-data-ppol")) + set_bits |= LED_CTRL_SERIAL_LED_DATA_PPOL; + if (dev_read_bool(dev, "brcm,led-test-mode")) + set_bits |= LED_CTRL_LED_TEST_MODE; + + clrsetbits_32(regs + LED_CTRL_REG, ~0, set_bits); + } else { + struct bcm6858_led_priv *priv = dev_get_priv(dev); + void __iomem *regs; + unsigned int pin; + + regs = dev_remap_addr(dev_get_parent(dev)); + if (!regs) + return -EINVAL; + + pin = dev_read_u32_default(dev, "reg", LEDS_MAX); + if (pin >= LEDS_MAX) + return -EINVAL; + + priv->regs = regs; + priv->pin = pin; + + /* this led is managed by software */ + clrbits_32(regs + LED_HW_LED_EN_REG, 1 << pin); + + /* configure the polarity */ + if (dev_read_bool(dev, "active-low")) + clrbits_32(regs + LED_SW_LED_IP_PPOL_REG, 1 << pin); + else + setbits_32(regs + LED_SW_LED_IP_PPOL_REG, 1 << pin); + } + + return 0; +} + +static int bcm6858_led_bind(struct udevice *parent) +{ + ofnode node; + + dev_for_each_subnode(node, parent) { + struct led_uc_plat *uc_plat; + struct udevice *dev; + const char *label; + int ret; + + label = ofnode_read_string(node, "label"); + if (!label) { + debug("%s: node %s has no label\n", __func__, + ofnode_get_name(node)); + return -EINVAL; + } + + ret = device_bind_driver_to_node(parent, "bcm6858-led", + ofnode_get_name(node), + node, &dev); + if (ret) + return ret; + + uc_plat = dev_get_uclass_platdata(dev); + uc_plat->label = label; + } + + return 0; +} + +static const struct udevice_id bcm6858_led_ids[] = { + { .compatible = "brcm,bcm6858-leds" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6858_led) = { + .name = "bcm6858-led", + .id = UCLASS_LED, + .of_match = bcm6858_led_ids, + .bind = bcm6858_led_bind, + .probe = bcm6858_led_probe, + .priv_auto_alloc_size = sizeof(struct bcm6858_led_priv), + .ops = &bcm6858_led_ops, +}; -- 2.7.4

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[U-Boot] [PATCH v4 0/4] Add Ethernet support for Poplar board
by Shawn Guo 24 Apr '19

24 Apr '19

The series adds Ethernet support for Poplar board. It firstly creates a reset driver for HiSilicon platform, then introduces higmacv300 Ethernet driver, and finally enables Ethernet support for Poplar board. Changes for v4: - Add a polarity field into struct reset_ctl. - Instead of defining custom macros for polarity, use generic ones in include/dt-bindings/reset/ti-syscon.h. - Use .data field as register offset and .id field as bit shift. Changes for v3: - Add polarity support into reset driver, so that we can drop the hacking on gmac reset sequence from higmacv300 driver. Changes for v2: - Rename driver symbol to HIGMACV300_ETH. - Remove the use of temp variable 'addr' in higmac_recv(). - Simplify the return of function higmac_ofdata_to_platdata() and higmac_probe(). - Combine delaration and initialization for phyintf in function higmac_ofdata_to_platdata(). - Eliminate the MDIO read/write macros. - Use wait_for_bit_le32() for MDIO command completion polling. - Set up RX packet buffers in RX_FQ descriptor at initialization time, so that we do not need to allocate/free packet buffers repeatedly. - Inform GMAC that the RX descriptor is no longer in use in function higmac_free_pkt(). - Define BITS_DESC_ENA instead of using magic number 0xf. Shawn Guo (4): reset: add polarity field into struct reset_ctl reset: add reset driver for HiSilicon platform net: add higmacv300 Ethernet driver for HiSilicon platform poplar: enable Ethernet driver support arch/arm/dts/hi3798cv200-u-boot.dtsi | 14 + configs/poplar_defconfig | 3 + drivers/net/Kconfig | 9 + drivers/net/Makefile | 1 + drivers/net/higmacv300.c | 597 +++++++++++++++++++++++++++ drivers/reset/Kconfig | 6 + drivers/reset/Makefile | 1 + drivers/reset/reset-hisilicon.c | 103 +++++ include/reset.h | 3 + 9 files changed, 737 insertions(+) create mode 100644 drivers/net/higmacv300.c create mode 100644 drivers/reset/reset-hisilicon.c -- 2.18.0

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[U-Boot] [PATCH] ARM: da850evm: Remove legacy MMC code
by Adam Ford 24 Apr '19

24 Apr '19

With the migration to DM in SPL and the DT support, the old legacy code is no longer neaded, so this patch removes it Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index e8ec553f99..1bc26828bf 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -204,25 +204,6 @@ int misc_init_r(void) return 0; } -#ifndef CONFIG_DM_MMC -#ifdef CONFIG_MMC_DAVINCI -static struct davinci_mmc mmc_sd0 = { - .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, - .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .version = MMC_CTLR_VERSION_2, -}; - -int board_mmc_init(bd_t *bis) -{ - mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); - - /* Add slot-0 to mmc subsystem */ - return davinci_mmc_init(bis, &mmc_sd0); -} -#endif -#endif - static const struct pinmux_config gpio_pins[] = { #ifdef CONFIG_USE_NOR /* GP0[11] is required for NOR to work on Rev 3 EVMs */ -- 2.17.1

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[U-Boot] [PATCH 1/2] pci: Add boundary check for hose->regions
by Thierry Reding 24 Apr '19

24 Apr '19

From: Thierry Reding <treding(a)nvidia.com> Make sure that we don't overflow the hose->regions array, otherwise we would end up overwriting the hose->region_count field and cause mayhem to ensue. Also print an error message when we'd be overflowing because it indicates that there aren't enough regions available and the number needs to be increased. Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- drivers/pci/pci-uclass.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 824fa1190747..cf1e7617ae35 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -918,6 +918,11 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, return; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (hose->region_count == MAX_PCI_REGIONS) { + pr_err("maximum number of regions parsed, aborting\n"); + break; + } + if (bd->bi_dram[i].size) { pci_set_region(hose->regions + hose->region_count++, bd->bi_dram[i].start, -- 2.20.1

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[U-Boot] [PATCH 00/18] Initial support of driver brcmnand (from kernel 4.18)
by Philippe Reynes 24 Apr '19

24 Apr '19

This serie is a port the support of driver brcmnand from kernel 4.18 to u-boot. I've tried to stay as close as possible to the kernel. In this first port, I haven't ported the support of DMA, it's not mandatory in the first step and it could be added later. This code has been tested on bcm6838 (mips), bcm63158 (arm) and bcm6858 (arm64). In the code, I've used "#ifndef __UBOOT__" to show the difference between the kernel code. I've also added a file brcmnand_compat.[hc] to compat function with the kernel (for example devm_clk_get). Changes in v1: - define less function in brcmnand_compat.c/h and add more #ifndef __UBOOT__ - port completion.h (function stubbed) from kernel 4.18 - define devm_ioremap for everybody - remove duplicate SoB - update text commit - add support of bcm63158 Boris Brezillon (1): mtd: nand: provide several helpers to do common NAND operations Brian Norris (1): mtd: add get/set of_node/flash_node helpers Marc Gonzalez (1): mtd: nand: import nand_hw_control_init() Philippe Reynes (15): arm: asm: io.h: define readX_relaxed and writeX_relaxed include: linux: io: define devm_ioremap on board with ioremap compat linux: import completion from linux 4.18 drivers: nand: brcmnand: add initial support drivers: nand: brcmnand: add parameter parameter-page-big-endian drivers: nand: brcmnand: add an option to read the write-protect from device tree dt: bcm6838: add nand controller dt: bcm968380gerg: enable nand controller bcm968380gerg: add nand support dt: bcm6858: add nand controller dt: bcm968580xref: enable nand controller bcm968580xref: add nand support dt: bcm63158: add nand controller dt: bcm963158: enable nand controller bcm963158: add nand support arch/arm/dts/bcm63158.dtsi | 13 + arch/arm/dts/bcm6858.dtsi | 13 + arch/arm/dts/bcm963158.dts | 15 + arch/arm/dts/bcm968580xref.dts | 15 + arch/arm/include/asm/io.h | 21 + arch/mips/dts/brcm,bcm6838.dtsi | 13 + arch/mips/dts/brcm,bcm968380gerg.dts | 12 + configs/bcm963158_ram_defconfig | 6 + configs/bcm968380gerg_ram_defconfig | 7 + configs/bcm968580xref_ram_defconfig | 7 + drivers/mtd/nand/raw/Kconfig | 25 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/brcmnand/Makefile | 7 + drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c | 123 + drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c | 122 + drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c | 123 + drivers/mtd/nand/raw/brcmnand/brcmnand.c | 2805 +++++++++++++++++++++++ drivers/mtd/nand/raw/brcmnand/brcmnand.h | 63 + drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c | 66 + drivers/mtd/nand/raw/brcmnand/brcmnand_compat.h | 15 + drivers/mtd/nand/raw/nand_base.c | 1013 ++++++-- include/configs/broadcom_bcm963158.h | 7 + include/configs/broadcom_bcm968380gerg.h | 7 + include/configs/broadcom_bcm968580xref.h | 7 + include/linux/completion.h | 173 ++ include/linux/io.h | 2 +- include/linux/mtd/rawnand.h | 49 + 27 files changed, 4569 insertions(+), 161 deletions(-) create mode 100644 drivers/mtd/nand/raw/brcmnand/Makefile create mode 100644 drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c create mode 100644 drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c create mode 100644 drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c create mode 100644 drivers/mtd/nand/raw/brcmnand/brcmnand.c create mode 100644 drivers/mtd/nand/raw/brcmnand/brcmnand.h create mode 100644 drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c create mode 100644 drivers/mtd/nand/raw/brcmnand/brcmnand_compat.h create mode 100644 include/linux/completion.h -- 2.7.4

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[U-Boot] [PATCH v2] arm: arm64 32bit address relocation
by Ibai Erkiaga 24 Apr '19

24 Apr '19

Current relocation code is limited to 21bit PC-relative addressing which might not be enough for bigger code sizes. The following patch increases the addressing to 32bit PC-relative. This feature is specially interesting if U-Boot is build without optimiation (-O0) as the text section is increased significativelly. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza(a)xilinx.com> --- Changes in v2: - Fixed register name on comments arch/arm/lib/relocate_64.S | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index 7603f52..26d29c5 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -26,9 +26,10 @@ ENTRY(relocate_code) /* * Copy u-boot from flash to RAM */ - adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */ - subs x9, x0, x1 /* x8 <- Run to copy offset */ - b.eq relocate_done /* skip relocation */ + adrp x1, __image_copy_start /* x1 <- address bits [31:12] */ + add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */ + subs x9, x0, x1 /* x9 <- Run to copy offset */ + b.eq relocate_done /* skip relocation */ /* * Don't ldr x1, __image_copy_start here, since if the code is already * running at an address other than it was linked to, that instruction @@ -42,8 +43,10 @@ ENTRY(relocate_code) ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */ subs x9, x0, x1 /* x9 <- Link to copy offset */ - adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */ - adr x2, __image_copy_end /* x2 <- Run &__image_copy_end */ + adrp x1, __image_copy_start /* x1 <- address bits [31:12] */ + add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */ + adrp x2, __image_copy_end /* x2 <- address bits [31:12] */ + add x2, x2, :lo12:__image_copy_end /* x2 <- address bits [11:00] */ copy_loop: ldp x10, x11, [x1], #16 /* copy from source address [x1] */ stp x10, x11, [x0], #16 /* copy to target address [x0] */ @@ -54,8 +57,10 @@ copy_loop: /* * Fix .rela.dyn relocations */ - adr x2, __rel_dyn_start /* x2 <- Run &__rel_dyn_start */ - adr x3, __rel_dyn_end /* x3 <- Run &__rel_dyn_end */ + adrp x2, __rel_dyn_start /* x2 <- address bits [31:12] */ + add x2, x2, :lo12:__rel_dyn_start /* x2 <- address bits [11:00] */ + adrp x3, __rel_dyn_end /* x3 <- address bits [31:12] */ + add x3, x3, :lo12:__rel_dyn_end /* x3 <- address bits [11:00] */ fixloop: ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */ ldr x4, [x2], #8 /* x4 <- addend */ -- 1.8.3.1

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