March 2019 - U-Boot

[U-Boot] [PATCH] mmc: sh_mmcif: Set default MMCIF clock rate
by Marek Vasut 18 Mar '19

18 Mar '19

Set MMCIF clock rate to 97.5 MHz, which is the default according to Gen2 datasheet. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/sh_mmcif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 306daf1415..c8875ce8f8 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -696,7 +696,7 @@ static int sh_mmcif_dm_probe(struct udevice *dev) return ret; } - host->clk = clk_get_rate(&sh_mmcif_clk); + host->clk = clk_set_rate(&sh_mmcif_clk, 97500000); plat->cfg.name = dev->name; plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; -- 2.20.1

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[U-Boot] [PATCH 1/3] clk: renesas: Fix SDH clock divider decoding on Gen2
by Marek Vasut 18 Mar '19

18 Mar '19

The gen2_clk_get_sdh_div() function is supposed to look up the $val value read out of the SDCKCR register in the supplied table and return the matching divider value. The current implementation was matching the value from SDCKCR on the divider value in the table, which is wrong. Fix this and rework the function a bit to make it more readable. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/clk/renesas/clk-rcar-gen2.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 6dfd02f2eb..aedaab723b 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -44,13 +44,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = { { 0, 0 }, }; -static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div) +static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val) { - while ((*table++).val) { - if ((*table).div == div) - return div; + for (;;) { + if (!(*table).div) + return 0xff; + + if ((*table).val == val) + return (*table).div; + + table++; } - return 0xff; } static int gen2_clk_enable(struct clk *clk) -- 2.20.1

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[U-Boot] [PATCH] cmd: mmc: Make Mode: printout consistent
by Marek Vasut 18 Mar '19

18 Mar '19

The "Mode :" line is the only one in "mmc info" output that has a space in front of the colon. Drop the space to make it consistent with the rest of the output, e.g.: => mmc dev 1 ; mmc info switch to partitions #0, OK mmc1 is current device Device: sd@ee160000 Manufacturer ID: 3 OEM: 5344 Name: SL08G Bus Speed: 50000000 Mode : SD High Speed (50MHz) ^------------------------------ Remove this space Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 7.4 GiB Bus Width: 1-bit Erase Group Size: 512 Bytes Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> CC: Tom Rini <trini(a)konsulko.com> --- cmd/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/mmc.c b/cmd/mmc.c index 8bc3648193..6f3cb85cc0 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -26,7 +26,7 @@ static void print_mmcinfo(struct mmc *mmc) printf("Bus Speed: %d\n", mmc->clock); #if CONFIG_IS_ENABLED(MMC_VERBOSE) - printf("Mode : %s\n", mmc_mode_name(mmc->selected_mode)); + printf("Mode: %s\n", mmc_mode_name(mmc->selected_mode)); mmc_dump_capabilities("card capabilities", mmc->card_caps); mmc_dump_capabilities("host capabilities", mmc->host_caps); #endif -- 2.20.1

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[U-Boot] [PATCH] ARM: dts: rmobile: Increase off-on delay on the SD Vcc regulator
by Marek Vasut 18 Mar '19

18 Mar '19

An ADATA 16GB Industrial MLC card has so much capacitance on the Vcc pin that the usual toggling of regulator to power the card off and on is insufficient. When the card is calibrated into UHS SDR104 mode, it will remain in that mode across the power cycle and subsequent attempt to communicate with the card will fail. The test with this card is to insert it into an SDHI slot and perform "mmc dev 0 ; mmc dev 0", where the second "mmc dev 0" will fail. Fix this problem by increasing the off-on delay from 0 to 20 mS. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/arm/dts/r8a7795-h3ulcb-u-boot.dts | 4 ++++ arch/arm/dts/r8a7795-salvator-x-u-boot.dts | 8 ++++++++ arch/arm/dts/r8a7796-m3ulcb-u-boot.dts | 4 ++++ arch/arm/dts/r8a7796-salvator-x-u-boot.dts | 8 ++++++++ arch/arm/dts/r8a77965-salvator-x-u-boot.dts | 8 ++++++++ arch/arm/dts/r8a77990-ebisu-u-boot.dts | 2 ++ 6 files changed, 34 insertions(+) diff --git a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts index 4f5410f1e8..3c8b011b3f 100644 --- a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts @@ -19,6 +19,10 @@ }; }; +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts index 8ad21ca4f9..8e08e05cf2 100644 --- a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts @@ -8,6 +8,14 @@ #include "r8a7795-salvator-x.dts" #include "r8a7795-u-boot.dtsi" +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + +&vcc_sdhi3 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts index 843be4b67e..dd9e518ac7 100644 --- a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts @@ -19,6 +19,10 @@ }; }; +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts index 7614a810b6..be657a9f07 100644 --- a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts @@ -8,6 +8,14 @@ #include "r8a7796-salvator-x.dts" #include "r8a7796-u-boot.dtsi" +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + +&vcc_sdhi3 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts index bd32a25409..efa122203e 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts @@ -8,6 +8,14 @@ #include "r8a77965-salvator-x.dts" #include "r8a77965-u-boot.dtsi" +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + +&vcc_sdhi3 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts index e31b602630..27cfdab22c 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -36,6 +36,7 @@ gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; enable-active-high; + u-boot,off-on-delay-us = <20000>; }; vccq_sdhi0: regulator-vccq-sdhi0 { @@ -60,6 +61,7 @@ gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; enable-active-high; + u-boot,off-on-delay-us = <20000>; }; vccq_sdhi1: regulator-vccq-sdhi1 { -- 2.20.1

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[U-Boot] Pull request for UEFI system for v2019.04-rc4
by Heinrich Schuchardt 17 Mar '19

17 Mar '19

The following changes since commit e8e3f2d2d48f97b2c79b698eccedce8f4f880993: Merge branch '2019-03-08-master-imports' (2019-03-08 18:04:13 -0500) are available in the Git repository at: https://github.com/xypron2/u-boot tag efi-2019-04-rc4-3 for you to fetch changes up to e616100eab84464f09baa93b3fe5c15087a385c1: efi_loader: fix build error for freestanding.o (2019-03-14 21:03:14 +0100) Primary key fingerprint: 6DC4 F9C7 1F29 A6FA 06B7 6D33 C481 DBBC 2C05 1AC4 Fix an error with the serial communication on boards with a very small UART buffer which leads to a stalled system. Provide an X86 reset driver for the UEFI runtime. Fix a problem with parallel builds. Travis CI looks fine: https://travis-ci.org/xypron2/u-boot/builds/506462986 ---------------------------------------------------------------- Alexander Graf (1): x86: Add efi runtime reset Heinrich Schuchardt (1): efi_loader: fix build error for freestanding.o Matthias Brugger (1): efi_loader: Fix serial console size detection drivers/sysreset/sysreset_x86.c | 23 ++++++++++++++++++++++- lib/efi_loader/efi_console.c | 62 +++++++++++++++++++++++++++++++++++--------------------------- lib/efi_selftest/efi_freestanding.c | 11 +++++++++++ scripts/Makefile.lib | 2 +- 4 files changed, 69 insertions(+), 29 deletions(-) create mode 100644 lib/efi_selftest/efi_freestanding.c

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[U-Boot] Please pull u-boot-fsl-qoriq master
by Prabhakar Kushwaha 17 Mar '19

17 Mar '19

Hi Tom, The following changes since commit 9ba5e5bc261a16f51662490da0cf620dc7f29013: Revert "env: add spi_flash_read_env function" (2019-03-13 20:32:09 -0400) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git HEAD for you to fetch changes up to 158097052a6a528408e05d2345ff2ccdbb46036e: armv7: ls102xa: Add workaround for DDR erratum A-008850 (2019-03-15 11:52:01 +0530) Travis build log is https://travis-ci.org/prabhukush/u-boot/builds/506626436 Changes from rc4 tag - DPAA2 fixes and DDR errata workaround for LS1021A ---------------------------------------------------------------- Alison Wang (1): armv7: ls102xa: Add workaround for DDR erratum A-008850 Ioana Ciocoi Radulescu (1): driver: net: fsl-mc: Fix DPC MAC address fixup Meenakshi Aggarwal (1): mc : Reduce MC memory size to 128M Pankaj Bansal (2): drivers: net: ldpaa_eth: check if the dpmac is enabled board: fsl: lx2160aqds: modify the phy fixup code Pramod Kumar (1): drivers: net: ls1088ardb: Fix EC1 and EC2 RCW offset arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++ arch/arm/cpu/armv7/ls102xa/soc.c | 44 +++++++++++++++++++++---- arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 2 ++ board/freescale/ls1021aiot/ls1021aiot.c | 2 ++ board/freescale/ls1021aqds/ddr.c | 2 ++ board/freescale/ls1021aqds/ddr.h | 3 ++ board/freescale/ls1021aqds/ls1021aqds.c | 30 ----------------- board/freescale/ls1021atwr/ls1021atwr.c | 2 ++ board/freescale/lx2160a/eth_lx2160aqds.c | 38 +++++++++++++++++---- drivers/net/fsl-mc/mc.c | 26 ++++++++++++--- drivers/net/ldpaa_eth/ls1088a.c | 4 +-- drivers/net/ldpaa_eth/lx2160a.c | 4 +-- include/configs/ls1021aiot.h | 2 ++ include/configs/ls1021atwr.h | 2 ++ include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 2 +- 17 files changed, 117 insertions(+), 56 deletions(-) --prabhakar (pk)

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[U-Boot] [PATCH] arm: socfpga: make SPL_TEXT_BASE overridable
by Simon Goldschmidt 17 Mar '19

17 Mar '19

To boot from fpga on socfpga gen5, we need to set CONFIG_SPL_TEXT_BASE to 0xC0000000 (hps2fpgaslaves base address). Since converting CONFIG_SPL_TEXT_BASE to Kconfig hasn't been successful so far, let's make this value overridable in socfpga_common.h, so that we can have different board configs override this in socfpga_common.h. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 181af9b646..191204b27b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -248,8 +248,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * 0xFFEz_zzzz ...... Malloc area (grows up to top) * 0xFFE3_FFFF ...... End of SRAM (top) */ +#ifndef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#endif #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) /* SPL memory allocation configuration, this is for FAT implementation */ -- 2.17.1

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[U-Boot] passing info from SPL to U-Boot
by Heiko Schocher 17 Mar '19

17 Mar '19

Hello Simon, Tom, I am just stumbeld on an am437x basd board over the problem to pass the bootmode from SPL to U-Boot. On am437x the bootmode info get overwritten from SPL stack, and I need this info in U-Boot. Hack would be to move SPL stack to another address, but we loose than 0xa000 size for stack ... I do not want to go this way.. I thought gd info is passed from SPL to U-Boot, but this is not the case! Looking into ... 75 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ 76 mov sp, r0 77 bl board_init_f_alloc_reserve 78 mov sp, r0 79 /* set up gd here, outside any C code */ 80 mov r9, r0 81 bl board_init_f_init_reserve and common/init/board_init.c: 99 void board_init_f_init_reserve(ulong base) 100 { 101 struct global_data *gd_ptr; 102 103 /* 104 * clear GD entirely and set it up. 105 * Use gd_ptr, as gd may not be properly set yet. 106 */ 107 108 gd_ptr = (struct global_data *)base; 109 /* zero the area */ 110 memset(gd_ptr, '\0', sizeof(*gd)); 111 /* set GD unless architecture did it already */ 112 #if !defined(CONFIG_ARM) 113 arch_setup_gd(gd_ptr); 114 #endif gd is always initialized with zeros, no chance for passing infos from SPL to U-Boot... I really thought, that gd_t was intentionally designed for passing data between different U-Boot states, but looking into gd_t definiton in include/asm-generic/global_data.h it is a big ifdef mess and not useable as an "API" between TPL/SPL and U-Boot ... I thought also, that SPL detects for example ramsize and than passes this info to U-Boot ... But Ok, I found "common/init/handoff.c" which seems now the way to go, but: ./common/board_f.c 281 static int setup_spl_handoff(void) 282 { 283 #if CONFIG_IS_ENABLED(HANDOFF) 284 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF, 285 sizeof(struct spl_handoff)); 286 debug("Found SPL hand-off info %p\n", gd->spl_handoff); 287 #endif 288 289 return 0; 290 } There is gd->spl_handoff used ... how could this work at least on arm, if gd is set to zeros on init ? Do I miss something obvious? bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs(a)denx.de

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[U-Boot] [PATCH] test/py: Fix pytest4 deprecation warnings
by Marek Vasut 17 Mar '19

17 Mar '19

Fix the following spit from pytest: u-boot/test/py/conftest.py:438: RemovedInPytest4Warning: MarkInfo objects are deprecated as they contain merged marks which are hard to deal with correctly. Please use node.get_closest_marker(name) or node.iter_markers(name). Docs: https://docs.pytest.org/en/latest/mark.html#updating-code for board in mark.args: In both cases, the later suggestion is applicable. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Igor Opaniuk <igor.opaniuk(a)linaro.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> --- test/py/conftest.py | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/test/py/conftest.py b/test/py/conftest.py index e40cbf0ba1..745ca5ac4a 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -431,11 +431,9 @@ def setup_boardspec(item): Nothing. """ - mark = item.get_marker('boardspec') - if not mark: - return required_boards = [] - for board in mark.args: + for boards in item.iter_markers('boardspec'): + board = boards.args[0] if board.startswith('!'): if ubconfig.board_type == board[1:]: pytest.skip('board "%s" not supported' % ubconfig.board_type) @@ -459,10 +457,8 @@ def setup_buildconfigspec(item): Nothing. """ - mark = item.get_marker('buildconfigspec') - if not mark: - return - for option in mark.args: + for options in item.iter_markers('buildconfigspec'): + option = options.args[0] if not ubconfig.buildconfig.get('config_' + option.lower(), None): pytest.skip('.config feature "%s" not enabled' % option.lower()) -- 2.20.1

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[U-Boot] Clearfog Base PCI-E not working
by Влад Мао 16 Mar '19

16 Mar '19

I found mismatched entries in DTS: In armada-388-clearfog.dts: pcie-controller { status = "okay"; But in armada-385.dtsi we have: pciec: pcie { compatible = "marvell,armada-370-pcie"; After fixing it, PCIE does show up as expected.

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