March 2019 - U-Boot

[U-Boot] mpc85xx, mpc86xx: device tree model
by Prabhakar Kushwaha 18 Mar '19

18 Mar '19

Hi Tom, I am seeing following type of build warnings for MMC. +===================== WARNING ====================== +This board does not use CONFIG_DM_MMC. Please update +the board to use CONFIG_DM_MMC before the v2019.04 release. +Failure to update by the deadline may result in board removal. +See doc/driver-model/MIGRATION.txt for more info. Considering "number" of powerpc platform are not migrated to deice tree. They can not be migrated to CONFIG_DM_MMC withing v2019.04 time-frame (considering rc4 is on 18th march). v2019.07 looks feasible for removing all warning which includes CONFIG_DM_USB, CONFIG_DM_SCSI, CONFIG_DM_PCI, CONFIG_DM_SPI_FLASH and CONFIG_DM_MMC. is there any plan of removing boards which don't have CONFIG_DM_MMC for v2019.04? --prabhakar (pk)

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[U-Boot] [PATCH v2] usb: host: Print device name when scanning
by Ismael Luceno Cortes 18 Mar '19

18 Mar '19

The name assigned to the USB host controller interface is a better indicator than the counter currently in use (which has no meaning other than being the order in which the interface is found). Example of the original output: > USB0: USB EHCI 1.10 > scanning bus 0 for devices... 2 USB Device(s) found > scanning usb for storage devices... 1 Storage Device(s) found Patched output: > USB0(usb@ee080100): USB EHCI 1.10 > scanning bus 0 for devices... 2 USB Device(s) found > scanning usb for storage devices... 1 Storage Device(s) found Signed-off-by: Ismael Luceno <ismael.luceno(a)silicon-gears.com> --- Notes: Changes since v1: - Improved commit message. drivers/usb/host/usb-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 611ea97a72..0575f5393b 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -255,7 +255,7 @@ int usb_init(void) uclass_foreach_dev(bus, uc) { /* init low_level USB */ - printf("USB%d: ", count); + printf("USB%d(%s): ", count, bus->name); count++; #ifdef CONFIG_SANDBOX base-commit: 9ba5e5bc261a16f51662490da0cf620dc7f29013 -- 2.19.1

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[U-Boot] [PATCH 1/2] rockchip: chromebook_minnie: Enable sound
by Simon Glass 18 Mar '19

18 Mar '19

Enable sound for this board, which has the same codec as jerry. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/arm/dts/rk3288-veyron-minnie.dts | 12 ++++++++++++ configs/chromebook_minnie_defconfig | 5 +++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts index 0a2915fba09..646f6ae7424 100644 --- a/arch/arm/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/dts/rk3288-veyron-minnie.dts @@ -85,6 +85,18 @@ regulator-boot-on; vin-supply = <&vcc18_wl>; }; + + sound { + compatible = "rockchip,audio-max98090-jerry"; + + cpu { + sound-dai = <&i2s 0>; + }; + + codec { + sound-dai = <&max98090 0>; + }; + }; }; &backlight { diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index b0428740736..93e40c02101 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -75,6 +76,10 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SERIAL=y +CONFIG_SOUND=y +CONFIG_I2S=y +CONFIG_I2S_ROCKCHIP=y +CONFIG_SOUND_MAX98090=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y -- 2.20.1.415.g653613c723-goog

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[U-Boot] [PATCH] usb: host: Print device name when scanning
by Ismael Luceno Cortes 18 Mar '19

18 Mar '19

Signed-off-by: Ismael Luceno <ismael.luceno(a)silicon-gears.com> --- drivers/usb/host/usb-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 611ea97a72..0575f5393b 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -255,7 +255,7 @@ int usb_init(void) uclass_foreach_dev(bus, uc) { /* init low_level USB */ - printf("USB%d: ", count); + printf("USB%d(%s): ", count, bus->name); count++; #ifdef CONFIG_SANDBOX -- 2.19.1

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[U-Boot] [PATCH v3] cmd: clk: Handle ENODEV from clk_get_rate
by Ismael Luceno Cortes 18 Mar '19

18 Mar '19

clk_get_rate may return -ENODEV if the clock isn't valid. Also, make the error cases go through a single path. Fixes: ff8eee0330a6 ("cmd: clk: Add trivial implementation of clock dump for DM") Signed-off-by: Ismael Luceno <ismael.luceno(a)silicon-gears.com> Reviewed-by: Matthias Brugger <mbrugger(a)suse.com> --- CC: Matthias Brugger <mbrugger(a)suse.com> Notes: Changes since v2: - Further improved commit message. Changes since v1: - Added further explanation to the commit message. cmd/clk.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/cmd/clk.c b/cmd/clk.c index fd4231589c..41f2ae0a50 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -26,20 +26,23 @@ int __weak soc_clk_dump(void) uclass_foreach_dev(dev, uc) { memset(&clk, 0, sizeof(clk)); ret = device_probe(dev); - if (ret) { - printf("%-30.30s : ? Hz\n", dev->name); - continue; - } + if (ret) + goto noclk; ret = clk_request(dev, &clk); - if (ret) { - printf("%-30.30s : ? Hz\n", dev->name); - continue; - } - - printf("%-30.30s : %lu Hz\n", dev->name, clk_get_rate(&clk)); + if (ret) + goto noclk; + ulong rate = clk_get_rate(&clk); clk_free(&clk); + + if (rate == -ENODEV) + goto noclk; + + printf("%-30.30s : %lu Hz\n", dev->name, rate); + continue; + noclk: + printf("%-30.30s : ? Hz\n", dev->name); } return 0; -- 2.19.1

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[U-Boot] [PATCH 0/3] PSCI support for r8a7790 SoC (Lager/Stout boards)
by Oleksandr Tyshchenko 18 Mar '19

18 Mar '19

From: Oleksandr Tyshchenko <oleksandr_tyshchenko(a)epam.com> Hi, all. The purpose of this patch series is to add PSCI support for Renesas boards based on R-Car Gen2 r8a7790 SoC. Actually, our target in Stout board, but as Lager board is also based on the same SoC, that patch series covers both. The main goal of using PSCI is to have common interface to boot CPUs from Hypervisor/Linux. PSCI is a generic well-known way to bring-up CPU and proven to work. With this patch series applied all CPUs will be switched to a non-secure Hypervisor mode. For running Type 1 Hypervisor (e.g. Xen) it is mandatory requirement. From other side, there are recommendation to boot Linux in Hypervisor mode on ARM. This allows KVM or other Hypervisor (e.g. Jailhouse) to be useable on the platform. If there are no Hypervisor present, Linux will just initialize the Hypervisor mode correctly and drop to Supervisor mode. Till now, we have been using a *custom solution* for running Xen Hypervisor on Lager/Stout boards, which requires a specific U-Boot version (which performs СPUs boot in a non-generic way) and different hacks into R-Car Gen2 platform code in Linux. We have a situation where different methods are used in order to boot CPUs from Xen/Linux. Which results in a forced switching between different U-Boot versions, when we need to switch between bare Linux and Xen, which is quite inconvenient. This should be totally transparent to the user. ---------- Current patch series is based on the following commit: 425c0a43fbbec36571f6a03b530695b8b16a841d “Prepare v2019.01-rc3” It was tested with bare Linux 5.0.0-rc3 and Xen 4.12.0-rc with Linux 5.0.0-rc3 as guest OS. Everything worked as expected. In case of bare Linux, all CPU cores started in HYP mode and PSCI checker confirmed that hotplug tests had successfully passed. Just one note. For each secondary CPU boot, Linux complains about “Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable”. Probably because the corresponding ARM errata (CONFIG_ARM_CORTEX_A15_CVE_2017_5715, etc) is not propagated to non-boot (secondary) CPUs. You can also find patch series here (last 3 patches): https://github.com/otyshchenko1/u-boot/commits/r8a7790_psci_upstream ---------- Please note: 1. Current patch series implies corresponding changes to Linux. You can find them here (last 2 patches): https://github.com/otyshchenko1/linux/commits/psci_upstream I am about to push them as well. 2. As PSCI code expects a bigger “Maximum supported CPUs for PSCI” value (8) than default option (4), you will get a compilation error: arch/arm/mach-rmobile/psci.c:21:2: error: #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" To resolve it, just run make menuconfig, set this option to 8 (or change in .config directly) and recompile. ---------- Oleksandr Tyshchenko (3): ARM: rmobile: Switch CPU to non-secure HYP mode for r8a7790 based boards ARM: rmobile: Add basic PSCI support for r8a7790 SoC ARM: rmobile: Add possibility to debug main PSCI commands arch/arm/mach-rmobile/Kconfig.32 | 6 + arch/arm/mach-rmobile/Makefile | 6 + arch/arm/mach-rmobile/debug.h | 91 +++++++++ arch/arm/mach-rmobile/pm-r8a7790.c | 408 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-rmobile/pm-r8a7790.h | 72 +++++++ arch/arm/mach-rmobile/psci.c | 216 ++++++++++++++++++++ board/renesas/lager/lager.c | 51 +++++ board/renesas/stout/stout.c | 51 +++++ include/configs/lager.h | 5 + include/configs/stout.h | 5 + 10 files changed, 911 insertions(+) create mode 100644 arch/arm/mach-rmobile/debug.h create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.c create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.h create mode 100644 arch/arm/mach-rmobile/psci.c -- 2.7.4

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[U-Boot] [U-BOOT][PATCH V3] sunxi: Use clrsetbits_le32 instead of multiple instruction
by Shyam Saini 18 Mar '19

18 Mar '19

From: Michael Trimarchi <michael(a)amarulasolutions.com> This will improve code readabilty Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- Changelogs: V1->V2: None V2->V3: Fix use of clrsetbits_le32 and setbits_le32 functions --- arch/arm/mach-sunxi/dram_sun8i_a33.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index 1da2727f9874..09742cbc2b55 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -148,11 +148,8 @@ static void auto_set_timing_para(struct dram_para *para) reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); writel(reg_val, &mctl_ctl->dramtmg5); /* Set two rank timing and exit self-refresh timing */ - reg_val = readl(&mctl_ctl->dramtmg8); - reg_val &= ~(0xff << 8); - reg_val &= ~(0xff << 0); - reg_val |= (0x33 << 8); - reg_val |= (0x8 << 0); + clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0)); + setbits_le32(&mctl_ctl->dramtmg8, (0x33 << 8) | (0x8 << 0)); writel(reg_val, &mctl_ctl->dramtmg8); /* Set phy interface time */ reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) -- 2.11.0

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[U-Boot] [PATCH] ARM: kirkwood: disable dcache for Kirkwood boards
by Chris Packham 18 Mar '19

18 Mar '19

Prior to commit 93b283d49f93 ("ARM: CPU: arm926ejs: Consolidate cache routines to common file") the kirkwood boards didn't have and dcache support. The network and usb drivers rely on this. Set CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h. Reported-by: Leigh Brown <leigh(a)solinno.co.uk> Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- arch/arm/mach-kirkwood/include/mach/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index fcd903887bff..3a4014e308b3 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -26,6 +26,7 @@ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ +#define CONFIG_SYS_DCACHE_OFF /* Disable data cache */ /* * By default kwbimage.cfg from board specific folder is used -- 2.21.0

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[U-Boot] [PATCH] arm: kirkwood: lsxl: disable dcache
by Michael Walle 18 Mar '19

18 Mar '19

Both the network as well as the USB driver are not working with the data cache enabled. Signed-off-by: Michael Walle <michael(a)walle.cc> --- include/configs/lsxl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 9d4be18413..728263910e 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -32,6 +32,7 @@ #define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_KIRKWOOD_GPIO +#define CONFIG_SYS_DCACHE_OFF /* * Commands configuration -- 2.11.0

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Re: [U-Boot] [PATCH v3 05/11] riscv: save hart ID in register tp instead of s0
by Rick Chen 18 Mar '19

18 Mar '19

> > From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > > Sent: Monday, March 18, 2019 2:29 AM > > To: u-boot(a)lists.denx.de > > Cc: Anup Patel; Andreas Schwab; Bin Meng; Atish Patra; Palmer Dabbelt; Lukas > > Auer; Atish Patra; Anup Patel; Rick Jian-Zhi Chen(陳建志) > > Subject: [PATCH v3 05/11] riscv: save hart ID in register tp instead of s0 > > > > The hart ID passed by the previous boot stage is currently stored in register s0. If > > we divert the control flow inside a function, which is required as part of > > multi-hart support, the function epilog may not be called, clobbering register s0. > > Save the hart ID in the unallocatable register tp instead to protect the hart ID. > > > > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > > --- > > > > Changes in v3: > > - New patch to save the hart ID in register tp instead of s0 > > > > Changes in v2: None > > > > arch/riscv/cpu/start.S | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index > > a30f6f7194..bcc0ff696d 100644 > > --- a/arch/riscv/cpu/start.S > > +++ b/arch/riscv/cpu/start.S > > @@ -36,7 +36,7 @@ > > .globl _start > > _start: > > /* save hart id and dtb pointer */ > > - mv s0, a0 > > + mv tp, a0 > > mv s1, a1 > > > > la t0, trap_entry > > @@ -64,7 +64,7 @@ call_board_init_f_0: > > jal board_init_f_init_reserve > > > > /* save the boot hart id to global_data */ > > - SREG s0, GD_BOOT_HART(gp) > > + SREG tp, GD_BOOT_HART(gp) > > > > /* Enable cache */ > > jal icache_enable Reviewed-by: Rick Chen <rick(a)andestech.com>

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