March 2019 - U-Boot

[U-Boot] [PATCH] rsa: check that pointer checksum isn't NULL before using it
by Philippe Reynes 25 Mar '19

25 Mar '19

The pointer checksum were used before checking that it isn't NULL. We move the code that use it after the check. Reported-by: Coverity (CID: 185835) Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- lib/rsa/rsa-verify.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 9734f6d..287fcc4 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -295,7 +295,7 @@ static int rsa_verify_key(struct image_sign_info *info, #endif struct checksum_algo *checksum = info->checksum; struct padding_algo *padding = info->padding; - int hash_len = checksum->checksum_len; + int hash_len; if (!prop || !sig || !hash || !checksum) return -EIO; @@ -315,6 +315,7 @@ static int rsa_verify_key(struct image_sign_info *info, } uint8_t buf[sig_len]; + hash_len = checksum->checksum_len; #if !defined(USE_HOSTCC) ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); -- 2.7.4

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[U-Boot] [PATCH] Revert "cmd: Kconfig: Do not include EEPROM if DM_I2C is used without DM_I2C_COMPAT"
by Simon Goldschmidt 25 Mar '19

25 Mar '19

This reverts commit 65a97e7fcf54feb7c4ebe1aee8a572830af4cf51. The 'eeprom' command has been converted to work with DM_I2C in a patch submitted around the same time as this commit: commit 0c07a9b4078d ("eeprom: Add device model based I2C support to eeprom command") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- cmd/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 4bcc5c4557..74c5a1a6ed 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -455,7 +455,6 @@ config CRC32_VERIFY config CMD_EEPROM bool "eeprom - EEPROM subsystem" - depends on !DM_I2C || DM_I2C_COMPAT help (deprecated, needs conversion to driver model) Provides commands to read and write EEPROM (Electrically Erasable -- 2.17.1

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[U-Boot] [PATCH] arm: zynq: Add an info message about post config
by Michal Simek 25 Mar '19

25 Mar '19

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Post configuration cant be run at u-boot as u-boot didn't has any info about the design.So,this patch adds an info message that post config was not run and needs to be run manually if needed. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/fpga/zynqpl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 683cf14b47e6..069c63ba4562 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -408,6 +408,8 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, if (bstype != BIT_PARTIAL) zynq_slcr_devcfg_enable(); + puts("INFO:post config was not run, please run manually if needed\n"); + return FPGA_SUCCESS; } -- 1.9.1

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[U-Boot] [PATCH] arm64: zynqmp: Add idcode for new RFSoC silicon ZU39DR
by Michal Simek 25 Mar '19

25 Mar '19

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> This patch adds "zu39dr" to the list of zynqmp devices The zu39DR is the new RFSoC silicon with id value of 0x66. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynqmp/zynqmp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index cfe772a9cf48..751c37dce2be 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -170,6 +170,10 @@ static const struct { .id = 0x62, .name = "29dr", }, + { + .id = 0x66, + .name = "39dr", + }, }; #endif -- 1.9.1

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[U-Boot] Adding F2FS support
by Juraj Vijtiuk 25 Mar '19

25 Mar '19

Hello, I've started to work on adding F2FS support to U-boot. After a quick search of the U-Boot mailing archives, I see that support for multiple file systems, like ZFS was already added by reusing existing GRUB code. F2FS was added to GRUB last year, in this commit: http://git.savannah.gnu.org/cgit/grub.git/commit/?id=71f9e4ac44142af52c3fc1… so I'd port that to U-Boot. F2FS has also been added to the Linux kernel in version 3.8 and is licensed under GNU GPLv2, so there shouldn't be any issues with that as far as I know. I plan to use the ZFS patch as a starting point, and reference other fs patches and recent ZFS updates when needed. Are there any potential issues or anything else I should know before I start working on the patch? Regards, Juraj Vijtiuk

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[U-Boot] [PATCH v2] driver: net: update copyright info
by Pankaj Bansal 25 Mar '19

25 Mar '19

Update copyright info for the issues reported after running check-legal test. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> --- Notes: V2: - Removed past tense from commit description and body drivers/net/fsl-mc/mc.c | 3 +-- drivers/net/ldpaa_eth/ldpaa_eth.c | 2 +- drivers/net/ldpaa_eth/ldpaa_eth.h | 2 +- drivers/net/ldpaa_eth/ldpaa_wriop.c | 1 + drivers/net/ldpaa_eth/lx2160a.c | 2 +- drivers/net/phy/phy.c | 2 ++ include/fsl-mc/ldpaa_wriop.h | 1 + include/phy.h | 2 ++ 8 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index cc59b21f9f..dc4dd4398a 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1,8 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP */ #include <common.h> #include <errno.h> diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 73b7ba29df..fc732c7be9 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017-2019 NXP */ #include <common.h> diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index 3f9154b5bb..dd559bb78d 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017-2019 NXP */ #ifndef __LDPAA_ETH_H diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c index 06a284ad68..a5a19c6b1a 100644 --- a/drivers/net/ldpaa_eth/ldpaa_wriop.c +++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Freescale Semiconductor + * Copyright 2018-2019 NXP */ #include <common.h> diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c index 1fbeb0d14b..8a71bf40a3 100644 --- a/drivers/net/ldpaa_eth/lx2160a.c +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #include <common.h> #include <phy.h> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 0c8b29dae4..7bf8e9ef05 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -3,6 +3,8 @@ * Generic PHY Management code * * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2018-2019 NXP + * * author Andy Fleming * * Based loosely off of Linux's PHY Lib diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h index b55c39cbb2..3f32c39ec9 100644 --- a/include/fsl-mc/ldpaa_wriop.h +++ b/include/fsl-mc/ldpaa_wriop.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015 Freescale Semiconductor + * Copyright 2018-2019 NXP */ #ifndef __LDPAA_WRIOP_H diff --git a/include/phy.h b/include/phy.h index f23ca63f3b..74d2e693eb 100644 --- a/include/phy.h +++ b/include/phy.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2018-2019 NXP + * * Andy Fleming <afleming(a)gmail.com> * * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h -- 2.17.1

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[U-Boot] [PATCH 1/2] ARM: socfpga: Pull PL310 clearing into common code
by Marek Vasut 25 Mar '19

25 Mar '19

Pull the PL310 clearing code into common code, so it can be reused by Arria10. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dalon Westergreen <dwesterg(a)gmail.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> --- arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 54 +++++++++++++++++++++++ arch/arm/mach-socfpga/spl_gen5.c | 54 ----------------------- 3 files changed, 55 insertions(+), 54 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 86d5d2b62b..876b850be2 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void); #endif void do_bridge_reset(int enable); +void socfpga_pl310_clear(void); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ec8339e045..14337ff2d9 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -46,6 +46,60 @@ int dram_init(void) return 0; } +void socfpga_pl310_clear(void) +{ + u32 mask = 0xff, ena = 0; + + icache_enable(); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x0, &pl310->pl310_tag_latency_ctrl); + writel(0x10, &pl310->pl310_data_latency_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + ena = readl(&pl310->pl310_ctrl); + ena |= L2X0_CTRL_EN; + + /* + * Invalidate the PL310 L2 cache. Keep the invalidation code + * entirely in L1 I-cache to avoid any bus traffic through + * the L2. + */ + asm volatile( + ".align 5 \n" + " b 3f \n" + "1: str %1, [%4] \n" + " dsb \n" + " isb \n" + " str %0, [%2] \n" + " dsb \n" + " isb \n" + "2: ldr %0, [%2] \n" + " cmp %0, #0 \n" + " bne 2b \n" + " str %0, [%3] \n" + " dsb \n" + " isb \n" + " b 4f \n" + "3: b 1b \n" + "4: nop \n" + : "+r"(mask), "+r"(ena) + : "r"(&pl310->pl310_inv_way), + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) + : "memory", "cc"); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + void enable_caches(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 142b60f887..3e2b9365ec 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -66,60 +66,6 @@ u32 spl_boot_mode(const u32 boot_device) } #endif -static void socfpga_pl310_clear(void) -{ - u32 mask = 0xff, ena = 0; - - icache_enable(); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x0, &pl310->pl310_tag_latency_ctrl); - writel(0x10, &pl310->pl310_data_latency_ctrl); - - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); - - /* Enable the L2 cache */ - ena = readl(&pl310->pl310_ctrl); - ena |= L2X0_CTRL_EN; - - /* - * Invalidate the PL310 L2 cache. Keep the invalidation code - * entirely in L1 I-cache to avoid any bus traffic through - * the L2. - */ - asm volatile( - ".align 5 \n" - " b 3f \n" - "1: str %1, [%4] \n" - " dsb \n" - " isb \n" - " str %0, [%2] \n" - " dsb \n" - " isb \n" - "2: ldr %0, [%2] \n" - " cmp %0, #0 \n" - " bne 2b \n" - " str %0, [%3] \n" - " dsb \n" - " isb \n" - " b 4f \n" - "3: b 1b \n" - "4: nop \n" - : "+r"(mask), "+r"(ena) - : "r"(&pl310->pl310_inv_way), - "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) - : "memory", "cc"); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); -- 2.20.1

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[U-Boot] [PATCH 0/5] Convert Pico i.MX7 to DM
by Joris Offouga 25 Mar '19

25 Mar '19

This series introduce DM Conversion for Pico i.MX7 Som and variant boards Joris Offouga (5): Arm: imx7d-pico: Import all Linux device tree for Pico i.MX7D SOM pico-imx7d: defconfig: Add DT file hooks pico-imx7d: defconfig Enable DM gpio pinctrl and pinctrl_imx7 pico-imx7d: Convert DM MMC pico-imx7d: Increase u-boot size for dfu request arch/arm/dts/imx7d-pico-hobbit.dts | 105 ++++ arch/arm/dts/imx7d-pico-pi.dts | 93 ++++ arch/arm/dts/imx7d-pico.dtsi | 590 +++++++++++++++++++++++ board/technexion/pico-imx7d/pico-imx7d.c | 42 +- board/technexion/pico-imx7d/spl.c | 38 ++ configs/pico-hobbit-imx7d_defconfig | 7 +- configs/pico-imx7d_defconfig | 7 +- configs/pico-pi-imx7d_defconfig | 7 +- include/configs/pico-imx7d.h | 2 +- 9 files changed, 848 insertions(+), 43 deletions(-) create mode 100644 arch/arm/dts/imx7d-pico-hobbit.dts create mode 100644 arch/arm/dts/imx7d-pico-pi.dts create mode 100644 arch/arm/dts/imx7d-pico.dtsi -- 2.17.1

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[U-Boot] [PATCH] mmc: correct the HS400 initialization process
by BOUGH CHEN 25 Mar '19

25 Mar '19

After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed() which indicates that the HS200/HS400 to HS downgrade is happening. During the HS400 initialization, first select to HS200, and config the related clock rate, then downgrade to HS mode. So here also need to config the downgrade value to be true, make sure in the function mmc_set_card_speed(), after switch to HS mode, first config the clock rate, then read the EXT_CSD. Otherwise read EXT_CSD in HS mode at wrong clock rate, e.g. 200MHz, may lead to uncertain result. Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer mode in this case, and USDHC will never get data transfer complete status, cause the uboot hang. Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/mmc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 1c1527cc74..55d3560b30 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1892,8 +1892,7 @@ static int mmc_select_hs400(struct mmc *mmc) } /* Set back to HS */ - mmc_set_card_speed(mmc, MMC_HS, false); - mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); + mmc_set_card_speed(mmc, MMC_HS, true); err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG); -- 2.17.1

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[U-Boot] [PATCH v1 00/26] colibri imx6 fixes, device tree enablement and driver model conversion
by Marcel Ziswiler 25 Mar '19

25 Mar '19

This series addresses some shortcomings, enables/introduces device tree support and converts all except video to using the driver model. This is fully tested both running our latest downstream BSP as well as the mainline Linux kernel. Bhuvanchandra DV (2): toradex: colibri_imx6: overwrite CMA memory set in device tree colibri_imx6: switch to zimage Gerard Salvatella (2): colibri_imx6: added nreset gpio on reboot board: colibri_imx6: check for and report ecc errors in fuses Marcel Ziswiler (12): colibri_imx6: get rid of obsolete nospl configurations colibri_imx6: use distro defaults colibri_imx6: move console in env from header file to defconfig colibri_imx6: enable fit image, gpt, imx thermal, efi loader support colibri_imx6: remove obsolete USB_GADGET_MASS_STORAGE configuration colibri_imx6: migrate to using device tree colibri_imx6: clean-up and migrate gpios to using driver model colibri_imx6: enable pin control driver colibri_imx6: migrate i2c to using driver model colibri_imx6: migrate pmic and regulator to using driver model colibri_imx6: migrate mmc to using driver model colibri_imx6: migrate usb to using driver model Max Krummenacher (7): colibri_imx6: drop CONFIG_OF_SYSTEM_SETUP colibri_imx6: print also 64-bit IT colibri_imx6: unify sd/mmc drive strenght with linux kernel settings colibri imx6: pf0100: reorder and cleanup message printing colibri imx6: disable ri and dcd irq in uarts colibri_imx6: change pmic fusing according to hw 1.1 requirements colibri_imx6: revert fuse value set in mfgr_fuse Sanchayan Maity (1): configs: colibri_imx6: Use ext4 file system by default Stefan Agner (2): colibri_imx6: add distroboot support colibri_imx6: use SDP if USB serial downloader has been used arch/arm/dts/imx6-colibri.dts | 411 ++++++++++++++++++ .../toradex/colibri_imx6/800mhz_2x64mx16.cfg | 58 --- .../toradex/colibri_imx6/800mhz_4x64mx16.cfg | 58 --- board/toradex/colibri_imx6/MAINTAINERS | 3 +- board/toradex/colibri_imx6/clocks.cfg | 41 -- board/toradex/colibri_imx6/colibri_imx6.c | 395 +++++++++-------- board/toradex/colibri_imx6/colibri_imx6.cfg | 37 -- board/toradex/colibri_imx6/ddr-setup.cfg | 97 ----- board/toradex/colibri_imx6/do_fuse.c | 2 +- board/toradex/colibri_imx6/pf0100.c | 177 +++++--- board/toradex/colibri_imx6/pf0100.h | 59 ++- board/toradex/colibri_imx6/pf0100_otp.inc | 16 +- configs/colibri_imx6_defconfig | 33 +- configs/colibri_imx6_nospl_defconfig | 63 --- include/configs/colibri_imx6.h | 66 +-- 15 files changed, 853 insertions(+), 663 deletions(-) create mode 100644 arch/arm/dts/imx6-colibri.dts delete mode 100644 board/toradex/colibri_imx6/800mhz_2x64mx16.cfg delete mode 100644 board/toradex/colibri_imx6/800mhz_4x64mx16.cfg delete mode 100644 board/toradex/colibri_imx6/clocks.cfg delete mode 100644 board/toradex/colibri_imx6/colibri_imx6.cfg delete mode 100644 board/toradex/colibri_imx6/ddr-setup.cfg delete mode 100644 configs/colibri_imx6_nospl_defconfig -- 2.20.1

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