February 2019 - U-Boot

[U-Boot] [PATCH v2] spl: implement CRC check on U-Boot uImage
by Simon Goldschmidt 10 Feb '19

10 Feb '19

SPL currently does not check uImage CRCs when loading U-Boot. This patch adds checking the uImage CRC when SPL loads U-Boot. It does this by reusing the existing config option SPL_CRC32_SUPPORT to allow leaving out the CRC check on boards where the additional code size or boot time is a problem (adding the CRC check currently adds ~1.4 kByte to flash). The SPL_CRC32_SUPPORT config option now gets enabled by default if SPL support for legacy images is enabled to check the CRC on all boards that don't actively take countermeasures. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- Changes in v2: - added Kconfig option SPL_LEGACY_IMAGE_CRC_CHECK to enable/disable checking CRC on legacy images common/spl/Kconfig | 21 +++++++++++++++------ common/spl/spl.c | 30 +++++++++++++++++++++++++++++- include/spl.h | 5 +++++ 3 files changed, 49 insertions(+), 7 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index d0564621d4..5c6c437ef0 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -80,6 +80,15 @@ config SPL_LEGACY_IMAGE_SUPPORT is y. If this is not set, SPL will move on to other available boot media to find a suitable image. +config SPL_LEGACY_IMAGE_CRC_CHECK + bool "Check CRC of Legacy images" + depends on SPL_LEGACY_IMAGE_SUPPORT + default y + select SPL_CRC32_SUPPORT + help + Enable this to check the CRC of Legacy images. While this increases + reliability, it affects both code size and boot duration. + config SPL_SYS_MALLOC_SIMPLE bool prompt "Only use malloc_simple functions in the SPL" @@ -207,13 +216,13 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE config SPL_CRC32_SUPPORT bool "Support CRC32" - depends on SPL_FIT + default y if SPL_LEGACY_IMAGE_SUPPORT help - Enable this to support CRC32 in FIT images within SPL. This is a - 32-bit checksum value that can be used to verify images. This is - the least secure type of checksum, suitable for detected - accidental image corruption. For secure applications you should - consider SHA1 or SHA256. + Enable this to support CRC32 in uImages or FIT images within SPL. + This is a 32-bit checksum value that can be used to verify images. + For FIT images, this is the least secure type of checksum, suitable + for detected accidental image corruption. For secure applications you + should consider SHA1 or SHA256. config SPL_MD5_SUPPORT bool "Support MD5" diff --git a/common/spl/spl.c b/common/spl/spl.c index 12f9359c0a..f2ea87a0ec 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -236,6 +236,14 @@ int spl_parse_image_header(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_LEGACY_IMAGE_SUPPORT u32 header_size = sizeof(struct image_header); + if (CONFIG_IS_ENABLED(LEGACY_IMAGE_CRC_CHECK)) { + /* check uImage header CRC */ + if (!image_check_hcrc(header)) { + puts("SPL: Image header CRC check failed!\n"); + return -EINVAL; + } + } + if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) { /* * On some system (e.g. powerpc), the load-address and @@ -253,6 +261,13 @@ int spl_parse_image_header(struct spl_image_info *spl_image, spl_image->size = image_get_data_size(header) + header_size; } +#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK + /* store uImage data length and CRC to check later */ + spl_image->dcrc_data = image_get_load(header); + spl_image->dcrc_length = image_get_data_size(header); + spl_image->dcrc = image_get_dcrc(header); +#endif + spl_image->os = image_get_os(header); spl_image->name = image_get_name(header); debug("spl: payload image: %32s load addr: 0x%lx size: %d\n", @@ -424,12 +439,25 @@ static struct spl_image_loader *spl_ll_find_loader(uint boot_device) static int spl_load_image(struct spl_image_info *spl_image, struct spl_image_loader *loader) { + int ret; struct spl_boot_device bootdev; bootdev.boot_device = loader->boot_device; bootdev.boot_device_name = NULL; - return loader->load_image(spl_image, &bootdev); + ret = loader->load_image(spl_image, &bootdev); +#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK + if (!ret && spl_image->dcrc_length) { + /* check data crc */ + ulong dcrc = crc32_wd(0, (unsigned char *)spl_image->dcrc_data, + spl_image->dcrc_length, CHUNKSZ_CRC32); + if (dcrc != spl_image->dcrc) { + puts("SPL: Image data CRC check failed!\n"); + ret = -EINVAL; + } + } +#endif + return ret; } /** diff --git a/include/spl.h b/include/spl.h index 9a439f468b..1b1d9ebbfb 100644 --- a/include/spl.h +++ b/include/spl.h @@ -33,6 +33,11 @@ struct spl_image_info { u32 size; u32 flags; void *arg; +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_CRC_CHECK) + ulong dcrc_data; + ulong dcrc_length; + ulong dcrc; +#endif }; /* -- 2.17.1

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[U-Boot] [PATCH] fdt: support booting with dtb in Android image
by Shawn Guo 10 Feb '19

10 Feb '19

Some platforms choose to store device tree blob in Android image second area. Let's try to look for dtb from there when booting an Android image, and use it for booting if found. Signed-off-by: Shawn Guo <shawn.guo(a)linaro.org> --- common/image-fdt.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/common/image-fdt.c b/common/image-fdt.c index 95748f0ae108..57f150311392 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -230,6 +230,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, ulong load, load_end; ulong image_start, image_data, image_end; #endif + ulong img_addr; ulong fdt_addr; char *fdt_blob = NULL; void *buf; @@ -245,6 +246,9 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, *of_flat_tree = NULL; *of_size = 0; + img_addr = simple_strtoul(argv[0], NULL, 16); + buf = map_sysmem(img_addr, 0); + if (argc > 2) select = argv[2]; if (select || genimg_has_config(images)) { @@ -415,6 +419,23 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, debug("## No Flattened Device Tree\n"); goto no_fdt; } +#ifdef CONFIG_ANDROID_BOOT_IMAGE + } else if (genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) { + struct andr_img_hdr *hdr = buf; + ulong fdt_data, fdt_len; + + if (android_image_get_second(hdr, &fdt_data, &fdt_len) != 0) + goto no_fdt; + + fdt_blob = (char *)fdt_data; + if (fdt_check_header(fdt_blob) != 0) + goto no_fdt; + + if (fdt_totalsize(fdt_blob) != fdt_len) + goto error; + + debug("## Using FDT found in Android image second area\n"); +#endif } else { debug("## No Flattened Device Tree\n"); goto no_fdt; -- 2.18.0

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[U-Boot] [PATCH] arm: mach-k3: common: Clean up ATF image startup function
by Andreas Dannenberg 10 Feb '19

10 Feb '19

Perform some cosmetic cleanup of the ATF image startup function, namely fixing a spelling mistake, capitalization of a few words, spacing, as well aligning how errors are printed and as using panic() for cases that were using a combination of printf() + hang(). Signed-off-by: Andreas Dannenberg <dannenberg(a)ti.com> --- arch/arm/mach-k3/common.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index e225458baf..79d4ffe988 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -45,33 +45,25 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) /* * It is assumed that remoteproc device 1 is the corresponding - * cortex A core which runs ATF. Make sure DT reflects the same. + * Cortex-A core which runs ATF. Make sure DT reflects the same. */ ret = rproc_dev_init(1); - if (ret) { - printf("%s: ATF failed to Initialize on rproc: ret= %d\n", - __func__, ret); - hang(); - } + if (ret) + panic("%s: ATF failed to initialize on rproc (%d)\n", __func__, + ret); ret = rproc_load(1, spl_image->entry_point, 0x200); - if (ret) { - printf("%s: ATF failed to load on rproc: ret= %d\n", - __func__, ret); - hang(); - } + if (ret) + panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret); - /* Add an extra newline to differentiate the ATF logs from SPL*/ + /* Add an extra newline to differentiate the ATF logs from SPL */ printf("Starting ATF on ARM64 core...\n\n"); ret = rproc_start(1); - if (ret) { - printf("%s: ATF failed to start on rproc: ret= %d\n", - __func__, ret); - hang(); - } + if (ret) + panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret); - debug("ATF started. Wait indefiniely\n"); + debug("ATF started. Waiting indefinitely...\n"); while (1) asm volatile("wfe"); } -- 2.17.1

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[U-Boot] [PATCH V2 1/2] bcm968580: rename to bcm968580xref
by Philippe Reynes 10 Feb '19

10 Feb '19

The name of the board is bcm968580xref, so rename the config to bcm968580xref too. Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- board/broadcom/bcm968580xref/MAINTAINERS | 4 ++-- configs/bcm968580_ram_defconfig | 35 -------------------------------- configs/bcm968580xref_ram_defconfig | 35 ++++++++++++++++++++++++++++++++ 3 files changed, 37 insertions(+), 37 deletions(-) delete mode 100644 configs/bcm968580_ram_defconfig create mode 100644 configs/bcm968580xref_ram_defconfig Changelog: v2: - update the config name in the MAINTAINERS file diff --git a/board/broadcom/bcm968580xref/MAINTAINERS b/board/broadcom/bcm968580xref/MAINTAINERS index 1ecdfbc..5ee0c4d 100644 --- a/board/broadcom/bcm968580xref/MAINTAINERS +++ b/board/broadcom/bcm968580xref/MAINTAINERS @@ -1,6 +1,6 @@ -BROADCOM BCM968580XREF +BCM968580XREF BOARD M: Philippe Reynes <philippe.reynes(a)softathome.com> S: Maintained F: board/broadcom/bcm968580xref/ F: include/configs/broadcom_bcm968580xref.h -F: configs/bcm968580_ram_defconfig +F: configs/bcm968580xref_ram_defconfig diff --git a/configs/bcm968580_ram_defconfig b/configs/bcm968580_ram_defconfig deleted file mode 100644 index 56e0a56..0000000 --- a/configs/bcm968580_ram_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_BCM6858=y -CONFIG_SYS_TEXT_BASE=0x10000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_BCM968580XREF=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTEFI_SELFTEST=y -CONFIG_DOS_PARTITION=y -CONFIG_ISO_PARTITION=y -CONFIG_EFI_PARTITION=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref" -# CONFIG_NET is not set -CONFIG_BLK=y -CONFIG_CLK=y -# CONFIG_MMC is not set -CONFIG_SPECIFY_CONSOLE_INDEX=y -# CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_CONS_INDEX=0 -CONFIG_DM_SERIAL=y -CONFIG_SERIAL_SEARCH_ALL=y -CONFIG_BCM6345_SERIAL=y -CONFIG_SYSRESET=y -CONFIG_REGEX=y -# CONFIG_GENERATE_SMBIOS_TABLE is not set diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig new file mode 100644 index 0000000..56e0a56 --- /dev/null +++ b/configs/bcm968580xref_ram_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_BCM6858=y +CONFIG_SYS_TEXT_BASE=0x10000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_TARGET_BCM968580XREF=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTEFI_SELFTEST=y +CONFIG_DOS_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref" +# CONFIG_NET is not set +CONFIG_BLK=y +CONFIG_CLK=y +# CONFIG_MMC is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y +CONFIG_SERIAL_SEARCH_ALL=y +CONFIG_BCM6345_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_REGEX=y +# CONFIG_GENERATE_SMBIOS_TABLE is not set -- 2.7.4

2 3

[U-Boot] [PATCH 1/3] configs: am65x_evm_r5: Enable GPT support
by Andrew F. Davis 10 Feb '19

10 Feb '19

The second loader stages may be stored on GPT partitions, enable support for this here. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- configs/am65x_evm_r5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 237b9e8229..51406548d4 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set -- 2.19.1

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[U-Boot] [PATCH v3 0/2] While converting SATA on Apalis iMX6 to use driver model I noticed it
by Marcel Ziswiler 10 Feb '19

10 Feb '19

crashing in case no SATA driver is actually there: Apalis iMX6 # sata init data abort pc : [<8ff78e1a>] lr : [<8ff78e1b>] reloc pc : [<1781be1a>] lr : [<1781be1b>] sp : 8df53068 ip : 00000001 fp : 00000002 r10: 8df612e8 r9 : 8df5ceb0 r8 : 8ffc2b28 r7 : 8ff746ed r6 : 00000000 r5 : 68abf82a r4 : 00000000 r3 : 8ff73d39 r2 : c0000000 r1 : 00000000 r0 : 0000000c Flags: nzcv IRQs off FIQs off Mode SVC_32 Code: 47700025 6803b570 6bdd4604 f0254805 (68abf82a) Resetting CPU ... resetting ... Investigating this I identified 3 places where no proper checking is done. This patch set adds such checks leading to a graceful error instead: Apalis iMX6 # sata init Cannot probe SATA device 0 (err=-19) Changes in v3: - Added Simon's reviewed-by. Changes in v2: - Update dm_test_uclass_devices_find() to test this behaviour as suggested by Simon. - Dropped "[PATCH 2/3] dm: sata: add null pointer check for dev" as suggested by Simon. - Added Simon's reviewed-by. Marcel Ziswiler (2): dm: device: fail uclass_find_first_device() if list_empty cmd: sata: add null pointer check for dev cmd/sata.c | 4 ++++ drivers/core/uclass.c | 2 +- test/dm/core.c | 4 ++++ 3 files changed, 9 insertions(+), 1 deletion(-) -- 2.20.1

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[U-Boot] [PATCH 1/5] bcm63158: add initial support
by Philippe Reynes 10 Feb '19

10 Feb '19

This add the initial support of the broadcom bcm63158 SoC family, only the cpu, dram and uart are supported. Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- arch/arm/Kconfig | 6 ++++ arch/arm/dts/bcm63158.dtsi | 85 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 arch/arm/dts/bcm63158.dtsi diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0edb10..4316de0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -528,6 +528,12 @@ config ARCH_BCM283X imply CMD_DM imply FAT_WRITE +config ARCH_BCM63158 + bool "Broadcom BCM63158 family" + select DM + select OF_CONTROL + imply CMD_DM + config ARCH_BCM6858 bool "Broadcom BCM6858 family" select DM diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi new file mode 100644 index 0000000..be68205 --- /dev/null +++ b/arch/arm/dts/bcm63158.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Philippe Reynes <philippe.reynes(a)softathome.com> + */ + +#include "skeleton64.dtsi" + +/ { + compatible = "brcm,bcm63158"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + l2: l2-cache0 { + compatible = "cache"; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0xbebc200>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + + uart0: serial@ff812000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xff812000 0x0 0x1000>; + clock = <50000000>; + + status = "disabled"; + }; + }; +}; -- 2.7.4

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[U-Boot] [PATCH] board/BuR/brppt1: drop DM_I2C_COMPAT
by Hannes Schmelzer 10 Feb '19

10 Feb '19

The TPS62517 PMIC driver has been partially converted to DM, so the legacy I2C access layer isn't needed anymore. Signed-off-by: Hannes Schmelzer <hannes.schmelzer(a)br-automation.com> --- board/BuR/brppt1/board.c | 5 ++--- board/BuR/brxre1/board.c | 2 +- board/BuR/common/bur_common.h | 2 +- board/BuR/common/common.c | 7 ++++--- configs/brppt1_mmc_defconfig | 1 - configs/brppt1_nand_defconfig | 1 - configs/brppt1_spi_defconfig | 1 - 7 files changed, 8 insertions(+), 11 deletions(-) diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index d2e7c72..b8ab19c 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -106,9 +106,8 @@ void am33xx_spl_board_init(void) /* setup I2C */ enable_i2c_pin_mux(); - i2c_set_bus_num(0); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - pmicsetup(0); + + pmicsetup(0, 0); /* peripheral reset */ rc = gpio_request(64 + 29, "GPMC_WAIT1"); diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c index 41ed28b..82c53d5 100644 --- a/board/BuR/brxre1/board.c +++ b/board/BuR/brxre1/board.c @@ -132,7 +132,7 @@ void am33xx_spl_board_init(void) puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); } - pmicsetup(0); + pmicsetup(0, 0); } const struct dpll_params *get_dpll_ddr_params(void) diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index 5f2d0d0..f743194 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -15,7 +15,7 @@ int load_lcdtiming(struct am335x_lcdpanel *panel); void br_summaryscreen(void); -void pmicsetup(u32 mpupll); +void pmicsetup(u32 mpupll, unsigned int bus); void enable_uart0_pin_mux(void); void enable_i2c_pin_mux(void); void enable_board_pin_mux(void); diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index f3eae5c..a1f7c44 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -269,13 +269,14 @@ int ft_board_setup(void *blob, bd_t *bd) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -void pmicsetup(u32 mpupll) +void pmicsetup(u32 mpupll, unsigned int bus) { int mpu_vdd; int usb_cur_lim; - if (i2c_probe(TPS65217_CHIP_PM)) { - puts("PMIC (0x24) not found! skip further initalization.\n"); + if (power_tps65217_init(bus)) { + printf("WARN: cannot setup PMIC 0x24 @ bus #%d, not found!.\n", + bus); return; } diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 083b5f7..f2d8220 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -71,7 +71,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y CONFIG_DM_MMC=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 1cfd5fc..275727d 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -73,7 +73,6 @@ CONFIG_BLK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y # CONFIG_MMC is not set diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 3737396..668c4c2 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -76,7 +76,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y CONFIG_DM_MMC=y -- 2.7.4

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[U-Boot] [PATCH] mmc: omap_hsmmc: Workaround errata regarding SDR104/HS200 tuning failures (i929)
by Faiz Abbas 10 Feb '19

10 Feb '19

Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions (SPRZ426D - November 2014 - Revised February 2018 [1]) mentions unexpected tuning pattern errors. A small failure band may be present in the tuning range which may be missed by the current algorithm. Furthermore, the failure bands vary with temperature leading to different optimum tuning values for different temperatures. As suggested in the related Application Report (SPRACA9B - October 2017 - Revised July 2018 [2]), tuning should be done in two stages. In stage 1, assign the optimum ratio in the maximum pass window for the current temperature. In stage 2, if the chosen value is close to the small failure band, move away from it in the appropriate direction. References: [1] http://www.ti.com/lit/pdf/sprz426 [2] http://www.ti.com/lit/pdf/SPRACA9 Signed-off-by: Faiz Abbas <faiz_abbas(a)ti.com> --- drivers/mmc/omap_hsmmc.c | 92 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 5cb97eb02a..b11c71cae7 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -47,6 +47,7 @@ #endif #include <dm.h> #include <power/regulator.h> +#include <thermal.h> DECLARE_GLOBAL_DATA_PTR; @@ -622,6 +623,10 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) u32 phase_delay = 0; u32 start_window = 0, max_window = 0; u32 length = 0, max_len = 0; + bool single_point_failure = false; + struct udevice *thermal_dev; + int temperature; + int i; mmc_base = priv->base_addr; val = readl(&mmc_base->capa2); @@ -632,9 +637,25 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50)))) return 0; + ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev); + if (ret) { + printf("Couldn't get thermal device for tuning\n"); + return ret; + } + ret = thermal_get_temp(thermal_dev, &temperature); + if (ret) { + printf("Couldn't get temperature for tuning\n"); + return ret; + } val = readl(&mmc_base->dll); val |= DLL_SWT; writel(val, &mmc_base->dll); + + /* + * Stage 1: Search for a maximum pass window ignoring any + * any single point failures. If the tuning value ends up + * near it, move away from it in stage 2 below + */ while (phase_delay <= MAX_PHASE_DELAY) { omap_hsmmc_set_dll(mmc, phase_delay); @@ -643,10 +664,16 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) if (cur_match) { if (prev_match) { length++; + } else if (single_point_failure) { + /* ignore single point failure */ + length++; + single_point_failure = false; } else { start_window = phase_delay; length = 1; } + } else { + single_point_failure = prev_match; } if (length > max_len) { @@ -668,8 +695,71 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) ret = -EIO; goto tuning_error; } + /* + * Assign tuning value as a ratio of maximum pass window based + * on temperature + */ + if (temperature < -20000) + phase_delay = min(max_window + 4 * max_len - 24, + max_window + + DIV_ROUND_UP(13 * max_len, 16) * 4); + else if (temperature < 20000) + phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4; + else if (temperature < 40000) + phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4; + else if (temperature < 70000) + phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4; + else if (temperature < 90000) + phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4; + else if (temperature < 120000) + phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4; + else + phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4; + + /* + * Stage 2: Search for a single point failure near the chosen tuning + * value in two steps. First in the +3 to +10 range and then in the + * +2 to -10 range. If found, move away from it in the appropriate + * direction by the appropriate amount depending on the temperature. + */ + for (i = 3; i <= 10; i++) { + omap_hsmmc_set_dll(mmc, phase_delay + i); + if (mmc_send_tuning(mmc, opcode, NULL)) { + if (temperature < 10000) + phase_delay += i + 6; + else if (temperature < 20000) + phase_delay += i - 12; + else if (temperature < 70000) + phase_delay += i - 8; + else if (temperature < 90000) + phase_delay += i - 6; + else + phase_delay += i - 6; + + goto single_failure_found; + } + } + + for (i = 2; i >= -10; i--) { + omap_hsmmc_set_dll(mmc, phase_delay + i); + if (mmc_send_tuning(mmc, opcode, NULL)) { + if (temperature < 10000) + phase_delay += i + 12; + else if (temperature < 20000) + phase_delay += i + 8; + else if (temperature < 70000) + phase_delay += i + 8; + else if (temperature < 90000) + phase_delay += i + 10; + else + phase_delay += i + 12; + + goto single_failure_found; + } + } + +single_failure_found: - phase_delay = max_window + 4 * ((3 * max_len) >> 2); omap_hsmmc_set_dll(mmc, phase_delay); mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); -- 2.19.2

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[U-Boot] [PATCH 0/7] stm32mp1: update clock driver
by Patrick Delaunay 10 Feb '19

10 Feb '19

This serie udpates the stm32mp1 clock driver with the latest patches and prepare alignment with latest kernel device tree. This patch is applicable on the top of the serie "stm32mp1: add trusted boot with TF-A" http://patchwork.ozlabs.org/project/uboot/list/?series=88521 Patrick Delaunay (7): clk: stm32mp1: no more get ck_usbo_48m in device tree clk: stm32mp1: add IPCC clock clk: stm32mp1: correct access to RCC_OCENSETR/RCC_OCENCLRR clk: stm32mp1: recalculate counter when switching freq clk: stm32mp1: add debug information dts: stm32mp1: clock tree update clk: stm32mp1: correctly handle Clock Spreading Generator arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 27 +++--- configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + doc/device-tree-bindings/clock/st,stm32mp1.txt | 10 +-- drivers/clk/clk_stm32mp1.c | 120 +++++++++++++++++++++---- include/dt-bindings/clock/stm32mp1-clks.h | 3 - 6 files changed, 124 insertions(+), 38 deletions(-) -- 2.7.4

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