February 2019 - U-Boot

Re: [U-Boot] [REGRESSION] tegra124: nyan-big: LPAE not working
by Thierry Reding 04 Mar '19

04 Mar '19

On Mon, Feb 11, 2019 at 10:04:37AM +0000, Tristan Bastian wrote: > > > > Thierry Reding – Mon, 11. February 2019 10:38 > > On Mon, Feb 11, 2019 at 09:20:33AM +0000, Tristan Bastian wrote: > > > > > > Thierry Reding – Mon, 11. February 2019 9:52 > > > > On Sun, Feb 10, 2019 at 08:53:11PM +0100, Tristan Bastian wrote: > > > > > Thierry, do you have any news on this? > > > > > > > > > > I don't think, that google is going to push an updated version of > > coreboot > > > > > to each nyan-big device.. > > > > > So reverting this patch at least for the nyan devices would be the best > > I > > > > > think.. > > > > > > > > Yes, I agree. I had a brief chat with Rob Herring about this and he too > > > > agrees that we should revert it for now. I'll make it a manual revert > > > > and add a comment to the device tree node that will hopefully avoid any > > > > future janitorial "cleanups" of this sort. > > > > > > great news! :) > > > > > > > > BTW: I'm now running u-boot natively and it seems like u-boot always has > > a > > > > > problem with the memory.. > > > > > If u-boot is used chainloaded to coreboot it is only getting 2GB of > > memory > > > > > and running u-boot natively also just gives me 2GB.. > > > > > I've tested that with a kernel with "ARM: tegra: Fix unit_address_vs_reg > > DTC > > > > > warnings for /memory" reverted and also on a kernel, before this patch > > was > > > > > applied.. > > > > > > > > It's possible that U-Boot doesn't support LPAE and therefore may not be > > > > able to use more than the 2 GiB of memory. > > > > > > So I at least enabled LPAE in u-boot with "CONFIG_ARMV7_LPAE=y" and > > > this was for some reason also needed to get some output on the > > > display.. > > > I'm not sure why LPAE needs to activated in u-boot for display output > > > on the nyan-big.. > > > Without LPAE enabled u-boot was still working, and booted linux, but > > > u-boot didn't display anything on screen, linux then did.. > > > > Yeah, that's surprising. Perhaps without LPAE U-Boot thinks there's not > > enough memory for the framebuffer? There should be plenty, so maybe > > there is something else going on here. > > > > > > However, U-Boot should be > > > > able to tell the kernel exactly how much memory the system has and pass > > > > that on via device tree. That still does work, right? > > > > > > It seems like this is not working.. > > > And this seems to be the case with both, u-boot chainloaded and > > > running u-boot natively.. > > > > > > I've used these scripts for flashing: > > > github.com/NVIDIA/tegra-uboot-flasher-scripts > > > And used the norrin device since it seems like it is the nyan-big dev > > > board? > > > But going with the norrin device config should not be the issue here > > > since the problem also exists when chainloading u-boot, right? > > > > It could be a problem. The memory bank configuration is stored in what's > > called a BCT along with a bunch of other parameters that define what the > > memory controller needs to access the given memory chips. So if you've > > flashed a BCT that's for a board with only 2 GiB of memory you would end > > up with a system that can't address any more than that. It's somewhat > > surprising that memory accesses work at all with a BCT that's for > > different memory chips, but sometimes you can get lucky. > > > > You may want to try reflashing with the right BCT. The simplest would > > probably be to duplicate the cbootimage configuration for Norrin and > > substitute the relevant bits by what you have from the Chromebook flash > > utilities. Looks like the BCT in really the only thing you can replace > > there. Make sure to replace it with the one that matches your Chromebook > > and it should give you the right memory bank configuration. > > Is there a way to check if the correct bct for my 4GB model was used? > What I tried was to edit the existing bct config file of norrin from here: > https://github.com/NVIDIA/cbootimage-configs/blob/master/tegra124/nvidia/no… > by replacing all entries for each memory bank with the entries from here: > https://github.com/coreboot/coreboot/blob/master/src/mainboard/google/nyan_… > > I also added the SDRAM[0], SDRAM[1], SDRAM[2], SDRAM[3] each time in front of each line.. > This also booted for me, but also just leaves me with only 2Gb of my 4GB.. > > And since this problem also occurs, when chainloading u-boot, this must be a problem with u-boot, I think.. Not necessarily. U-Boot reads the memory size from EMC registers and those EMC registers are programmed based on the contents of the BCT. So if the BCT is wrong, then it's going to be wrong irrespective of what bootloader you use. That said, I does indeed look as if U-Boot only supports 2 GiB of memory on 32-bit Tegra. arch/arm/mach-tegra/board.c contains the relevant code. If you look at dram_init() it uses query_sdram_size() to get the size of RAM. That will allow to convey up to 4 GiB of RAM, but then the code in board2.c (see dram_init_banksize()) only uses a single bank on 32-bit Tegra (CONFIG_PHYS_64BIT is only set for 64-bit Tegra). According to the comments for dram_init_bank_size() we can't store the second bank because the .start field is 32 bits wide and therefore can't store the 0x100000000 start address for the bank. It sounds to me like ARMV7_LPAE should perhaps select PHYS_64BIT to make sure all the appropriate variables can store addresses beyond the 32-bit boundary. It's one thing to not support > 2 GiB of memory in U-Boot, but it's an entirely different story if we can't even pass > GiB of memory to the kernel if they exist. Stephen, do you remember if there was anything preventing us from going 64-bit for phys_addr_t and phys_size_t on LPAE enabled systems? Cc Tom for visibility and U-Boot since this is a U-Boot bug. Thierry > Tristan > > > > Simon Glass used his servo board to enter the tegrarcm mode: > > > patchwork.ozlabs.org/patch/1019003/ > > > > > > I had to erase the internal SPI flash in order to boot into the > > > tegrarcm mode.. > > > Do you have some instructions or internal documentation to tell me, if > > > some of the unpopulated buttons on the nyan-big mainboard can be used > > > to enter the tegrarcm state? > > > > You should be able to boot into recovery mode with the "enterrcm" > > command in U-Boot. I'm not aware of any buttons on the mainboard that > > can be used for this, unfortunately. > > > > Thierry

5 4

[U-Boot] Marvell DDR training custom ODT configuration
by Baruch Siach 03 Mar '19

03 Mar '19

Hi Chris, Currently the value of g_odt_config is hard coded in Marvell SoC platform headers. Some SolidRun A388 SOMs need a custom value. These SOMs use both DDR chip-selects, but ODT0 alone is connected to both chips. For that to work we need to set g_odt_config to 0x30000, that is, ODT0 is configured for both CS0 and CS1. How can we do that in a clean way so as to not interfere too much with your periodic code syncs from Marvell's DDR training source tree? Thanks, baruch -- http://baruch.siach.name/blog/ ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch(a)tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

2 3

[U-Boot] [v2] powerpc: t104xrdb: Add support of MTA9ADF1G72AZ DDR
by Peng Ma 03 Mar '19

03 Mar '19

T1040RDB has been upgraded to support new DDR ie. MTA9ADF1G72AZ-3G2, 8GB. So adding support of new DDR part by updating board_specific_parameters udimm0. Signed-off-by: Peng Ma <peng.ma(a)nxp.com> --- change for V2: - update comments and subject board/freescale/t104xrdb/ddr.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index 319fc59..f9d667f 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -29,6 +29,7 @@ static const struct board_specific_parameters udimm0[] = { */ #ifdef CONFIG_SYS_FSL_DDR4 {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a}, + {1, 1600, 4, 8, 5, 0x0607080B, 0x0C0C0D09}, #elif defined(CONFIG_SYS_FSL_DDR3) {2, 833, 4, 8, 6, 0x06060607, 0x08080807}, {2, 833, 0, 8, 6, 0x06060607, 0x08080807}, -- 1.7.1

2 1

[U-Boot] [PATCH 1/1] efi_loader: HII protocols: fix new_package_list()
by Heinrich Schuchardt 02 Mar '19

02 Mar '19

In new_package_list() we call new_packagelist() to create a new package list. Next we try to add the packages which fails for form packages. Due to this error we call free_packagelist(). Now in free_packagelist() list_del() is called for an uninitialized field hii->link. This leads to changing random memory addresses. To solve the problem move the initialization of hii->link to new_packagelist(). Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- @Takahiro: Please, review the patch. --- lib/efi_loader/efi_hii.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c index d63d2d84184..0ed4b196333 100644 --- a/lib/efi_loader/efi_hii.c +++ b/lib/efi_loader/efi_hii.c @@ -343,6 +343,7 @@ static struct efi_hii_packagelist *new_packagelist(void) struct efi_hii_packagelist *hii; hii = malloc(sizeof(*hii)); + list_add_tail(&hii->link, &efi_package_lists); hii->max_string_id = 0; INIT_LIST_HEAD(&hii->string_tables); INIT_LIST_HEAD(&hii->guid_list); @@ -465,7 +466,6 @@ new_package_list(const struct efi_hii_database_protocol *this, } hii->driver_handle = driver_handle; - list_add_tail(&hii->link, &efi_package_lists); *handle = hii; return EFI_EXIT(EFI_SUCCESS); -- 2.20.1

4 4

[U-Boot] [PATCH 1/1] efi_loader: error handling for `efidebug boot add`
by Heinrich Schuchardt 02 Mar '19

02 Mar '19

In `efidebug boot add iPXE scsi 0:1 snp-arm64.efi --foo` a parameter is missing. Hence the command should not silently return as if everything were ok but should display the usage info. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/efidebug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/efidebug.c b/cmd/efidebug.c index 5072a7b39bc..db96682c5a4 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -491,7 +491,7 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag, id = (int)simple_strtoul(argv[1], &endp, 16); if (*endp != '\0' || id > 0xffff) - return CMD_RET_FAILURE; + return CMD_RET_USAGE; sprintf(var_name, "Boot%04X", id); p = var_name16; -- 2.20.1

2 1

[U-Boot] db-88f6820-amc doesn't boot on latest u-boot/master
by Chris Packham 02 Mar '19

02 Mar '19

Hi All, I was just testing out the db-88f6820-amc on u-boot#master and found that the SPL can't fetch then next stage from SPI. U-Boot SPL 2019.04-rc2-00139-g91c56ed98da7 (Mar 01 2019 - 10:26:26 +1300) High speed PHY - Version: 2.0 Detected Device ID 6820 board SerDes lanes topology details: | Lane # | Speed | Type | -------------------------------- | 0 | 5 | PCIe0 | | 4 | 0 | SGMII1 | | 5 | 0 | SGMII2 | -------------------------------- PCIe, Idx 0: detected no link High speed PHY - Ended Successfully mv_ddr: mv_ddr-armada-18.09.2 DDR3 Training Sequence - Switching XBAR Window to FastPath Window mv_ddr: completed successfully Trying to boot from SPI SPI probe failed. SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### I haven't had time to bisect this yet but I wondered if this was related to the recent spi changes (this board uses SPI1 so maybe that's the corner case). I may also potentially be fixed by the SPI Kconfig series that is floating around on the list.

2 6

[U-Boot] [PATCH] am335x-fb: don't override lcd_get_size()
by David Rivshin 01 Mar '19

01 Mar '19

From: David Rivshin <DRivshin(a)allworx.com> am335x-fb overrides the default lcd_get_size() to add an extra 32 bytes compared to the normal calculation. While the gd->fb_base is an extra 32 bytes larger than the logical framebuffer size, the first 32 bytes is always skipped. Adding that extra 32 bytes in lcd_get_size() can cause check_cache_range() (called from lcd_sync(), via flush_dcache_range()) to output a warning because the end address is not cacheline aligned, even if the start and real framebuffer size are. When removing that "+ 0x20" the am335x-fb lcd_get_size() is identical to the default one, so just delete it altogether. Signed-off-by: David Rivshin <drivshin(a)allworx.com> --- drivers/video/am335x-fb.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index 51c1af587f..3a510cf91c 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -103,12 +103,6 @@ static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE; DECLARE_GLOBAL_DATA_PTR; -int lcd_get_size(int *line_length) -{ - *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; - return *line_length * panel_info.vl_row + 0x20; -} - int am335xfb_init(struct am335x_lcdpanel *panel) { u32 raster_ctrl = 0; base-commit: d3689267f92c5956e09cc7d1baa4700141662bff -- 2.20.1

2 2

[U-Boot] [PATCH 0/3] arm: socfpga: clean up socfpga_common.h
by Simon Goldschmidt 01 Mar '19

01 Mar '19

This series cleans up the include/configs/socfpga_common.h file a bit. It removes some defines that are used nowhere and cleans up some leftovers after various subsystems have been converted to use DM. Simon Goldschmidt (3): arm: socfpga: move legacy i2c defines to vining arm: socfpga: clean up socfpga_common.h arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ include/configs/socfpga_common.h | 41 --------------------------- include/configs/socfpga_vining_fpga.h | 24 ++++++++++++++++ 2 files changed, 24 insertions(+), 41 deletions(-) -- 2.17.1

3 20

[U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies
by Marek Vasut 01 Mar '19

01 Mar '19

Configure the PL310 tag and data latency registers, which slightly improves performance and aligns the behavior with Linux. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dalon Westergreen <dwesterg(a)gmail.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> --- arch/arm/mach-socfpga/misc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 78fbe28724..1ea4e32c11 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -62,6 +62,9 @@ void v7_outer_cache_enable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + writel(0x111, &pl310->pl310_tag_latency_ctrl); + writel(0x121, &pl310->pl310_data_latency_ctrl); + /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | -- 2.19.2

3 7

[U-Boot] iMX8QXP MEK: no ethernet
by Andrejs Cainikovs 01 Mar '19

01 Mar '19

Hi, I cant get ethernet to work on iMX8QXP MEK board with latest sources (tried v2019.01 as well). Is this a bug or work in progress? --- U-Boot SPL 2019.04-rc2-00134-g783e66816d (Feb 28 2019 - 13:15:40 +0100) Normal Boot Trying to boot from MMC2_2 U-Boot 2019.04-rc2-00134-g783e66816d (Feb 28 2019 - 13:15:40 +0100) CPU: NXP i.MX8QXP RevB A35 at 147228 MHz Model: Freescale i.MX8QXP MEK Board: iMX8QXP MEK Build: SCFW 3301c1a9 Boot: SD1 DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: eth-1: ethernet@5b040000 Hit any key to stop autoboot: 0 => dhcp No ethernet found. --- Best regards, Andrejs Cainikovs.

3 9