December 2019 - U-Boot

[PATCH 1/4] rockchip: fit_spl_optee: get text and optee base from build
by Kever Yang 05 Dec '19

05 Dec '19

Instead of hardcode the base address, we can get them from the build output, eg. get the SYS_TEXT_BASE from .config and get optee base from DRAM_BASE. We can use this script for SoCs with DRAM base not from 0x60000000(rk3229 and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/mach-rockchip/fit_spl_optee.sh | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/fit_spl_optee.sh b/arch/arm/mach-rockchip/fit_spl_optee.sh index 89ef04312c..4118472d9f 100755 --- a/arch/arm/mach-rockchip/fit_spl_optee.sh +++ b/arch/arm/mach-rockchip/fit_spl_optee.sh @@ -17,6 +17,12 @@ if [ ! -f $TEE ]; then fi dtname=$1 +text_base=`sed -n "/SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" .config \ + |tr -d '\r'` +dram_base=`sed -n "/SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" \ + include/autoconf.mk|tr -d '\r'` +tee_base=`echo "obase=16;$(($dram_base+0x8400000))"|bc` +tee_base='0x'$tee_base cat << __HEADER_EOF /* @@ -39,7 +45,7 @@ cat << __HEADER_EOF os = "U-Boot"; arch = "arm"; compression = "none"; - load = <0x61000000>; + load = <$text_base>; }; optee { description = "OP-TEE"; @@ -48,8 +54,8 @@ cat << __HEADER_EOF arch = "arm"; os = "tee"; compression = "none"; - load = <0x68400000>; - entry = <0x68400000>; + load = <$tee_base>; + entry = <$tee_base>; }; fdt { description = "$(basename $dtname .dtb)"; -- 2.17.1

1 3

[U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode
by Xiaowei Bao 05 Dec '19

05 Dec '19

From: Xiaowei Bao <xiaowei.bao(a)nxp.com> Signed-off-by: hongbo.wang <hongbo.wang(a)nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian(a)nxp.com> Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- v2: - Add the NXP copyright and make the function readability. drivers/pci/pcie_layerscape.c | 117 +++++++++++++++++++++++++++-------------- drivers/pci/pcie_layerscape.h | 19 +++++-- 2 files changed, 91 insertions(+), 45 deletions(-) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index db1375a..8f5ebda 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver */ @@ -105,13 +105,14 @@ static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type, } /* Use bar match mode and MEM type as default */ -static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, - int bar, u64 phys) +static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int idx, + int bar, u64 phys) { dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT); dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET); dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET); - dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); + dbi_writel(pcie, PCIE_ATU_TYPE_MEM | PCIE_CTRL1_FUNC_NUM(pf), + PCIE_ATU_CR1); dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2); } @@ -341,50 +342,61 @@ static void ls_pcie_setup_ctrl(struct ls_pcie *pcie) ls_pcie_disable_bars(pcie); } -static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie) +static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie, u32 pf) { - u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE; + pci_size_t atu_size = CONFIG_SYS_PCI_MEMORY_SIZE; + u64 phys = 0; + phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_2M; + + phys = ALIGN(phys, PCIE_BAR0_SIZE); /* ATU 0 : INBOUND : map BAR0 */ - ls_pcie_atu_inbound_set(pcie, 0, 0, phys); + ls_pcie_atu_inbound_set(pcie, pf, 0 + pf * BAR_NUM, 0, phys); /* ATU 1 : INBOUND : map BAR1 */ - phys += PCIE_BAR1_SIZE; - ls_pcie_atu_inbound_set(pcie, 1, 1, phys); + phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE); + ls_pcie_atu_inbound_set(pcie, pf, 1 + pf * BAR_NUM, 1, phys); /* ATU 2 : INBOUND : map BAR2 */ - phys += PCIE_BAR2_SIZE; - ls_pcie_atu_inbound_set(pcie, 2, 2, phys); - /* ATU 3 : INBOUND : map BAR4 */ - phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE; - ls_pcie_atu_inbound_set(pcie, 3, 4, phys); + phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE); + ls_pcie_atu_inbound_set(pcie, pf, 2 + pf * BAR_NUM, 2, phys); + /* ATU 3 : INBOUND : map BAR2 */ + phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR2_SIZE); + ls_pcie_atu_inbound_set(pcie, pf, 3 + pf * BAR_NUM, 4, phys); /* ATU 0 : OUTBOUND : map MEM */ - ls_pcie_atu_outbound_set(pcie, 0, - PCIE_ATU_TYPE_MEM, - pcie->cfg_res.start, - 0, - CONFIG_SYS_PCI_MEMORY_SIZE); + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, (u64)pcie->cfg_res.start, + 0, atu_size); + + /* ATU 1 : OUTBOUND : map MEM */ + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_MEM, (u64)pcie->cfg_res.start + + atu_size, atu_size, atu_size); } /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) { + u32 mask; + /* The least inbound window is 4KiB */ - if (size < 4 * 1024) - return; + if (size < SZ_4K) + mask = 0; + else + mask = size - 1; switch (bar) { case 0: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_0); + writel(mask, bar_base + PCI_BASE_ADDRESS_0); break; case 1: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_1); + writel(mask, bar_base + PCI_BASE_ADDRESS_1); break; case 2: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_2); + writel(mask, bar_base + PCI_BASE_ADDRESS_2); writel(0, bar_base + PCI_BASE_ADDRESS_3); break; case 4: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_4); + writel(mask, bar_base + PCI_BASE_ADDRESS_4); writel(0, bar_base + PCI_BASE_ADDRESS_5); break; default: @@ -394,13 +406,28 @@ static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) static void ls_pcie_ep_setup_bars(void *bar_base) { - /* BAR0 - 32bit - 4K configuration */ + /* BAR0 - 32bit - configuration */ + ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); + /* BAR1 - 32bit - MSIX*/ + ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); + /* BAR2 - 64bit - MEM descriptor */ + ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); + /* BAR4 - 64bit - MEM*/ + ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); +} + +static void ls_pcie_ep_setup_vf_bars(void *bar_base) +{ + /* VF BAR0 MASK register at offset 0x19c*/ + bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0; + + /* VF-BAR0 - 32bit - configuration */ ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); - /* BAR1 - 32bit - 8K MSIX*/ + /* VF-BAR1 - 32bit - MSIX*/ ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); - /* BAR2 - 64bit - 4K MEM desciptor */ + /* VF-BAR2 - 64bit - MEM descriptor */ ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); - /* BAR4 - 64bit - 1M MEM*/ + /* VF-BAR4 - 64bit - MEM*/ ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); } @@ -412,25 +439,33 @@ static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) static void ls_pcie_setup_ep(struct ls_pcie *pcie) { u32 sriov; + u32 pf, vf; + void *bar_base = NULL; sriov = readl(pcie->dbi + PCIE_SRIOV); if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) { - int pf, vf; - + pcie->sriov_flag = 1; for (pf = 0; pf < PCIE_PF_NUM; pf++) { - for (vf = 0; vf <= PCIE_VF_NUM; vf++) { - ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf), - PCIE_PF_VF_CTRL); - - ls_pcie_ep_setup_bars(pcie->dbi); - ls_pcie_ep_setup_atu(pcie); + if (pcie->cfg2_flag) { + for (vf = 0; vf <= PCIE_VF_NUM; vf++) { + ctrl_writel(pcie, + PCIE_LCTRL0_VAL(pf, vf), + PCIE_PF_VF_CTRL); + } } + bar_base = pcie->dbi + + PCIE_MASK_OFFSET(pcie->cfg2_flag, pf); + ls_pcie_ep_setup_bars(bar_base); + ls_pcie_ep_setup_vf_bars(bar_base); + + ls_pcie_ep_setup_atu(pcie, pf); } - /* Disable CFG2 */ - ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); + + if (pcie->cfg2_flag) /* Disable CFG2 */ + ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); } else { ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); - ls_pcie_ep_setup_atu(pcie); + ls_pcie_ep_setup_atu(pcie, 0); } ls_pcie_ep_enable_cfg(pcie); @@ -502,6 +537,7 @@ static int ls_pcie_probe(struct udevice *dev) * for LS2088A series SoCs */ svr = get_svr(); + pcie->cfg2_flag = 1; svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || svr == SVR_LS2048A || svr == SVR_LS2044A || @@ -511,6 +547,7 @@ static int ls_pcie_probe(struct udevice *dev) LS2088A_PCIE_PHYS_SIZE * pcie->idx; pcie->cfg_res.end = pcie->cfg_res.start + cfg_size; pcie->ctrl = pcie->lut + 0x40000; + pcie->cfg2_flag = 0; } pcie->cfg0 = map_physmem(pcie->cfg_res.start, diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index ddfbba6..eb910ba 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver */ @@ -9,6 +9,7 @@ #define _PCIE_LAYERSCAPE_H_ #include <pci.h> #include <dm.h> +#include <linux/sizes.h> #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -85,11 +86,17 @@ #define PCIE_PF_NUM 2 #define PCIE_VF_NUM 64 +#define BAR_NUM 4 -#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */ -#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */ -#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ -#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ +#define PCIE_BAR0_SIZE SZ_4K /* 4K */ +#define PCIE_BAR1_SIZE SZ_8K /* 8K for MSIX */ +#define PCIE_BAR2_SIZE SZ_4K /* 4K */ +#define PCIE_BAR4_SIZE SZ_1M /* 1M */ + +#define PCIE_SRIOV_VFBAR0 0x19C +#define PCIE_CTRL1_FUNC_NUM(pf) (pf << 20) + +#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x20000 * (pf))) /* LUT registers */ #define PCIE_LUT_UDR(n) (0x800 + (n) * 8) @@ -144,6 +151,8 @@ struct ls_pcie { bool big_endian; bool enabled; int next_lut_index; + uint sriov_flag; + uint cfg2_flag; int mode; }; -- 1.7.1

4 16

[PATCH 1/1] drivers: net: add Broadcom bnxt driver for supported platforms
by Vladimir Olovyannikov 05 Dec '19

05 Dec '19

From: Suresh Channappa <suresh.channappa(a)broadcom.com> Add bnxt L2 driver support. This driver is used by several Broadcom iProc platforms. Signed-off-by: Suresh Channappa <suresh.channappa(a)broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov(a)broadcom.com> --- drivers/net/Kconfig | 1 + drivers/net/Makefile | 1 + drivers/net/bnxt/Kconfig | 8 + drivers/net/bnxt/Makefile | 5 + drivers/net/bnxt/bnxt.c | 2202 +++++++++++++++++++++++++++++++++++ drivers/net/bnxt/bnxt.h | 403 +++++++ drivers/net/bnxt/bnxt_dbg.h | 538 +++++++++ drivers/net/bnxt/bnxt_hsi.h | 889 ++++++++++++++ drivers/net/bnxt/bnxt_ver.h | 22 + drivers/net/bnxt/pci_ids.h | 17 + 10 files changed, 4086 insertions(+) create mode 100644 drivers/net/bnxt/Kconfig create mode 100644 drivers/net/bnxt/Makefile create mode 100644 drivers/net/bnxt/bnxt.c create mode 100644 drivers/net/bnxt/bnxt.h create mode 100644 drivers/net/bnxt/bnxt_dbg.h create mode 100644 drivers/net/bnxt/bnxt_hsi.h create mode 100644 drivers/net/bnxt/bnxt_ver.h create mode 100644 drivers/net/bnxt/pci_ids.h diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4182897d89..3c136eeaa7 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1,6 +1,7 @@ source "drivers/net/phy/Kconfig" source "drivers/net/pfe_eth/Kconfig" source "drivers/net/fsl-mc/Kconfig" +source "drivers/net/bnxt/Kconfig" config DM_ETH bool "Enable Driver Model for Ethernet drivers" diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 30991834ec..7b26cf9f2c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -3,6 +3,7 @@ # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +obj-$(CONFIG_BNXT_ETH) += bnxt/ obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o diff --git a/drivers/net/bnxt/Kconfig b/drivers/net/bnxt/Kconfig new file mode 100644 index 0000000000..0805f6e53d --- /dev/null +++ b/drivers/net/bnxt/Kconfig @@ -0,0 +1,8 @@ +config BNXT_ETH + bool "BNXT PCI support" + depends on DM_ETH && DM_PCI + help + This driver implements support for + Broadcom pcie BCM57320 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb + RDMA Ethernet Controller (bnxt pci controller). + The controller is used on Broadcom iProc platforms. diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile new file mode 100644 index 0000000000..6ba101b44c --- /dev/null +++ b/drivers/net/bnxt/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2019 Broadcom. + +# Broadcom nxe Ethernet driver +obj-y += bnxt.o \ No newline at end of file diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c new file mode 100644 index 0000000000..45199083b1 --- /dev/null +++ b/drivers/net/bnxt/bnxt.c @@ -0,0 +1,2202 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Broadcom. + */ + +#include <common.h> +#include <dm.h> +#include <env_flags.h> +#include <environment.h> +#include <errno.h> +#include <memalign.h> +#include <pci.h> +#include <net.h> +#include <asm/io.h> +#include <dm/device-internal.h> +#include <linux/ctype.h> +#include <linux/types.h> +#include "bnxt.h" +#include "bnxt_dbg.h" +#include "pci_ids.h" + +static void print_mac(u8 *mac, u8 flag); +static const char banner[] = DRV_MODULE_DESC " v" UBOOT_MODULE_VER ","; +static const char fw_ver[] = " FW v"; + +static void display_banner(struct bnxt *bp) +{ + int i; + + printf(banner); + printf(fw_ver); + printf("%d.%d.", bp->fw_maj, bp->fw_min); + printf("%d.%d\n", bp->fw_bld, bp->fw_rsvd); + printf("ETH MAC: "); + for (i = 0; i < ETH_ALEN; i++) { + printf("%02x", bp->mac_set[i]); + if (i != (ETH_ALEN - 1)) + printf(":"); + } + + printf(", Port(%d), PF(%d)\n", bp->port_idx, bp->ordinal_value); +} + +/* Broadcom ethernet driver PCI APIs. */ +static void bnxt_bring_pci(struct bnxt *bp) +{ + u16 cmd_reg = 0; + + pci_read_word16(bp->pdev, PCI_VENDOR_ID, &bp->vendor_id); + pci_read_word16(bp->pdev, PCI_DEVICE_ID, &bp->device_id); + pci_read_word16(bp->pdev, + PCI_SUBSYSTEM_VENDOR_ID, + &bp->subsystem_vendor); + pci_read_word16(bp->pdev, PCI_SUBSYSTEM_ID, &bp->subsystem_device); + pci_read_word16(bp->pdev, PCI_COMMAND, &bp->cmd_reg); + pci_read_byte(bp->pdev, PCICFG_ME_REGISTER, &bp->pf_num); + pci_read_byte(bp->pdev, PCI_INTERRUPT_LINE, &bp->irq); + bp->bar0 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + bp->bar1 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, PCI_REGION_MEM); + bp->bar2 = pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, PCI_REGION_MEM); + cmd_reg = bp->cmd_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + cmd_reg |= PCI_COMMAND_INTX_DISABLE; /* disable intr */ + pci_write_word(bp->pdev, PCI_COMMAND, cmd_reg); + pci_read_word16(bp->pdev, PCI_COMMAND, &cmd_reg); + dbg_pci(bp, __func__, cmd_reg); +} + +int bnxt_free_rx_iob(struct bnxt *bp) +{ + unsigned int i; + + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RX_IOB))) + return STATUS_SUCCESS; + + for (i = 0; i < bp->rx.buf_cnt; i++) { + if (bp->rx.iob[i]) { + free(bp->rx.iob[i]); + bp->rx.iob[i] = NULL; + } + } + + FLAG_RESET(bp->flag_hwrm, VALID_RX_IOB); + + return STATUS_SUCCESS; +} + +static void set_rx_desc(u8 *buf, void *iob, u16 cons_id, u32 iob_idx) +{ + struct rx_prod_pkt_bd *desc; + u16 off = cons_id * sizeof(struct rx_prod_pkt_bd); + + desc = (struct rx_prod_pkt_bd *)&buf[off]; + desc->flags_type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT; + desc->len = MAX_ETHERNET_PACKET_BUFFER_SIZE; + desc->opaque = iob_idx; + desc->dma.addr = virt_to_bus(iob); +} + +static int bnxt_alloc_rx_iob(struct bnxt *bp, u16 cons_id, u16 iob_idx) +{ + void *iob; + + iob = memalign(BNXT_DMA_ALIGNMENT, RX_STD_DMA_ALIGNED); + if (!iob) + return -ENOMEM; + + dbg_rx_iob(iob, iob_idx, cons_id); + set_rx_desc((u8 *)bp->rx.bd_virt, iob, cons_id, (u32)iob_idx); + bp->rx.iob[iob_idx] = iob; + + return 0; +} + +void bnxt_mm_init(struct bnxt *bp, const char *func) +{ + memset(bp->hwrm_addr_req, 0, REQ_BUFFER_SIZE); + memset(bp->hwrm_addr_resp, 0, RESP_BUFFER_SIZE); + memset(bp->cq.bd_virt, 0, CQ_RING_DMA_BUFFER_SIZE); + memset(bp->tx.bd_virt, 0, TX_RING_DMA_BUFFER_SIZE); + memset(bp->rx.bd_virt, 0, RX_RING_DMA_BUFFER_SIZE); + + bp->data_addr_mapping = virt_to_bus(bp->hwrm_addr_data); + bp->req_addr_mapping = virt_to_bus(bp->hwrm_addr_req); + bp->resp_addr_mapping = virt_to_bus(bp->hwrm_addr_resp); + bp->wait_link_timeout = LINK_DEFAULT_TIMEOUT; + bp->link_status = STATUS_LINK_DOWN; + bp->media_change = 1; + bp->mtu = MAX_ETHERNET_PACKET_BUFFER_SIZE; + bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; + bp->rx.buf_cnt = NUM_RX_BUFFERS; + bp->rx.ring_cnt = MAX_RX_DESC_CNT; + bp->tx.ring_cnt = MAX_TX_DESC_CNT; + bp->cq.ring_cnt = MAX_CQ_DESC_CNT; + bp->cq.completion_bit = 0x1; + bp->link_set = LINK_SPEED_DRV_100G; + dbg_mem(bp, func); +} + +void bnxt_free_mem(struct bnxt *bp) +{ + if (bp->cq.bd_virt) { + free(bp->cq.bd_virt); + bp->cq.bd_virt = NULL; + } + + if (bp->rx.bd_virt) { + free(bp->rx.bd_virt); + bp->rx.bd_virt = NULL; + } + + if (bp->tx.bd_virt) { + free(bp->tx.bd_virt); + bp->tx.bd_virt = NULL; + } + + if (bp->hwrm_addr_resp) { + free(bp->hwrm_addr_resp); + bp->resp_addr_mapping = 0; + bp->hwrm_addr_resp = NULL; + } + + if (bp->hwrm_addr_req) { + free(bp->hwrm_addr_req); + bp->req_addr_mapping = 0; + bp->hwrm_addr_req = NULL; + } + + if (bp->hwrm_addr_data) { + free(bp->hwrm_addr_data); + bp->data_addr_mapping = 0; + bp->hwrm_addr_data = NULL; + } + + dbg_mem_free_done(__func__); +} + +int bnxt_alloc_mem(struct bnxt *bp) +{ + bp->hwrm_addr_data = memalign(BNXT_DMA_ALIGNMENT, DMA_BUF_SIZE_ALIGNED); + bp->hwrm_addr_req = memalign(BNXT_DMA_ALIGNMENT, REQ_BUF_SIZE_ALIGNED); + bp->hwrm_addr_resp = MEM_HWRM_RESP; + + memset(&bp->tx, 0, sizeof(struct lm_tx_info_t)); + memset(&bp->rx, 0, sizeof(struct lm_rx_info_t)); + memset(&bp->cq, 0, sizeof(struct lm_cmp_info_t)); + + bp->tx.bd_virt = memalign(BNXT_DMA_ALIGNMENT, REQ_BUF_SIZE_ALIGNED); + bp->rx.bd_virt = memalign(BNXT_DMA_ALIGNMENT, REQ_BUF_SIZE_ALIGNED); + bp->cq.bd_virt = memalign(BNXT_DMA_ALIGNMENT, REQ_BUF_SIZE_ALIGNED); + + test_if(bp->hwrm_addr_req && + bp->hwrm_addr_resp && + bp->hwrm_addr_data && + bp->tx.bd_virt && + bp->rx.bd_virt && + bp->cq.bd_virt) { + bnxt_mm_init(bp, __func__); + return STATUS_SUCCESS; + } + + dbg_mem_alloc_fail(__func__); + bnxt_free_mem(bp); + + return -ENOMEM; +} + +static void hwrm_init(struct bnxt *bp, struct input *req, u16 cmd, u16 len) +{ + memset(req, 0, len); + req->req_type = cmd; + req->cmpl_ring = (u16)HWRM_NA_SIGNATURE; + req->target_id = (u16)HWRM_NA_SIGNATURE; + req->resp_addr = bp->resp_addr_mapping; + req->seq_id = bp->seq_id++; +} + +static void hwrm_write_req(struct bnxt *bp, void *req, u32 cnt) +{ + u32 i = 0; + + for (i = 0; i < cnt; i++) { + write32(((u32 *)req)[i], + (bp->bar0 + GRC_COM_CHAN_BASE + (i * 4))); + } + + writel(0x1, (bp->bar0 + GRC_COM_CHAN_BASE + GRC_COM_CHAN_TRIG)); +} + +static void short_hwrm_cmd_req(struct bnxt *bp, u16 len) +{ + struct hwrm_short_input sreq; + + memset(&sreq, 0, sizeof(struct hwrm_short_input)); + sreq.req_type = (u16)((struct input *)bp->hwrm_addr_req)->req_type; + sreq.signature = SHORT_REQ_SIGNATURE_SHORT_CMD; + sreq.size = len; + sreq.req_addr = bp->req_addr_mapping; + dbg_short_cmd((u8 *)&sreq, __func__, sizeof(struct hwrm_short_input)); + hwrm_write_req(bp, &sreq, sizeof(struct hwrm_short_input) / 4); +} + +static int wait_resp(struct bnxt *bp, u32 tmo, u16 len, const char *func) +{ + struct input *req = (struct input *)bp->hwrm_addr_req; + struct output *resp = (struct output *)bp->hwrm_addr_resp; + u8 *ptr = (u8 *)resp; + u32 idx; + u32 wait_cnt = HWRM_CMD_DEFAULT_MULTIPLAYER((u32)tmo); + u16 resp_len = 0; + u16 ret = STATUS_TIMEOUT; + + if (len > bp->hwrm_max_req_len) + short_hwrm_cmd_req(bp, len); + else + hwrm_write_req(bp, req, (u32)(len / 4)); + + for (idx = 0; idx < wait_cnt; idx++) { + resp_len = resp->resp_len; + test_if(resp->seq_id == req->seq_id && + resp->req_type == req->req_type && + ptr[resp_len - 1] == 1) { + bp->last_resp_code = resp->error_code; + ret = resp->error_code; + break; + } + + udelay(HWRM_CMD_POLL_WAIT_TIME); + } + + dbg_hw_cmd(bp, func, len, resp_len, tmo, ret); + + return (int)ret; +} + +static void bnxt_db_cq(struct bnxt *bp) +{ + writel(CQ_DOORBELL_KEY_IDX(bp->cq.cons_idx), bp->bar1); +} + +static void bnxt_db_rx(struct bnxt *bp, u32 idx) +{ + writel(RX_DOORBELL_KEY_RX | idx, bp->bar1); +} + +static void bnxt_db_tx(struct bnxt *bp, u32 idx) +{ + writel((u32)(TX_DOORBELL_KEY_TX | idx), bp->bar1); +} + +int iob_pad(void *packet, int length) +{ + if (length >= ETH_ZLEN) + return length; + + memset(((u8 *)packet + length), 0x00, (ETH_ZLEN - length)); + + return ETH_ZLEN; +} + +static inline u32 bnxt_tx_avail(struct bnxt *bp) +{ + barrier(); + + return TX_AVAIL(bp->tx.ring_cnt) - + ((bp->tx.prod_id - bp->tx.cons_id) & + (bp->tx.ring_cnt - 1)); +} + +void set_txq(struct bnxt *bp, int entry, dma_addr_t mapping, int len) +{ + struct tx_bd_short *prod_bd; + + prod_bd = (struct tx_bd_short *)BD_NOW(bp->tx.bd_virt, + entry, + sizeof(struct tx_bd_short)); + if (len < 512) + prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT512; + else if (len < 1024) + prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT1K; + else if (len < 2048) + prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT2K; + else + prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_GTE2K; + + prod_bd->flags_type |= TX_BD_FLAGS; + prod_bd->dma.addr = mapping; + prod_bd->len = len; + prod_bd->opaque = (u32)entry; + dump_tx_bd(prod_bd, (u16)(sizeof(struct tx_bd_short))); +} + +static void bnxt_tx_complete(struct bnxt *bp) +{ + bp->tx.cons_id = NEXT_IDX(bp->tx.cons_id, bp->tx.ring_cnt); + bp->tx.cnt++; + dump_tx_stat(bp); +} + +int post_rx_buffers(struct bnxt *bp) +{ + u16 cons_id = (bp->rx.cons_idx % bp->rx.ring_cnt); + u16 iob_idx; + + while (bp->rx.iob_cnt < bp->rx.buf_cnt) { + iob_idx = (cons_id % bp->rx.buf_cnt); + if (!bp->rx.iob[iob_idx]) { + if (bnxt_alloc_rx_iob(bp, cons_id, iob_idx) < 0) { + dbg_rx_alloc_iob_fail(iob_idx, cons_id); + break; + } + } + + cons_id = NEXT_IDX(cons_id, bp->rx.ring_cnt); + bp->rx.iob_cnt++; + } + + if (cons_id != bp->rx.cons_idx) { + dbg_rx_cid(bp->rx.cons_idx, cons_id); + bp->rx.cons_idx = cons_id; + bnxt_db_rx(bp, (u32)cons_id); + } + + FLAG_SET(bp->flag_hwrm, VALID_RX_IOB); + + return STATUS_SUCCESS; +} + +u8 bnxt_rx_drop(struct bnxt *bp, u8 *rx_buf, struct rx_pkt_cmpl_hi *rx_cmp_hi) +{ + u8 chksum_err = 0; + u8 i; + u16 error_flags; + + error_flags = (rx_cmp_hi->errors_v2 >> + RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT); + if (rx_cmp_hi->errors_v2 == 0x20 || rx_cmp_hi->errors_v2 == 0x21) + chksum_err = 1; + + if (error_flags && !chksum_err) { + bp->rx.err++; + return 1; + } + + for (i = 0; i < 6; i++) { + if (rx_buf[6 + i] != bp->mac_set[i]) + break; + } + + if (i == 6) { + bp->rx.dropped++; + return 2; /* Drop the loopback packets */ + } + + return 0; +} + +static void bnxt_adv_cq_index(struct bnxt *bp, u16 count) +{ + u16 cons_idx = bp->cq.cons_idx + count; + + if (cons_idx >= MAX_CQ_DESC_CNT) { + /* Toggle completion bit when the ring wraps. */ + bp->cq.completion_bit ^= 1; + cons_idx = cons_idx - MAX_CQ_DESC_CNT; + } + + bp->cq.cons_idx = cons_idx; +} + +void bnxt_adv_rx_index(struct bnxt *bp, u8 *iob, u32 iob_idx) +{ + u16 cons_id = (bp->rx.cons_idx % bp->rx.ring_cnt); + + set_rx_desc((u8 *)bp->rx.bd_virt, (void *)iob, cons_id, iob_idx); + cons_id = NEXT_IDX(cons_id, bp->rx.ring_cnt); + if (cons_id != bp->rx.cons_idx) { + dbg_rx_cid(bp->rx.cons_idx, cons_id); + bp->rx.cons_idx = cons_id; + bnxt_db_rx(bp, (u32)cons_id); + } +} + +void rx_process(struct bnxt *bp, struct rx_pkt_cmpl *rx_cmp, + struct rx_pkt_cmpl_hi *rx_cmp_hi) +{ + u32 desc_idx = rx_cmp->opaque; + u8 *iob = bp->rx.iob[desc_idx]; + + dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx); + bp->rx.iob_len = rx_cmp->len; + bp->rx.iob_rx = iob; + if (bnxt_rx_drop(bp, iob, rx_cmp_hi)) + bp->rx.iob_recv = PKT_DROPPED; + else + bp->rx.iob_recv = PKT_RECEIVED; + + bp->rx.rx_cnt++; + + dbg_rxp(bp->rx.iob_rx, bp->rx.iob_len, bp->rx.iob_recv); + bnxt_adv_rx_index(bp, iob, desc_idx); + bnxt_adv_cq_index(bp, 2); /* Rx completion is 2 entries. */ +} + +static int bnxt_rx_complete(struct bnxt *bp, struct rx_pkt_cmpl *rx_cmp) +{ + struct rx_pkt_cmpl_hi *rx_cmp_hi; + u8 completion_bit = bp->cq.completion_bit; + + if (bp->cq.cons_idx == (bp->cq.ring_cnt - 1)) { + rx_cmp_hi = (struct rx_pkt_cmpl_hi *)bp->cq.bd_virt; + completion_bit ^= 0x1; /* Ring has wrapped. */ + } else { + rx_cmp_hi = (struct rx_pkt_cmpl_hi *)(rx_cmp + 1); + } + + if (!((rx_cmp_hi->errors_v2 & RX_PKT_CMPL_V2) ^ completion_bit)) + rx_process(bp, rx_cmp, rx_cmp_hi); + + return NO_MORE_CQ_BD_TO_SERVICE; +} + +static int bnxt_hwrm_ver_get(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_ver_get_input); + struct hwrm_ver_get_input *req; + struct hwrm_ver_get_output *resp; + int rc; + + req = (struct hwrm_ver_get_input *)bp->hwrm_addr_req; + resp = (struct hwrm_ver_get_output *)bp->hwrm_addr_resp; + hwrm_init(bp, (void *)req, (u16)HWRM_VER_GET, cmd_len); + req->hwrm_intf_maj = HWRM_VERSION_MAJOR; + req->hwrm_intf_min = HWRM_VERSION_MINOR; + req->hwrm_intf_upd = HWRM_VERSION_UPDATE; + rc = wait_resp(bp, HWRM_CMD_DEFAULT_TIMEOUT, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + bp->hwrm_spec_code = + resp->hwrm_intf_maj_8b << 16 | + resp->hwrm_intf_min_8b << 8 | + resp->hwrm_intf_upd_8b; + bp->hwrm_cmd_timeout = (u32)resp->def_req_timeout; + if (!bp->hwrm_cmd_timeout) + bp->hwrm_cmd_timeout = (u32)HWRM_CMD_DEFAULT_TIMEOUT; + + if (resp->hwrm_intf_maj_8b >= 1) + bp->hwrm_max_req_len = resp->max_req_win_len; + + bp->chip_id = + resp->chip_rev << 24 | + resp->chip_metal << 16 | + resp->chip_bond_id << 8 | + resp->chip_platform_type; + bp->chip_num = resp->chip_num; + test_if((resp->dev_caps_cfg & SHORT_CMD_SUPPORTED) && + (resp->dev_caps_cfg & SHORT_CMD_REQUIRED)) + FLAG_SET(bp->flags, BNXT_FLAG_HWRM_SHORT_CMD_SUPP); + + bp->hwrm_max_ext_req_len = resp->max_ext_req_len; + bp->fw_maj = resp->hwrm_fw_maj_8b; + bp->fw_min = resp->hwrm_fw_min_8b; + bp->fw_bld = resp->hwrm_fw_bld_8b; + bp->fw_rsvd = resp->hwrm_fw_rsvd_8b; + print_fw_ver(resp, bp->hwrm_cmd_timeout); + + return STATUS_SUCCESS; +} + +/* Broadcom ethernet driver Function HW cmds APIs. */ +static int bnxt_hwrm_func_resource_qcaps(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_func_resource_qcaps_input); + struct hwrm_func_resource_qcaps_input *req; + struct hwrm_func_resource_qcaps_output *resp; + int rc; + + req = (struct hwrm_func_resource_qcaps_input *)bp->hwrm_addr_req; + resp = (struct hwrm_func_resource_qcaps_output *)bp->hwrm_addr_resp; + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_RESOURCE_QCAPS, cmd_len); + req->fid = (u16)HWRM_NA_SIGNATURE; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc != STATUS_SUCCESS) + return STATUS_SUCCESS; + + FLAG_SET(bp->flags, BNXT_FLAG_RESOURCE_QCAPS_SUPPORT); + /* VFs */ + bp->max_vfs = resp->max_vfs; + bp->vf_res_strategy = resp->vf_reservation_strategy; + /* vNICs */ + bp->min_vnics = resp->min_vnics; + bp->max_vnics = resp->max_vnics; + /* MSI-X */ + bp->max_msix = resp->max_msix; + /* Ring Groups */ + bp->min_hw_ring_grps = resp->min_hw_ring_grps; + bp->max_hw_ring_grps = resp->max_hw_ring_grps; + /* TX Rings */ + bp->min_tx_rings = resp->min_tx_rings; + bp->max_tx_rings = resp->max_tx_rings; + /* RX Rings */ + bp->min_rx_rings = resp->min_rx_rings; + bp->max_rx_rings = resp->max_rx_rings; + /* Completion Rings */ + bp->min_cp_rings = resp->min_cmpl_rings; + bp->max_cp_rings = resp->max_cmpl_rings; + /* RSS Contexts */ + bp->min_rsscos_ctxs = resp->min_rsscos_ctx; + bp->max_rsscos_ctxs = resp->max_rsscos_ctx; + /* L2 Contexts */ + bp->min_l2_ctxs = resp->min_l2_ctxs; + bp->max_l2_ctxs = resp->max_l2_ctxs; + /* Statistic Contexts */ + bp->min_stat_ctxs = resp->min_stat_ctx; + bp->max_stat_ctxs = resp->max_stat_ctx; + dbg_func_resource_qcaps(bp); + + return STATUS_SUCCESS; +} + +static u32 set_ring_info(struct bnxt *bp) +{ + u32 enables = 0; + + bp->num_cmpl_rings = DEFAULT_NUMBER_OF_CMPL_RINGS; + bp->num_tx_rings = DEFAULT_NUMBER_OF_TX_RINGS; + bp->num_rx_rings = DEFAULT_NUMBER_OF_RX_RINGS; + bp->num_hw_ring_grps = DEFAULT_NUMBER_OF_RING_GRPS; + bp->num_stat_ctxs = DEFAULT_NUMBER_OF_STAT_CTXS; + if (bp->min_cp_rings <= DEFAULT_NUMBER_OF_CMPL_RINGS) + bp->num_cmpl_rings = bp->min_cp_rings; + + if (bp->min_tx_rings <= DEFAULT_NUMBER_OF_TX_RINGS) + bp->num_tx_rings = bp->min_tx_rings; + + if (bp->min_rx_rings <= DEFAULT_NUMBER_OF_RX_RINGS) + bp->num_rx_rings = bp->min_rx_rings; + + if (bp->min_hw_ring_grps <= DEFAULT_NUMBER_OF_RING_GRPS) + bp->num_hw_ring_grps = bp->min_hw_ring_grps; + + if (bp->min_stat_ctxs <= DEFAULT_NUMBER_OF_STAT_CTXS) + bp->num_stat_ctxs = bp->min_stat_ctxs; + + print_num_rings(bp); + enables = (FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS | + FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS | + FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS | + FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS | + FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS); + + return enables; +} + +static void bnxt_hwrm_assign_resources(struct bnxt *bp) +{ + struct hwrm_func_cfg_input *req; + u32 enables = 0; + + if (FLAG_TEST(bp->flags, BNXT_FLAG_RESOURCE_QCAPS_SUPPORT)) + enables = set_ring_info(bp); + + req = (struct hwrm_func_cfg_input *)bp->hwrm_addr_req; + req->num_cmpl_rings = bp->num_cmpl_rings; + req->num_tx_rings = bp->num_tx_rings; + req->num_rx_rings = bp->num_rx_rings; + req->num_stat_ctxs = bp->num_stat_ctxs; + req->num_hw_ring_grps = bp->num_hw_ring_grps; + req->enables = enables; +} + +static int bnxt_hwrm_nvm_flush(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_nvm_flush_input); + struct hwrm_nvm_flush_input *req; + int rc; + + req = (struct hwrm_nvm_flush_input *)bp->hwrm_addr_req; + + hwrm_init(bp, (void *)req, (u16)HWRM_NVM_FLUSH, cmd_len); + + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_func_qcaps_req(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_func_qcaps_input); + struct hwrm_func_qcaps_input *req; + struct hwrm_func_qcaps_output *resp; + int rc; + + req = (struct hwrm_func_qcaps_input *)bp->hwrm_addr_req; + resp = (struct hwrm_func_qcaps_output *)bp->hwrm_addr_resp; + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_QCAPS, cmd_len); + req->fid = (u16)HWRM_NA_SIGNATURE; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + bp->fid = resp->fid; + bp->port_idx = (u8)resp->port_id; + + /* Get MAC address for this PF */ + memcpy(&bp->mac_addr[0], &resp->mac_address[0], ETH_ALEN); + + /* + * If environment variable is not set for MAC + * Use the controller MAC address + */ + test_if(!bp->mac_set[0] && !bp->mac_set[1] && + !bp->mac_set[2] && !bp->mac_set[3] && + !bp->mac_set[4] && !bp->mac_set[5]) + memcpy(&bp->mac_set[0], &bp->mac_addr[0], ETH_ALEN); + + print_func_qcaps(bp); + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_func_qcfg_req(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_func_qcfg_input); + struct hwrm_func_qcfg_input *req; + struct hwrm_func_qcfg_output *resp; + int rc; + + req = (struct hwrm_func_qcfg_input *)bp->hwrm_addr_req; + resp = (struct hwrm_func_qcfg_output *)bp->hwrm_addr_resp; + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_QCFG, cmd_len); + req->fid = (u16)HWRM_NA_SIGNATURE; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + if (resp->flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST) + FLAG_SET(bp->flags, BNXT_FLAG_MULTI_HOST); + + if (resp->port_partition_type & + FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0) + FLAG_SET(bp->flags, BNXT_FLAG_NPAR_MODE); + + bp->ordinal_value = (u8)resp->pci_id & 0x0F; + bp->stat_ctx_id = resp->stat_ctx_id; + memcpy(&bp->mac_addr[0], &resp->mac_address[0], ETH_ALEN); + print_func_qcfg(bp); + dbg_flags(__func__, bp->flags); + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_func_reset_req(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_func_reset_input); + struct hwrm_func_reset_input *req; + + req = (struct hwrm_func_reset_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_RESET, cmd_len); + req->func_reset_level = FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME; + + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); +} + +static int bnxt_hwrm_func_cfg_req(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_func_cfg_input); + struct hwrm_func_cfg_input *req; + + req = (struct hwrm_func_cfg_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_CFG, cmd_len); + req->fid = (u16)HWRM_NA_SIGNATURE; + bnxt_hwrm_assign_resources(bp); + + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); +} + +static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_func_drv_rgtr_input); + struct hwrm_func_drv_rgtr_input *req; + int rc; + + req = (struct hwrm_func_drv_rgtr_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_DRV_RGTR, cmd_len); + /* Register with HWRM */ + req->enables = FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | + FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD | + FUNC_DRV_RGTR_REQ_ENABLES_VER; + req->async_event_fwd[0] |= 0x01; + req->os_type = FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER; + req->ver_maj = UBOOT_VERSION_MAJOR; + req->ver_min = UBOOT_VERSION_MINOR; + req->ver_upd = UBOOT_VERSION_UPDATE; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_SET(bp->flag_hwrm, VALID_DRIVER_REG); + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_func_drv_unrgtr_input); + struct hwrm_func_drv_unrgtr_input *req; + int rc; + + if (!(FLAG_TEST(bp->flag_hwrm, VALID_DRIVER_REG))) + return STATUS_SUCCESS; + + req = (struct hwrm_func_drv_unrgtr_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_DRV_UNRGTR, cmd_len); + req->flags = FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_RESET(bp->flag_hwrm, VALID_DRIVER_REG); + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_cfa_l2_filter_alloc(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_cfa_l2_filter_alloc_input); + struct hwrm_cfa_l2_filter_alloc_input *req; + struct hwrm_cfa_l2_filter_alloc_output *resp; + int rc; + u32 flags = CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX; + u32 enables; + + req = (struct hwrm_cfa_l2_filter_alloc_input *)bp->hwrm_addr_req; + resp = (struct hwrm_cfa_l2_filter_alloc_output *)bp->hwrm_addr_resp; + enables = CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | + CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | + CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK; + + hwrm_init(bp, (void *)req, (u16)HWRM_CFA_L2_FILTER_ALLOC, cmd_len); + req->flags = flags; + req->enables = enables; + memcpy((char *)&req->l2_addr[0], (char *)&bp->mac_set[0], ETH_ALEN); + memset((char *)&req->l2_addr_mask[0], 0xff, ETH_ALEN); + memcpy((char *)&req->t_l2_addr[0], (char *)&bp->mac_set[0], ETH_ALEN); + memset((char *)&req->t_l2_addr_mask[0], 0xff, ETH_ALEN); + req->src_type = CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT; + req->src_id = (u32)bp->port_idx; + req->dst_id = bp->vnic_id; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_SET(bp->flag_hwrm, VALID_L2_FILTER); + bp->l2_filter_id = resp->l2_filter_id; + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_cfa_l2_filter_free(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_cfa_l2_filter_free_input); + struct hwrm_cfa_l2_filter_free_input *req; + int rc; + + if (!(FLAG_TEST(bp->flag_hwrm, VALID_L2_FILTER))) + return STATUS_SUCCESS; + + req = (struct hwrm_cfa_l2_filter_free_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_CFA_L2_FILTER_FREE, cmd_len); + req->l2_filter_id = bp->l2_filter_id; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_RESET(bp->flag_hwrm, VALID_L2_FILTER); + + return STATUS_SUCCESS; +} + +u32 bnxt_set_rx_mask(u32 rx_mask) +{ + u32 mask = 0; + + if (!rx_mask) + return mask; + mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; + if (rx_mask != RX_MASK_ACCEPT_NONE) { + if (rx_mask & RX_MASK_ACCEPT_MULTICAST) + mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; + + if (rx_mask & RX_MASK_ACCEPT_ALL_MULTICAST) + mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; + + if (rx_mask & RX_MASK_PROMISCUOUS_MODE) + mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; + } + + return mask; +} + +static int bnxt_hwrm_set_rx_mask(struct bnxt *bp, u32 rx_mask) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_cfa_l2_set_rx_mask_input); + struct hwrm_cfa_l2_set_rx_mask_input *req; + u32 mask = bnxt_set_rx_mask(rx_mask); + + req = (struct hwrm_cfa_l2_set_rx_mask_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_CFA_L2_SET_RX_MASK, cmd_len); + req->vnic_id = bp->vnic_id; + req->mask = mask; + + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); +} + +static int bnxt_hwrm_port_mac_cfg(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_port_mac_cfg_input); + struct hwrm_port_mac_cfg_input *req; + + req = (struct hwrm_port_mac_cfg_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_PORT_MAC_CFG, cmd_len); + req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; + + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); +} + +static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp, u16 idx) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_port_phy_qcfg_input); + struct hwrm_port_phy_qcfg_input *req; + struct hwrm_port_phy_qcfg_output *resp; + int rc; + + req = (struct hwrm_port_phy_qcfg_input *)bp->hwrm_addr_req; + resp = (struct hwrm_port_phy_qcfg_output *)bp->hwrm_addr_resp; + hwrm_init(bp, (void *)req, (u16)HWRM_PORT_PHY_QCFG, cmd_len); + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + if (idx & SUPPORT_SPEEDS) + bp->support_speeds = resp->support_speeds; + + if (idx & DETECT_MEDIA) + bp->media_detect = resp->module_status; + + if (idx & PHY_SPEED) + bp->current_link_speed = resp->link_speed; + + if (idx & PHY_STATUS) { + if (resp->link == PORT_PHY_QCFG_RESP_LINK_LINK) + bp->link_status = STATUS_LINK_ACTIVE; + else + bp->link_status = STATUS_LINK_DOWN; + } + + return STATUS_SUCCESS; +} + +u16 set_link_speed_mask(u16 link_cap) +{ + u16 speed_mask = 0; + + if (link_cap & SPEED_CAPABILITY_DRV_100M) + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB; + + if (link_cap & SPEED_CAPABILITY_DRV_1G) + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB; + + if (link_cap & SPEED_CAPABILITY_DRV_10G) + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB; + + if (link_cap & SPEED_CAPABILITY_DRV_25G) + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB; + + if (link_cap & SPEED_CAPABILITY_DRV_40G) + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB; + + if (link_cap & SPEED_CAPABILITY_DRV_50G) + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB; + + if (link_cap & SPEED_CAPABILITY_DRV_100G) + speed_mask |= PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB; + + return speed_mask; +} + +static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_port_phy_cfg_input); + struct hwrm_port_phy_cfg_input *req; + u32 flags; + u32 enables = 0; + u16 force_link_speed = 0; + u16 auto_link_speed_mask = 0; + u8 auto_mode = 0; + u8 auto_pause = 0; + u8 auto_duplex = 0; + + /* + * If multi_host or NPAR is set to TRUE, + * do not issue hwrm_port_phy_cfg + */ + if (FLAG_TEST(bp->flags, PORT_PHY_FLAGS)) { + dbg_flags(__func__, bp->flags); + return STATUS_SUCCESS; + } + + req = (struct hwrm_port_phy_cfg_input *)bp->hwrm_addr_req; + flags = PORT_PHY_CFG_REQ_FLAGS_FORCE | + PORT_PHY_CFG_REQ_FLAGS_RESET_PHY; + + switch (GET_MEDIUM_SPEED(bp->medium)) { + case MEDIUM_SPEED_1000MBPS: + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; + break; + case MEDIUM_SPEED_10GBPS: + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; + break; + case MEDIUM_SPEED_25GBPS: + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; + break; + case MEDIUM_SPEED_40GBPS: + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; + break; + case MEDIUM_SPEED_50GBPS: + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; + break; + case MEDIUM_SPEED_100GBPS: + force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; + break; + default: + /* Enable AUTONEG by default */ + auto_mode = PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; + flags &= ~PORT_PHY_CFG_REQ_FLAGS_FORCE; + enables |= PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE | + PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK | + PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX | + PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE; + auto_pause = PORT_PHY_CFG_REQ_AUTO_PAUSE_TX | + PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; + auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH; + auto_link_speed_mask = bp->support_speeds; + break; + } + + hwrm_init(bp, (void *)req, (u16)HWRM_PORT_PHY_CFG, cmd_len); + req->flags = flags; + req->enables = enables; + req->port_id = bp->port_idx; + req->force_link_speed = force_link_speed; + req->auto_mode = auto_mode; + req->auto_duplex = auto_duplex; + req->auto_pause = auto_pause; + req->auto_link_speed_mask = auto_link_speed_mask; + + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); +} + +static int bnxt_qphy_link(struct bnxt *bp) +{ + u16 flag = QCFG_PHY_ALL; + + /* Query Link Status */ + if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS) + return STATUS_FAILURE; + + if (bp->link_status != STATUS_LINK_ACTIVE) { + /* + * Configure link if it is not up. + * try to bring link up, but don't return + * failure if port_phy_cfg() fails + */ + bnxt_hwrm_port_phy_cfg(bp); + /* refresh link speed values after bringing link up */ + if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS) + return STATUS_FAILURE; + } + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_stat_ctx_alloc_input); + struct hwrm_stat_ctx_alloc_input *req; + struct hwrm_stat_ctx_alloc_output *resp; + int rc; + + req = (struct hwrm_stat_ctx_alloc_input *)bp->hwrm_addr_req; + resp = (struct hwrm_stat_ctx_alloc_output *)bp->hwrm_addr_resp; + hwrm_init(bp, (void *)req, (u16)HWRM_STAT_CTX_ALLOC, cmd_len); + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_SET(bp->flag_hwrm, VALID_STAT_CTX); + bp->stat_ctx_id = (u16)resp->stat_ctx_id; + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_stat_ctx_free_input); + struct hwrm_stat_ctx_free_input *req; + int rc; + + if (!(FLAG_TEST(bp->flag_hwrm, VALID_STAT_CTX))) + return STATUS_SUCCESS; + + req = (struct hwrm_stat_ctx_free_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_STAT_CTX_FREE, cmd_len); + req->stat_ctx_id = (u32)bp->stat_ctx_id; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_RESET(bp->flag_hwrm, VALID_STAT_CTX); + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_ring_free_grp(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_ring_grp_free_input); + struct hwrm_ring_grp_free_input *req; + int rc; + + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_GRP))) + return STATUS_SUCCESS; + + req = (struct hwrm_ring_grp_free_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_RING_GRP_FREE, cmd_len); + req->ring_group_id = (u32)bp->ring_grp_id; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_RESET(bp->flag_hwrm, VALID_RING_GRP); + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_ring_alloc_grp(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_ring_grp_alloc_input); + struct hwrm_ring_grp_alloc_input *req; + struct hwrm_ring_grp_alloc_output *resp; + int rc; + + req = (struct hwrm_ring_grp_alloc_input *)bp->hwrm_addr_req; + resp = (struct hwrm_ring_grp_alloc_output *)bp->hwrm_addr_resp; + hwrm_init(bp, (void *)req, (u16)HWRM_RING_GRP_ALLOC, cmd_len); + req->cr = bp->cq_ring_id; + req->rr = bp->rx_ring_id; + req->ar = (u16)HWRM_NA_SIGNATURE; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_SET(bp->flag_hwrm, VALID_RING_GRP); + bp->ring_grp_id = (u16)resp->ring_group_id; + + return STATUS_SUCCESS; +} + +int bnxt_hwrm_ring_free(struct bnxt *bp, u16 ring_id, u8 ring_type) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_ring_free_input); + struct hwrm_ring_free_input *req; + + req = (struct hwrm_ring_free_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_RING_FREE, cmd_len); + req->ring_type = ring_type; + req->ring_id = ring_id; + + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); +} + +static int bnxt_hwrm_ring_alloc(struct bnxt *bp, + dma_addr_t ring_map, + u16 length, + u16 ring_id, + u8 ring_type, + u8 int_mode) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_ring_alloc_input); + struct hwrm_ring_alloc_input *req; + struct hwrm_ring_alloc_output *resp; + int rc; + + req = (struct hwrm_ring_alloc_input *)bp->hwrm_addr_req; + resp = (struct hwrm_ring_alloc_output *)bp->hwrm_addr_resp; + hwrm_init(bp, (void *)req, (u16)HWRM_RING_ALLOC, cmd_len); + req->ring_type = ring_type; + req->page_tbl_addr = ring_map; + req->page_size = LM_PAGE_SIZE; + req->length = (u32)length; + req->cmpl_ring_id = ring_id; + req->int_mode = int_mode; + if (ring_type == RING_ALLOC_REQ_RING_TYPE_TX) { + req->queue_id = TX_RING_QID; + } else if (ring_type == RING_ALLOC_REQ_RING_TYPE_RX) { + req->queue_id = RX_RING_QID; + req->enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID; + req->rx_buf_size = MAX_ETHERNET_PACKET_BUFFER_SIZE; + } + + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + if (ring_type == RING_ALLOC_REQ_RING_TYPE_L2_CMPL) { + FLAG_SET(bp->flag_hwrm, VALID_RING_CQ); + bp->cq_ring_id = resp->ring_id; + } else if (ring_type == RING_ALLOC_REQ_RING_TYPE_TX) { + FLAG_SET(bp->flag_hwrm, VALID_RING_TX); + bp->tx_ring_id = resp->ring_id; + } else if (ring_type == RING_ALLOC_REQ_RING_TYPE_RX) { + FLAG_SET(bp->flag_hwrm, VALID_RING_RX); + bp->rx_ring_id = resp->ring_id; + } + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_ring_alloc_cq(struct bnxt *bp) +{ + return bnxt_hwrm_ring_alloc(bp, + virt_to_bus(bp->cq.bd_virt), + bp->cq.ring_cnt, + 0, + RING_ALLOC_REQ_RING_TYPE_L2_CMPL, + BNXT_CQ_INTR_MODE()); +} + +static int bnxt_hwrm_ring_alloc_tx(struct bnxt *bp) +{ + return bnxt_hwrm_ring_alloc(bp, + virt_to_bus(bp->tx.bd_virt), + bp->tx.ring_cnt, bp->cq_ring_id, + RING_ALLOC_REQ_RING_TYPE_TX, + BNXT_INTR_MODE()); +} + +static int bnxt_hwrm_ring_alloc_rx(struct bnxt *bp) +{ + return bnxt_hwrm_ring_alloc(bp, + virt_to_bus(bp->rx.bd_virt), + bp->rx.ring_cnt, + bp->cq_ring_id, + RING_ALLOC_REQ_RING_TYPE_RX, + BNXT_INTR_MODE()); +} + +static int bnxt_hwrm_ring_free_cq(struct bnxt *bp) +{ + int ret = STATUS_SUCCESS; + + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_CQ))) + return ret; + + ret = RING_FREE(bp, bp->cq_ring_id, RING_FREE_REQ_RING_TYPE_L2_CMPL); + if (ret == STATUS_SUCCESS) + FLAG_RESET(bp->flag_hwrm, VALID_RING_CQ); + + return ret; +} + +static int bnxt_hwrm_ring_free_tx(struct bnxt *bp) +{ + int ret = STATUS_SUCCESS; + + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_TX))) + return ret; + + ret = RING_FREE(bp, bp->tx_ring_id, RING_FREE_REQ_RING_TYPE_TX); + if (ret == STATUS_SUCCESS) + FLAG_RESET(bp->flag_hwrm, VALID_RING_TX); + + return ret; +} + +static int bnxt_hwrm_ring_free_rx(struct bnxt *bp) +{ + int ret = STATUS_SUCCESS; + + if (!(FLAG_TEST(bp->flag_hwrm, VALID_RING_RX))) + return ret; + + ret = RING_FREE(bp, bp->rx_ring_id, RING_FREE_REQ_RING_TYPE_RX); + if (ret == STATUS_SUCCESS) + FLAG_RESET(bp->flag_hwrm, VALID_RING_RX); + + return ret; +} + +static int bnxt_hwrm_vnic_alloc(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_vnic_alloc_input); + struct hwrm_vnic_alloc_input *req; + struct hwrm_vnic_alloc_output *resp; + int rc; + + req = (struct hwrm_vnic_alloc_input *)bp->hwrm_addr_req; + resp = (struct hwrm_vnic_alloc_output *)bp->hwrm_addr_resp; + hwrm_init(bp, (void *)req, (u16)HWRM_VNIC_ALLOC, cmd_len); + req->flags = VNIC_ALLOC_REQ_FLAGS_DEFAULT; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_SET(bp->flag_hwrm, VALID_VNIC_ID); + bp->vnic_id = resp->vnic_id; + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_vnic_free(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_vnic_free_input); + struct hwrm_vnic_free_input *req; + int rc; + + if (!(FLAG_TEST(bp->flag_hwrm, VALID_VNIC_ID))) + return STATUS_SUCCESS; + + req = (struct hwrm_vnic_free_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_VNIC_FREE, cmd_len); + req->vnic_id = bp->vnic_id; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + if (rc) + return STATUS_FAILURE; + + FLAG_RESET(bp->flag_hwrm, VALID_VNIC_ID); + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_vnic_cfg(struct bnxt *bp) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_vnic_cfg_input); + struct hwrm_vnic_cfg_input *req; + + req = (struct hwrm_vnic_cfg_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_VNIC_CFG, cmd_len); + req->enables = VNIC_CFG_REQ_ENABLES_MRU; + req->mru = bp->mtu; + req->enables |= VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP; + req->dflt_ring_grp = bp->ring_grp_id; + req->vnic_id = bp->vnic_id; + + return wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); +} + +static int set_phy_speed(struct bnxt *bp) +{ + char name[20]; + char name1[20]; + u16 flag = PHY_STATUS | PHY_SPEED | DETECT_MEDIA; + + /* Query Link Status */ + if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS) + return STATUS_FAILURE; + + switch (bp->current_link_speed) { + case PORT_PHY_QCFG_RESP_LINK_SPEED_100GB: + sprintf(name, "%s %s", str_100, str_gbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_50GB: + sprintf(name, "%s %s", str_50, str_gbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_40GB: + sprintf(name, "%s %s", str_40, str_gbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_25GB: + sprintf(name, "%s %s", str_25, str_gbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_20GB: + sprintf(name, "%s %s", str_20, str_gbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_10GB: + sprintf(name, "%s %s", str_10, str_gbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB: + sprintf(name, "%s %s", str_2_5, str_gbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_2GB: + sprintf(name, "%s %s", str_2, str_gbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_1GB: + sprintf(name, "%s %s", str_1, str_gbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_100MB: + sprintf(name, "%s %s", str_100, str_mbps); + break; + case PORT_PHY_QCFG_RESP_LINK_SPEED_10MB: + sprintf(name, "%s %s", str_10, str_mbps); + break; + default: + sprintf(name, "%s %x", str_unknown, bp->current_link_speed); + } + + sprintf(name1, "bnxt_eth%u_phy_speed", bp->cardnum); + env_set(name1, name); + dbg_phy_speed(bp, name); + + return STATUS_SUCCESS; +} + +static int set_phy_link(struct bnxt *bp, u32 tmo) +{ + char name[32]; + int ret; + + set_phy_speed(bp); + dbg_link_status(bp); + if (bp->link_status == STATUS_LINK_ACTIVE) { + dbg_link_state(bp, tmo); + sprintf(name, "bnxt_eth%u_link", bp->cardnum); + env_set(name, "up"); + sprintf(name, "bnxt_eth%u_media", bp->cardnum); + env_set(name, "connected"); + ret = STATUS_SUCCESS; + } else { + sprintf(name, "bnxt_eth%u_link", bp->cardnum); + env_set(name, "down"); + sprintf(name, "bnxt_eth%u_media", bp->cardnum); + env_set(name, "disconnected"); + ret = STATUS_FAILURE; + } + + return ret; +} + +static int get_phy_link(struct bnxt *bp) +{ + u16 flag = PHY_STATUS | PHY_SPEED | DETECT_MEDIA; + + dbg_chip_info(bp); + /* Query Link Status */ + if (bnxt_hwrm_port_phy_qcfg(bp, flag) != STATUS_SUCCESS) + return STATUS_FAILURE; + + set_phy_link(bp, 100); + + return STATUS_SUCCESS; +} + +static int bnxt_hwrm_set_async_event(struct bnxt *bp) +{ + int rc; + u16 cmd_len = (u16)sizeof(struct hwrm_func_cfg_input); + struct hwrm_func_cfg_input *req; + + req = (struct hwrm_func_cfg_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_FUNC_CFG, cmd_len); + req->fid = (u16)HWRM_NA_SIGNATURE; + req->enables = FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR; + req->async_event_cr = bp->cq_ring_id; + rc = wait_resp(bp, bp->hwrm_cmd_timeout, cmd_len, __func__); + + return rc; +} + +int bnxt_hwrm_get_nvmem(struct bnxt *bp, + u16 data_len, + u16 option_num, + u16 dimensions, + u16 index_0) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_nvm_get_variable_input); + struct hwrm_nvm_get_variable_input *req; + + req = (struct hwrm_nvm_get_variable_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_NVM_GET_VARIABLE, cmd_len); + req->dest_data_addr = bp->data_addr_mapping; + req->data_len = data_len; + req->option_num = option_num; + req->dimensions = dimensions; + req->index_0 = index_0; + + return wait_resp(bp, + HWRM_CMD_FLASH_MULTIPLAYER(bp->hwrm_cmd_timeout), + cmd_len, + __func__); +} + +static void set_medium(struct bnxt *bp) +{ + switch (bp->link_set & LINK_SPEED_DRV_MASK) { + case LINK_SPEED_DRV_1G: + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_1000MBPS); + break; + case LINK_SPEED_DRV_2_5G: + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_2500MBPS); + break; + case LINK_SPEED_DRV_10G: + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_10GBPS); + break; + case LINK_SPEED_DRV_25G: + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_25GBPS); + break; + case LINK_SPEED_DRV_40G: + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_40GBPS); + break; + case LINK_SPEED_DRV_50G: + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_50GBPS); + break; + case LINK_SPEED_DRV_100G: + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_100GBPS); + break; + case LINK_SPEED_DRV_200G: + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_200GBPS); + break; + case LINK_SPEED_DRV_AUTONEG: + bp->medium = SET_MEDIUM_SPEED(bp, MEDIUM_SPEED_AUTONEG); + break; + default: + bp->medium = SET_MEDIUM_DUPLEX(bp, MEDIUM_FULL_DUPLEX); + break; + } +} + +static int bnxt_hwrm_get_link_speed(struct bnxt *bp) +{ + u32 *ptr32 = (u32 *)bp->hwrm_addr_data; + + if (bnxt_hwrm_get_nvmem(bp, + 4, + (u16)LINK_SPEED_DRV_NUM, + 1, + (u16)bp->port_idx) != STATUS_SUCCESS) + return STATUS_FAILURE; + + bp->link_set = *ptr32; + bp->link_set &= SPEED_DRV_MASK; + set_medium(bp); + + return STATUS_SUCCESS; +} + +typedef int (*hwrm_func_t)(struct bnxt *bp); + +hwrm_func_t down_chip[] = { + bnxt_hwrm_cfa_l2_filter_free, /* Free l2 filter */ + bnxt_free_rx_iob, /* Free rx iob */ + bnxt_hwrm_vnic_free, /* Free vnic */ + bnxt_hwrm_ring_free_grp, /* Free ring group */ + bnxt_hwrm_ring_free_rx, /* Free rx ring */ + bnxt_hwrm_ring_free_tx, /* Free tx ring */ + bnxt_hwrm_ring_free_cq, /* Free CQ ring */ + bnxt_hwrm_stat_ctx_free, /* Free Stat ctx */ + bnxt_hwrm_func_drv_unrgtr, /* unreg driver */ + NULL, +}; + +hwrm_func_t bring_chip[] = { + bnxt_hwrm_ver_get, /* HWRM_VER_GET */ + bnxt_hwrm_func_reset_req, /* HWRM_FUNC_RESET */ + bnxt_hwrm_func_drv_rgtr, /* HWRM_FUNC_DRV_RGTR */ + bnxt_hwrm_func_resource_qcaps, /* HWRM_FUNC_RESOURCE_QCAPS */ + bnxt_hwrm_func_qcfg_req, /* HWRM_FUNC_QCFG */ + bnxt_hwrm_func_qcaps_req, /* HWRM_FUNC_QCAPS */ + bnxt_hwrm_get_link_speed, /* HWRM_NVM_GET_VARIABLE - 203 */ + bnxt_hwrm_port_mac_cfg, /* HWRM_PORT_MAC_CFG */ + bnxt_qphy_link, /* HWRM_PORT_PHY_QCFG */ + bnxt_hwrm_func_cfg_req, /* HWRM_FUNC_CFG - ring resource*/ + bnxt_hwrm_stat_ctx_alloc, /* Allocate Stat Ctx ID */ + bnxt_hwrm_ring_alloc_cq, /* Allocate CQ Ring */ + bnxt_hwrm_ring_alloc_tx, /* Allocate Tx ring */ + bnxt_hwrm_ring_alloc_rx, /* Allocate Rx Ring */ + bnxt_hwrm_ring_alloc_grp, /* Create Ring Group */ + post_rx_buffers, /* Post RX buffers */ + bnxt_hwrm_set_async_event, /* ENABLES_ASYNC_EVENT_CR */ + bnxt_hwrm_vnic_alloc, /* Alloc VNIC */ + bnxt_hwrm_vnic_cfg, /* Config VNIC */ + bnxt_hwrm_cfa_l2_filter_alloc, /* Alloc L2 Filter */ + get_phy_link, /* Get Physical Link */ + NULL, +}; + +int bnxt_hwrm_run(hwrm_func_t cmds[], struct bnxt *bp) +{ + hwrm_func_t *ptr; + int ret; + + for (ptr = cmds; *ptr; ++ptr) { + ret = (*ptr)(bp); + if (ret) + return STATUS_FAILURE; + } + + return STATUS_SUCCESS; +} + +#define bnxt_down_chip(bp) bnxt_hwrm_run(down_chip, bp) +#define bnxt_bring_chip(bp) bnxt_hwrm_run(bring_chip, bp) + +/* Broadcom ethernet driver Network interface APIs. */ +static int bnxt_start(struct udevice *dev) +{ + struct bnxt *bp = dev_get_priv(dev); + + if (bnxt_hwrm_set_rx_mask(bp, RX_MASK) != STATUS_SUCCESS) + return STATUS_FAILURE; + + return STATUS_SUCCESS; +} + +static int bnxt_send(struct udevice *dev, void *packet, int length) +{ + struct bnxt *bp = dev_get_priv(dev); + int len; + u16 entry; + dma_addr_t mapping; + + if (bnxt_tx_avail(bp) < 1) { + dbg_no_tx_bd(); + return -ENOBUFS; + } + + entry = bp->tx.prod_id; + len = iob_pad(packet, length); + mapping = virt_to_bus(packet); + set_txq(bp, entry, mapping, len); + entry = NEXT_IDX(entry, bp->tx.ring_cnt); + dump_tx_pkt(packet, mapping, len); + bnxt_db_tx(bp, (u32)entry); + bp->tx.prod_id = entry; + bp->tx.cnt_req++; + bnxt_tx_complete(bp); + + return 0; +} + +static void bnxt_link_evt(struct bnxt *bp, struct cmpl_base *cmp) +{ + struct hwrm_async_event_cmpl *evt; + + evt = (struct hwrm_async_event_cmpl *)cmp; + switch (evt->event_id) { + case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: + if (evt->event_data1 & 0x01) + bp->link_status = STATUS_LINK_ACTIVE; + else + bp->link_status = STATUS_LINK_DOWN; + + set_phy_link(bp, 0); + break; + default: + break; + } +} + +static int bnxt_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct bnxt *bp = dev_get_priv(dev); + struct cmpl_base *cmp; + u16 old_cons_idx = bp->cq.cons_idx; + int done = SERVICE_NEXT_CQ_BD; + u32 cq_type; + + while (done == SERVICE_NEXT_CQ_BD) { + cmp = (struct cmpl_base *)BD_NOW(bp->cq.bd_virt, + bp->cq.cons_idx, + sizeof(struct cmpl_base)); + if ((cmp->info3_v & CMPL_BASE_V) ^ bp->cq.completion_bit) + break; + + cq_type = cmp->type & CMPL_BASE_TYPE_MASK; + dump_evt((u8 *)cmp, cq_type, bp->cq.cons_idx); + dump_CQ(cmp, bp->cq.cons_idx); + switch (cq_type) { + case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: + bnxt_link_evt(bp, cmp); + /* Fall through */ + case CMPL_BASE_TYPE_TX_L2: + case CMPL_BASE_TYPE_STAT_EJECT: + bnxt_adv_cq_index(bp, 1); + break; + case CMPL_BASE_TYPE_RX_L2: + done = bnxt_rx_complete(bp, (struct rx_pkt_cmpl *)cmp); + break; + default: + done = NO_MORE_CQ_BD_TO_SERVICE; + break; + } + } + + if (bp->cq.cons_idx != old_cons_idx) + bnxt_db_cq(bp); + + if (bp->rx.iob_recv == PKT_RECEIVED) { + *packetp = bp->rx.iob_rx; + return bp->rx.iob_len; + } + + return -EAGAIN; +} + +static void bnxt_stop(struct udevice *dev) +{ + struct bnxt *bp = dev_get_priv(dev); + + bnxt_hwrm_set_rx_mask(bp, 0); +} + +static int bnxt_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct bnxt *bp = dev_get_priv(dev); + + dbg_rx_pkt(bp, __func__, packet, length); + bp->rx.iob_recv = PKT_DONE; + bp->rx.iob_len = 0; + bp->rx.iob_rx = NULL; + + return 0; +} + +static const struct eth_ops bnxt_eth_ops = { + .start = bnxt_start, + .send = bnxt_send, + .recv = bnxt_recv, + .stop = bnxt_stop, + .free_pkt = bnxt_free_pkt, +}; + +static const struct udevice_id bnxt_eth_ids[] = { + { .compatible = "broadcom,nxe" }, + { } +}; + +static int num_cards; /* Number of bnxt devices seen so far */ + +static int bnxt_eth_bind(struct udevice *dev) +{ + char name[20]; + + sprintf(name, "bnxt_eth%u", num_cards++); + + return device_set_name(dev, name); +} + +static int bnxt_eth_probe(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct bnxt *bp = dev_get_priv(dev); + int err; + + bp->name = dev->name; + bp->pdev = (struct udevice *)dev; + bp->cardnum = trailing_strtol(dev->name); + bnxt_bring_pci(bp); + err = bnxt_alloc_mem(bp); + if (err) + goto down_pci; + + eth_env_get_enetaddr_by_index("eth", bp->cardnum + 1, bp->mac_set); + err = bnxt_bring_chip(bp); + if (err) + goto down_chip; + + display_banner(bp); + memcpy(plat->enetaddr, bp->mac_set, ETH_ALEN); + /* + * Now, driver probe /remove manually called. + * Avoid reentrant of probe / remove command. + */ + bp->drv_load = 1; + + return 0; +down_chip: + bnxt_down_chip(bp); + bnxt_free_mem(bp); +down_pci: + return err; +} + +static int bnxt_eth_remove(struct udevice *dev) +{ + struct bnxt *bp = dev_get_priv(dev); + + bnxt_down_chip(bp); /* Down chip */ + device_remove(dev, DM_REMOVE_NORMAL); + bnxt_free_mem(bp); + bp->drv_load = 0; + + return 0; +} + +U_BOOT_DRIVER(eth_bnxt) = { + .name = "eth_bnxt", + .id = UCLASS_ETH, + .of_match = bnxt_eth_ids, + .bind = bnxt_eth_bind, + .ops = &bnxt_eth_ops, + .priv_auto_alloc_size = sizeof(struct bnxt), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +U_BOOT_PCI_DEVICE(eth_bnxt, bnxt_nics); + +static void print_mac(u8 *mac, u8 flag) +{ + printf("bnxt "); + if (flag) + printf("Set"); + else + printf("Get"); + + printf(" MAC :"); + printf(" %02x:%02x:%02x:", mac[0], mac[1], mac[2]); + printf("%02x:%02x:%02x\n", mac[3], mac[4], mac[5]); +} + +static void env_set_ethaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct bnxt *bp = dev_get_priv(dev); + char cmd[100]; + char var[32]; + u8 mac_env[ARP_HLEN]; + + eth_env_get_enetaddr_by_index("eth", bp->cardnum + 1, mac_env); + if (!memcmp(plat->enetaddr, mac_env, ARP_HLEN)) + return; + + sprintf(var, "%s%daddr", "eth", bp->cardnum + 1); + sprintf(cmd, "%s %s %pM", "env set -f", var, plat->enetaddr); + run_command(cmd, CMD_FLAG_ENV); + printf("\n"); + run_command("saveenv", CMD_FLAG_ENV); +} + +static void env_del_ethaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct bnxt *bp = dev_get_priv(dev); + char cmd[100]; + char var[32]; + + sprintf(var, "%s%daddr", "eth", bp->cardnum + 1); + sprintf(cmd, "%s %s %pM", "env delete -f", var, plat->enetaddr); + run_command(cmd, CMD_FLAG_ENV); + run_command("saveenv", CMD_FLAG_ENV); + printf("\n"); +} + +static int bnxt_drv_probe(struct udevice *dev) +{ + int ret; + + ret = bnxt_eth_probe(dev); + if (ret) + return CMD_RET_FAILURE; + + /* copy ROM MAC to environment. */ + env_set_ethaddr(dev); + + return CMD_RET_SUCCESS; +} + +static int bnxt_drv_remove(struct udevice *dev) +{ + struct bnxt *bp = dev_get_priv(dev); + + env_del_ethaddr(dev); + bnxt_eth_remove(dev); + printf("bnxt_eth%d - Device removed\n", bp->cardnum); + + return CMD_RET_SUCCESS; +} + +static int bnxt_get_mac(struct bnxt *bp) +{ + print_mac(&bp->mac_set[0], 0); + + return CMD_RET_SUCCESS; +} + +void prn_link_speed(u32 speed, u8 flag) +{ + u32 speed1 = ((speed & LINK_SPEED_DRV_MASK) >> LINK_SPEED_DRV_SHIFT); + + printf("bnxt "); + if (flag) + printf("Set"); + else + printf("Get"); + + printf(" Link Speed : "); + switch (speed & LINK_SPEED_DRV_MASK) { + case LINK_SPEED_DRV_1G: + printf("1 GBPS"); + break; + case LINK_SPEED_DRV_2_5G: + printf("2.5 GBPS"); + break; + case LINK_SPEED_DRV_10G: + printf("10 GBPS"); + break; + case LINK_SPEED_DRV_25G: + printf("25 GBPS"); + break; + case LINK_SPEED_DRV_40G: + printf("40 GBPS"); + break; + case LINK_SPEED_DRV_50G: + printf("50 GBPS"); + break; + case LINK_SPEED_DRV_100G: + printf("100 GBPS"); + break; + case LINK_SPEED_DRV_200G: + printf("200 GBPS"); + break; + case LINK_SPEED_DRV_AUTONEG: + printf("AUTONEG"); + break; + default: + printf("%x", speed1); + break; + } + + printf("\n"); +} + +static int bnxt_get_link_speed(struct bnxt *bp) +{ + if (bnxt_hwrm_get_link_speed(bp) == STATUS_SUCCESS) + prn_link_speed(bp->link_set, 0); + + return CMD_RET_SUCCESS; +} + +static int bnxt_supported_speed(struct bnxt *bp) +{ + if (bnxt_hwrm_port_phy_qcfg(bp, SUPPORT_SPEEDS) != STATUS_SUCCESS) + return CMD_RET_FAILURE; + + printf("bnxt - Supported speed\n\n"); + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_1GB) + printf(" (1) - 1 GBPS\n"); + + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_10GB) + printf(" (2) - 10 GBPS\n"); + + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_25GB) + printf(" (3) - 25 GBPS\n"); + + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_50GB) + printf(" (5) - 50 GBPS\n"); + + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_100GB) + printf(" (6) - 100 GBPS\n"); + + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_200GB) + printf(" (7) - 200 GBPS\n"); + + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_2_5GB) + printf(" (E) - 2.5 GBPS\n"); + + if (bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_100MB) + printf(" (F) - 100 MBPS\n"); + + return CMD_RET_SUCCESS; +} + +int bnxt_hwrm_set_nvmem(struct bnxt *bp, + u16 data_len, + u16 option_num, + u16 dimensions, + u16 index_0, + u8 flag) +{ + u16 cmd_len = (u16)sizeof(struct hwrm_nvm_set_variable_input); + struct hwrm_nvm_set_variable_input *req; + + req = (struct hwrm_nvm_set_variable_input *)bp->hwrm_addr_req; + hwrm_init(bp, (void *)req, (u16)HWRM_NVM_SET_VARIABLE, cmd_len); + req->src_data_addr = bp->data_addr_mapping; + req->data_len = data_len; + req->option_num = option_num; + req->dimensions = dimensions; + req->index_0 = index_0; + req->flags = flag; + + return wait_resp(bp, + HWRM_CMD_FLASH_MULTIPLAYER(bp->hwrm_cmd_timeout), + cmd_len, + __func__); +} + +static int bnxt_set_link_speed(struct bnxt *bp) +{ + u32 *dma_buf32 = (u32 *)bp->hwrm_addr_data; + + memset(bp->hwrm_addr_data, 0, 8); + dma_buf32[0] = bp->link_set; + dma_buf32[1] = 0; + if (bnxt_hwrm_set_nvmem(bp, + 4, + (u16)LINK_SPEED_DRV_NUM, + 1, + (u16)bp->port_idx, + 0) != STATUS_SUCCESS) + return CMD_RET_FAILURE; + + memset(bp->hwrm_addr_data, 0, 8); + dma_buf32[0] = bp->link_set; + dma_buf32[1] = 0; + if (bnxt_hwrm_set_nvmem(bp, + 4, + (u16)LINK_SPEED_FW_NUM, + 1, + (u16)bp->port_idx, + 0) != STATUS_SUCCESS) + return CMD_RET_FAILURE; + + bnxt_hwrm_nvm_flush(bp); + + return CMD_RET_SUCCESS; +} + +static int bnxt_set_mac(struct bnxt *bp) +{ + u32 *dma_buf32 = (u32 *)bp->hwrm_addr_data; + u8 *dma_buf = (u8 *)bp->hwrm_addr_data; + + memset(bp->hwrm_addr_data, 0, 8); + memcpy(&dma_buf[2], &bp->mac_set[0], ETH_ALEN); + dma_buf32[0] = cpu_to_be32(dma_buf32[0]); + dma_buf32[1] = cpu_to_be32(dma_buf32[1]); + if (bnxt_hwrm_set_nvmem(bp, + 64, + (u16)FUNC_MAC_ADDR_NUM, + 1, + (u16)bp->ordinal_value, + 0) != STATUS_SUCCESS) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_bnxt_set_link(struct bnxt *bp, char *link_str) +{ + bp->link_set = simple_strtoul(link_str, NULL, 16); + + switch (bp->link_set) { + case LINK_SPEED_DRV_AUTONEG: + printf("- AutoNeg Not Supported\n"); + return 0; + case LINK_SPEED_DRV_1G: + if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_1GB)) { + printf("- 1 GBPS: Link Speed is not supported\n"); + return 0; + } + + break; + case LINK_SPEED_DRV_10G: + if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_10GB)) { + printf("- 10 GBPS: Link Speed is not supported\n"); + return 0; + } + + break; + case LINK_SPEED_DRV_25G: + if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_25GB)) { + printf("- 25 GBPS: Link Speed is not supported\n"); + return 0; + } + + break; + case LINK_SPEED_DRV_40G: + printf("- 40 GBPS Not Supported\n"); + return 0; + case LINK_SPEED_DRV_50G: + if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_50GB)) { + printf("- 50 GBPS: Link Speed is not supported\n"); + return 0; + } + + break; + case LINK_SPEED_DRV_100G: + if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_100GB)) { + printf("- 100 GBPS: Link Speed is not supported\n"); + return 0; + } + + break; + case LINK_SPEED_DRV_200G: + if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_200GB)) { + printf("- 200 GBPS: Link Speed is not supported\n"); + return 0; + } + + break; + case LINK_SPEED_DRV_2_5G: + if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_2_5GB)) { + printf("- 2.5 GBPS: Link Speed is not supported\n"); + return 0; + } + + break; + case LINK_SPEED_DRV_100M: + if (!(bp->support_speeds & PORT_QCFG_SUPPORT_SPEEDS_100MB)) { + printf("- 100 MBPS: Link Speed is not supported\n"); + return 0; + } + + break; + default: + printf("- Invalid Link Speed specified\n"); + return CMD_RET_USAGE; + } + + prn_link_speed(bp->link_set, 1); + + return bnxt_set_link_speed(bp); +} + +static int do_bnxt_set_mac(struct bnxt *bp, char *mac_str) +{ + struct eth_pdata *plat = dev_get_platdata(bp->pdev); + u8 addr[ETH_ALEN]; + int ret = CMD_RET_USAGE; + + if (eth_validate_ethaddr_str(mac_str)) { + printf("Invalid MAC Address %s\n", mac_str); + return 0; + } + + eth_parse_enetaddr(mac_str, &addr[0]); + + if (!is_valid_ethaddr(&addr[0])) { + printf("- Warning: Invalid MAC address to set\n"); + return 0; + } + + memcpy(bp->mac_set, addr, ETH_ALEN); + + print_mac(&bp->mac_set[0], 1); + ret = bnxt_set_mac(bp); + if (ret) + return ret; + + bnxt_hwrm_nvm_flush(bp); + + /* copy ROM MAC to environment. */ + memcpy(plat->enetaddr, bp->mac_set, ETH_ALEN); + env_set_ethaddr(bp->pdev); + + return CMD_RET_SUCCESS; +} + +static int print_drv(u8 flag) +{ + printf("bnxt - Device "); + if (flag) + printf("already"); + else + printf("not"); + + printf(" initialized\n"); + + return CMD_RET_SUCCESS; +} + +static int bnxt_parse_input(int argc, char *const argv[]) +{ + if (!strcmp(argv[2], "probe")) { + return CMD_PROBE; + } else if (!strcmp(argv[2], "remove")) { + return CMD_REMOVE; + } else if (!strcmp(argv[2], "get")) { + if (!strncmp(argv[3], "supported_speed", 16)) + return CMD_GET_SUPPORTED_SPEED; + else if (!strncmp(argv[3], "link_speed", 11)) + return CMD_GET_LINK_SPEED; + else if (!strncmp(argv[3], "mac", 4)) + return CMD_GET_MAC; + } + + return CMD_UNKNOWN; +} + +static int do_bnxt(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + struct bnxt *bp; + char name[30]; + int ret = CMD_RET_USAGE; + int cardnum; + int op; + + printf("\n"); + if (argc < 2) + return ret; + + cardnum = simple_strtoul(argv[1], NULL, 10); + sprintf(name, "bnxt_eth%u", cardnum); + ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); + if (ret) + return CMD_RET_USAGE; + + bp = dev_get_priv(dev); + op = bnxt_parse_input(argc, argv); + ret = CMD_RET_USAGE; + switch (op) { + case CMD_PROBE: + if (!bp->drv_load) + ret = bnxt_drv_probe(dev); + else + ret = print_drv(1); + break; + case CMD_REMOVE: + ret = bnxt_drv_remove(dev); + break; + case CMD_GET_SUPPORTED_SPEED: + ret = bnxt_supported_speed(bp); + break; + case CMD_GET_MAC: + ret = bnxt_get_mac(bp); + break; + case CMD_GET_LINK_SPEED: + ret = bnxt_get_link_speed(bp); + break; + case CMD_SET_MAC: + ret = do_bnxt_set_mac(bp, argv[4]); + break; + case CMD_SET_LINK_SPEED: + ret = do_bnxt_set_link(bp, argv[4]); + break; + default: + if (op && !bp->drv_load) + ret = print_drv(0); + } + + printf("\n"); + + return ret; +} + +U_BOOT_CMD + (bnxt, 5, 1, do_bnxt, + "Broadcom NetXtreme-C/E Management", + /* */"<bnxt_eth#> probe\n" + " - Load Driver Instance.\n" + "bnxt <bnxt_eth#> remove\n" + " - Unload Driver Instance.\n" + "bnxt <bnxt_eth#> get supported_speed\n" + " - Get Supported Link Speeds.\n" + "bnxt <bnxt_eth#> get link_speed\n" + " - Get Current Link Speed.\n" + "bnxt <bnxt_eth#> get mac\n" + " - Get MAC Address.\n" +); diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h new file mode 100644 index 0000000000..f3e0b866db --- /dev/null +++ b/drivers/net/bnxt/bnxt.h @@ -0,0 +1,403 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom. + */ + +#ifndef _BNXT_H_ +#define _BNXT_H_ + +#include "bnxt_ver.h" +#include "bnxt_hsi.h" + +union dma_addr64_t { + dma_addr_t addr; + u64 as_u64; +}; + +/* Broadcom ethernet driver defines. */ +#define FLAG_SET(f, b) ((f) |= (b)) +#define FLAG_TEST(f, b) ((f) & (b)) +#define FLAG_RESET(f, b) ((f) &= ~(b)) +#define BNXT_FLAG_HWRM_SHORT_CMD_SUPP BIT(0) +#define BNXT_FLAG_HWRM_SHORT_CMD_REQ BIT(1) +#define BNXT_FLAG_RESOURCE_QCAPS_SUPPORT BIT(2) +#define BNXT_FLAG_MULTI_HOST BIT(3) +#define BNXT_FLAG_NPAR_MODE BIT(4) +/******************************************************************************* + * Status codes. + ******************************************************************************/ +#define STATUS_SUCCESS 0 +#define STATUS_FAILURE 1 +#define STATUS_LINK_ACTIVE 4 +#define STATUS_LINK_DOWN 5 +#define STATUS_TIMEOUT 0xffff +/******************************************************************************* + * Receive filter masks. + ******************************************************************************/ +#define RX_MASK_ACCEPT_NONE 0x0000 +#define RX_MASK_ACCEPT_MULTICAST 0x0002 +#define RX_MASK_ACCEPT_ALL_MULTICAST 0x0004 +#define RX_MASK_ACCEPT_BROADCAST 0x0008 +#define RX_MASK_PROMISCUOUS_MODE 0x10000 +/******************************************************************************* + * media speed. + ******************************************************************************/ +#define MEDIUM_SPEED_AUTONEG 0x0000L +#define MEDIUM_SPEED_1000MBPS 0x0300L +#define MEDIUM_SPEED_2500MBPS 0x0400L +#define MEDIUM_SPEED_10GBPS 0x0600L +#define MEDIUM_SPEED_25GBPS 0x0800L +#define MEDIUM_SPEED_40GBPS 0x0900L +#define MEDIUM_SPEED_50GBPS 0x0a00L +#define MEDIUM_SPEED_100GBPS 0x0b00L +#define MEDIUM_SPEED_200GBPS 0x0c00L +#define MEDIUM_SPEED_MASK 0xff00L +#define GET_MEDIUM_SPEED(m) ((m) & MEDIUM_SPEED_MASK) +#define SET_MEDIUM_SPEED(bp, s) (((bp)->medium & ~MEDIUM_SPEED_MASK) | (s)) +#define MEDIUM_UNKNOWN_DUPLEX 0x00000L +#define MEDIUM_FULL_DUPLEX 0x00000L +#define MEDIUM_HALF_DUPLEX 0x10000L +#define GET_MEDIUM_DUPLEX(m) ((m) & MEDIUM_HALF_DUPLEX) +#define SET_MEDIUM_DUPLEX(bp, d) (((bp)->medium & ~MEDIUM_HALF_DUPLEX) | (d)) +#define MEDIUM_SELECTIVE_AUTONEG 0x01000000L +#define GET_MEDIUM_AUTONEG_MODE(m) ((m) & 0xff000000L) +#define PCICFG_ME_REGISTER 0x98 +#define GRC_COM_CHAN_BASE 0 +#define GRC_COM_CHAN_TRIG 0x100 +#define HWRM_CMD_DEFAULT_TIMEOUT 500 /* in Miliseconds */ +#define HWRM_CMD_POLL_WAIT_TIME 100 /* In MicroeSconds */ +#define HWRM_CMD_DEFAULT_MULTIPLAYER(a) ((a) * 10) +#define HWRM_CMD_FLASH_MULTIPLAYER(a) ((a) * 100) +#define HWRM_CMD_FLASH_ERASE_MULTIPLAYER(a) ((a) * 1000) +#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 +#define DEFAULT_NUMBER_OF_CMPL_RINGS 0x01 +#define DEFAULT_NUMBER_OF_TX_RINGS 0x01 +#define DEFAULT_NUMBER_OF_RX_RINGS 0x01 +#define DEFAULT_NUMBER_OF_RING_GRPS 0x01 +#define DEFAULT_NUMBER_OF_STAT_CTXS 0x01 +#define NUM_RX_BUFFERS 8 +#define MAX_RX_DESC_CNT 16 +#define MAX_TX_DESC_CNT 16 +#define MAX_CQ_DESC_CNT 64 +#define TX_RING_DMA_BUFFER_SIZE (MAX_TX_DESC_CNT * sizeof(struct tx_bd_short)) +#define RX_RING_DMA_BUFFER_SIZE \ + (MAX_RX_DESC_CNT * sizeof(struct rx_prod_pkt_bd)) +#define CQ_RING_DMA_BUFFER_SIZE (MAX_CQ_DESC_CNT * sizeof(struct cmpl_base)) +#define BNXT_DMA_ALIGNMENT 256 //64 +#define REQ_BUFFER_SIZE 1024 +#define RESP_BUFFER_SIZE 1024 +#define DMA_BUFFER_SIZE 1024 +#define LM_PAGE_BITS 8 +#define BNXT_RX_STD_DMA_SZ 1536 +#define NEXT_IDX(N, S) (((N) + 1) & ((S) - 1)) +#define BD_NOW(bd, entry, len) (&((u8 *)(bd))[(entry) * (len)]) +#define BNXT_CQ_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL +#define BNXT_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL +/* Set default link timeout period to 500 millseconds */ +#define LINK_DEFAULT_TIMEOUT 500 +#define RX_MASK \ + (RX_MASK_ACCEPT_BROADCAST | \ + RX_MASK_ACCEPT_ALL_MULTICAST | \ + RX_MASK_ACCEPT_MULTICAST) +#define TX_RING_QID ((u16)bp->port_idx * 10) +#define RX_RING_QID 0 +#define LM_PAGE_SIZE LM_PAGE_BITS +#define virt_to_bus(a) ((dma_addr_t)(a)) +#define REQ_BUF_SIZE_ALIGNED ALIGN(REQ_BUFFER_SIZE, BNXT_DMA_ALIGNMENT) +#define RESP_BUF_SIZE_ALIGNED ALIGN(RESP_BUFFER_SIZE, BNXT_DMA_ALIGNMENT) +#define DMA_BUF_SIZE_ALIGNED ALIGN(DMA_BUFFER_SIZE, BNXT_DMA_ALIGNMENT) +#define RX_STD_DMA_ALIGNED ALIGN(BNXT_RX_STD_DMA_SZ, BNXT_DMA_ALIGNMENT) +#define PCI_COMMAND_INTX_DISABLE 0x0400 /* Interrupt disable */ +#define TX_AVAIL(r) ((r) - 1) +#define NO_MORE_CQ_BD_TO_SERVICE 1 +#define SERVICE_NEXT_CQ_BD 0 +#define PHY_STATUS 0x0001 +#define PHY_SPEED 0x0002 +#define DETECT_MEDIA 0x0004 +#define SUPPORT_SPEEDS 0x0008 +#define str_1 "1" +#define str_2 "2" +#define str_2_5 "2.5" +#define str_10 "10" +#define str_20 "20" +#define str_25 "25" +#define str_40 "40" +#define str_50 "50" +#define str_100 "100" +#define str_gbps "Gbps" +#define str_mbps "Mbps" +#define str_unknown "Unknown" +/* Broadcom ethernet driver nvm defines. */ +/* nvm cfg 1 - MAC settings */ +#define FUNC_MAC_ADDR_NUM 1 +/* nvm cfg 203 - u32 link_settings */ +#define LINK_SPEED_DRV_NUM 203 +#define LINK_SPEED_DRV_MASK 0x0000000F +#define LINK_SPEED_DRV_SHIFT 0 +#define LINK_SPEED_DRV_AUTONEG 0x0 +#define LINK_SPEED_DRV_1G 0x1 +#define LINK_SPEED_DRV_10G 0x2 +#define LINK_SPEED_DRV_25G 0x3 +#define LINK_SPEED_DRV_40G 0x4 +#define LINK_SPEED_DRV_50G 0x5 +#define LINK_SPEED_DRV_100G 0x6 +#define LINK_SPEED_DRV_200G 0x7 +#define LINK_SPEED_DRV_2_5G 0xE +#define LINK_SPEED_DRV_100M 0xF +/* nvm cfg 201 - u32 speed_cap_mask */ +#define SPEED_CAPABILITY_DRV_1G 0x1 +#define SPEED_CAPABILITY_DRV_10G 0x2 +#define SPEED_CAPABILITY_DRV_25G 0x4 +#define SPEED_CAPABILITY_DRV_40G 0x8 +#define SPEED_CAPABILITY_DRV_50G 0x10 +#define SPEED_CAPABILITY_DRV_100G 0x20 +#define SPEED_CAPABILITY_DRV_100M 0x8000 +/* nvm cfg 202 */ +/* nvm cfg 205 */ +#define LINK_SPEED_FW_NUM 205 +/* nvm cfg 210 */ +/* nvm cfg 211 */ +/* nvm cfg 213 */ +#define SPEED_DRV_MASK LINK_SPEED_DRV_MASK +/****************************************************************************** + * Doorbell info. + *****************************************************************************/ +#define RX_DOORBELL_KEY_RX (0x1UL << 28) +#define TX_DOORBELL_KEY_TX (0x0UL << 28) + +#define CMPL_DOORBELL_IDX_VALID 0x4000000UL +#define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28) + +/****************************************************************************** + * Transmit info. + *****************************************************************************/ +struct tx_bd_short { + u16 flags_type; +#define TX_BD_SHORT_TYPE_TX_BD_SHORT 0x0UL +#define TX_BD_SHORT_FLAGS_PACKET_END 0x40UL +#define TX_BD_SHORT_FLAGS_NO_CMPL 0x80UL +#define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8 +#define TX_BD_SHORT_FLAGS_LHINT_LT512 (0x0UL << 13) +#define TX_BD_SHORT_FLAGS_LHINT_LT1K (0x1UL << 13) +#define TX_BD_SHORT_FLAGS_LHINT_LT2K (0x2UL << 13) +#define TX_BD_SHORT_FLAGS_LHINT_GTE2K (0x3UL << 13) +#define TX_BD_SHORT_FLAGS_COAL_NOW 0x8000UL + u16 len; + u32 opaque; + union dma_addr64_t dma; +}; + +struct lm_tx_info_t { + void *bd_virt; + u16 prod_id; /* Tx producer index. */ + u16 cons_id; + u16 ring_cnt; + u32 cnt; /* Tx statistics. */ + u32 cnt_req; +}; + +struct cmpl_base { + u16 type; +#define CMPL_BASE_TYPE_MASK 0x3fUL +#define CMPL_BASE_TYPE_TX_L2 0x0UL +#define CMPL_BASE_TYPE_RX_L2 0x11UL +#define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL +#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL + u16 info1; + u32 info2; + u32 info3_v; +#define CMPL_BASE_V 0x1UL + u32 info4; +}; + +struct lm_cmp_info_t { + void *bd_virt; + u16 cons_idx; + u16 ring_cnt; + u8 completion_bit; + u8 res[3]; +}; + +struct rx_pkt_cmpl { + u16 flags_type; + u16 len; + u32 opaque; + u8 agg_bufs_v1; + u8 rss_hash_type; + u8 payload_offset; + u8 unused1; + u32 rss_hash; +}; + +struct rx_pkt_cmpl_hi { + u32 flags2; + u32 metadata; + u16 errors_v2; +#define RX_PKT_CMPL_V2 0x1UL +#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + u16 cfa_code; + u32 reorder; +}; + +struct rx_prod_pkt_bd { + u16 flags_type; +#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT 0x4UL + u16 len; + u32 opaque; + union dma_addr64_t dma; +}; + +struct lm_rx_info_t { + void *bd_virt; + void *iob[NUM_RX_BUFFERS]; + void *iob_rx; + u16 iob_len; + u16 iob_recv; + u16 iob_cnt; + u16 buf_cnt; /* Total Rx buffer descriptors. */ + u16 ring_cnt; + u16 cons_idx; /* Last processed consumer index. */ + u32 rx_cnt; + u32 rx_buf_cnt; + u32 err; + u32 crc; + u32 dropped; +}; + +#define VALID_DRIVER_REG 0x0001 +#define VALID_STAT_CTX 0x0002 +#define VALID_RING_CQ 0x0004 +#define VALID_RING_TX 0x0008 +#define VALID_RING_RX 0x0010 +#define VALID_RING_GRP 0x0020 +#define VALID_VNIC_ID 0x0040 +#define VALID_RX_IOB 0x0080 +#define VALID_L2_FILTER 0x0100 + +enum RX_FLAGS { + PKT_DONE = 0, + PKT_RECEIVED = 1, + PKT_DROPPED = 2, +}; + +struct bnxt { + struct udevice *pdev; + const char *name; + unsigned int cardnum; + void *hwrm_addr_req; + void *hwrm_addr_resp; + void *hwrm_addr_data; + dma_addr_t data_addr_mapping; + dma_addr_t req_addr_mapping; + dma_addr_t resp_addr_mapping; + struct lm_tx_info_t tx; /* Tx info. */ + struct lm_rx_info_t rx; /* Rx info. */ + struct lm_cmp_info_t cq; /* completion info. */ + u16 last_resp_code; + u16 seq_id; + u32 flag_hwrm; + u32 flags; + u16 drv_load; + u16 vendor_id; + u16 device_id; + u16 subsystem_vendor; + u16 subsystem_device; + u16 cmd_reg; + u8 pf_num; /* absolute PF number */ + u8 irq; + void __iomem *bar0; + void __iomem *bar1; + void __iomem *bar2; + u16 chip_num; + /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ + u32 chip_id; + u32 hwrm_cmd_timeout; + u16 hwrm_spec_code; + u16 hwrm_max_req_len; + u16 hwrm_max_ext_req_len; + u8 fw_maj; + u8 fw_min; + u8 fw_bld; + u8 fw_rsvd; + u8 mac_addr[ETH_ALEN]; /* HW MAC address */ + u8 mac_set[ETH_ALEN]; /* NVM Configured MAC */ + u16 fid; + u8 port_idx; + u8 ordinal_value; + u16 mtu; + u16 ring_grp_id; + u16 cq_ring_id; + u16 tx_ring_id; + u16 rx_ring_id; + u16 current_link_speed; + u16 link_status; + u16 wait_link_timeout; + u64 l2_filter_id; + u16 vnic_id; + u16 stat_ctx_id; + u32 medium; + u16 support_speeds; + u32 link_set; + u8 media_detect; + u8 media_change; + u16 max_vfs; + u16 vf_res_strategy; + u16 min_vnics; + u16 max_vnics; + u16 max_msix; + u16 min_hw_ring_grps; + u16 max_hw_ring_grps; + u16 min_tx_rings; + u16 max_tx_rings; + u16 min_rx_rings; + u16 max_rx_rings; + u16 min_cp_rings; + u16 max_cp_rings; + u16 min_rsscos_ctxs; + u16 max_rsscos_ctxs; + u16 min_l2_ctxs; + u16 max_l2_ctxs; + u16 min_stat_ctxs; + u16 max_stat_ctxs; + u16 num_cmpl_rings; + u16 num_tx_rings; + u16 num_rx_rings; + u16 num_stat_ctxs; + u16 num_hw_ring_grps; +}; + +/* defines required to resolve checkpatch errors / warnings */ +#define test_if if +#define write32 writel +#define pci_read_byte dm_pci_read_config8 +#define pci_read_word16 dm_pci_read_config16 +#define pci_write_word dm_pci_write_config16 +#define pci_map_bar dm_pci_map_bar +#define SHORT_CMD_SUPPORTED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED +#define SHORT_CMD_REQUIRED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED +#define CQ_DOORBELL_KEY_IDX(a) \ + (CMPL_DOORBELL_KEY_CMPL | \ + CMPL_DOORBELL_IDX_VALID | \ + (u32)(a)) +#define TX_BD_FLAGS \ + (TX_BD_SHORT_TYPE_TX_BD_SHORT | \ + TX_BD_SHORT_FLAGS_NO_CMPL | \ + TX_BD_SHORT_FLAGS_COAL_NOW | \ + TX_BD_SHORT_FLAGS_PACKET_END | \ + (1 << TX_BD_SHORT_FLAGS_BD_CNT_SFT)) +#define MEM_HWRM_RESP memalign(BNXT_DMA_ALIGNMENT, RESP_BUF_SIZE_ALIGNED) +#define PORT_PHY_FLAGS (BNXT_FLAG_NPAR_MODE | BNXT_FLAG_MULTI_HOST) +#define RING_FREE(bp, rid, flag) bnxt_hwrm_ring_free(bp, rid, flag) +#define QCFG_PHY_ALL (SUPPORT_SPEEDS | DETECT_MEDIA | PHY_SPEED | PHY_STATUS) +enum BNXT_CMD_FLAG { + CMD_UNKNOWN = 0, + CMD_PROBE, + CMD_REMOVE, + CMD_GET_SUPPORTED_SPEED, + CMD_GET_LINK_SPEED, + CMD_GET_MAC, + CMD_SET_MAC, + CMD_SET_LINK_SPEED, +}; + +#endif /* _BNXT_H_ */ diff --git a/drivers/net/bnxt/bnxt_dbg.h b/drivers/net/bnxt/bnxt_dbg.h new file mode 100644 index 0000000000..13d812664a --- /dev/null +++ b/drivers/net/bnxt/bnxt_dbg.h @@ -0,0 +1,538 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom. + */ + +#ifndef _BXNT_DBG_H_ +#define _BXNT_DBG_H_ + +/* Adjust commented out lines below to enable debug. */ +/* #define DEBUG_PCI */ +/* #define DEBUG_MEMORY */ +/* #define DEBUG_LINK */ +/* #define DEBUG_CHIP */ +/* #define DEBUG_FAIL */ +/* #define DEBUG_HWRM_CMDS */ +/* #define DEBUG_HWRM_DUMP */ +/* #define DEBUG_CQ */ +/* #define DEBUG_CQ_DUMP */ +/* #define DEBUG_TX */ +/* #define DEBUG_TX_DUMP */ +/* #define DEBUG_RX */ +/* #define DEBUG_RX_DUMP */ + +#if \ + defined(DEBUG_PCI) || \ + defined(DEBUG_MEMORY) || \ + defined(DEBUG_LINK) || \ + defined(DEBUG_CHIP) || \ + defined(DEBUG_FAIL) || \ + defined(DEBUG_HWRM_CMDS) || \ + defined(DEBUG_HWRM_DUMP) || \ + defined(DEBUG_CQ) || \ + defined(DEBUG_CQ_DUMP) || \ + defined(DEBUG_TX) || \ + defined(DEBUG_TX_DUMP) || \ + defined(DEBUG_RX) || \ + defined(DEBUG_RX_DUMP) +#define DEBUG_DEFAULT +#endif + +#if defined(DEBUG_DEFAULT) +#define dbg_prn printf +#define MAX_CHAR_SIZE(a) (u32)((1 << (a)) - 1) +#define DISP_U8 0x00 +#define DISP_U16 0x01 +#define DISP_U32 0x02 +#define DISP_U64 0x03 + +void dumpmemory1(u8 *buffer, u32 length, u8 flag) +{ + u32 jj = 0; + u8 i, c; + + printf("\n %p:", buffer); + for (jj = 0; jj < 16; jj++) { + if (!(jj & MAX_CHAR_SIZE(flag))) + printf(" "); + if (jj < length) + printf("%02x", buffer[jj]); + else + printf(" "); + if ((jj & 0xF) == 0xF) { + printf(" "); + for (i = 0; i < 16; i++) { + if (i < length) { + c = buffer[jj + i - 15]; + if (c >= 0x20 && c < 0x7F) + ; + else + c = '.'; + printf("%c", c); + } + } + } + } +} + +void dump_mem(u8 *buffer, u32 length, u8 flag) +{ + u32 length16, remlen, jj; + + length16 = length & 0xFFFFFFF0; + remlen = length & 0xF; + for (jj = 0; jj < length16; jj += 16) + dumpmemory1((u8 *)&buffer[jj], 16, flag); + if (remlen) + dumpmemory1((u8 *)&buffer[length16], remlen, flag); + if (length16 || remlen) + printf("\n"); +} +#endif + +#if defined(DEBUG_PCI) +void dbg_pci(struct bnxt *bp, const char *func, u16 cmd_reg) +{ + printf("- %s()\n", func); + printf(" Vendor id : %04X\n", bp->vendor_id); + printf(" Device id : %04X\n", bp->device_id); + printf(" Irq : %d\n", bp->irq); + printf(" PCI Command Reg : %04X %04X\n", bp->cmd_reg, cmd_reg); + printf(" Sub Vendor id : %04X\n", bp->subsystem_vendor); + printf(" Sub Device id : %04X\n", bp->subsystem_device); + printf(" PF Number : %X\n", bp->pf_num); + printf(" BAR (0) : %p\n", bp->bar0); + printf(" BAR (1) : %p\n", bp->bar1); + printf(" BAR (2) : %p\n", bp->bar2); +} +#else +#define dbg_pci(bp, func, creg) +#endif + +#if defined(DEBUG_MEMORY) +void dbg_mem(struct bnxt *bp, const char *func) +{ + printf("- %s()\n", func); + printf(" bp Addr : %p", bp); + printf(" Len %4d", (u16)sizeof(struct bnxt)); + printf(" phy %llx\n", virt_to_bus(bp)); + printf(" bp->hwrm_req_addr : %p", bp->hwrm_addr_req); + printf(" Len %4d", (u16)REQ_BUFFER_SIZE); + printf(" phy %llx\n", bp->req_addr_mapping); + printf(" bp->hwrm_resp_addr : %p", bp->hwrm_addr_resp); + printf(" Len %4d", (u16)RESP_BUFFER_SIZE); + printf(" phy %llx\n", bp->resp_addr_mapping); + printf(" bp->tx.bd_virt : %p", bp->tx.bd_virt); + printf(" Len %4d", (u16)TX_RING_DMA_BUFFER_SIZE); + printf(" phy %llx\n", virt_to_bus(bp->tx.bd_virt)); + printf(" bp->rx.bd_virt : %p", bp->rx.bd_virt); + printf(" Len %4d", (u16)RX_RING_DMA_BUFFER_SIZE); + printf(" phy %llx\n", virt_to_bus(bp->rx.bd_virt)); + printf(" bp->cq.bd_virt : %p", bp->cq.bd_virt); + printf(" Len %4d", (u16)CQ_RING_DMA_BUFFER_SIZE); + printf(" phy %llx\n", virt_to_bus(bp->cq.bd_virt)); +} +#else +#define dbg_mem(bp, func) +#endif + +#if defined(DEBUG_CHIP) +void print_fw_ver(struct hwrm_ver_get_output *resp, u32 tmo) +{ + if (resp->hwrm_intf_maj_8b < 1) { + dbg_prn(" HWRM interface %d.%d.%d is older than 1.0.0.\n", + resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, + resp->hwrm_intf_upd_8b); + dbg_prn(" Update FW with HWRM interface 1.0.0 or newer.\n"); + } + dbg_prn(" FW Version : %d.%d.%d.%d\n", + resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, + resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); + printf(" cmd timeout : %d\n", tmo); +} + +void dbg_func_resource_qcaps(struct bnxt *bp) +{ + /* Ring Groups */ + printf(" min_hw_ring_grps : %d\n", bp->min_hw_ring_grps); + printf(" max_hw_ring_grps : %d\n", bp->max_hw_ring_grps); + /* TX Rings */ + printf(" min_tx_rings : %d\n", bp->min_tx_rings); + printf(" max_tx_rings : %d\n", bp->max_tx_rings); + /* RX Rings */ + printf(" min_rx_rings : %d\n", bp->min_rx_rings); + printf(" max_rx_rings : %d\n", bp->max_rx_rings); + /* Completion Rings */ + printf(" min_cq_rings : %d\n", bp->min_cp_rings); + printf(" max_cq_rings : %d\n", bp->max_cp_rings); + /* Statistic Contexts */ + printf(" min_stat_ctxs : %d\n", bp->min_stat_ctxs); + printf(" max_stat_ctxs : %d\n", bp->max_stat_ctxs); +} + +void print_func_qcaps(struct bnxt *bp) +{ + printf(" Port Number : %d\n", bp->port_idx); + printf(" fid : 0x%04x\n", bp->fid); + dbg_prn(" PF MAC : %02x:%02x:%02x:%02x:%02x:%02x\n", + bp->mac_addr[0], + bp->mac_addr[1], + bp->mac_addr[2], + bp->mac_addr[3], + bp->mac_addr[4], + bp->mac_addr[5]); +} + +void print_func_qcfg(struct bnxt *bp) +{ + printf(" ordinal_value : %d\n", bp->ordinal_value); + printf(" stat_ctx_id : %x\n", bp->stat_ctx_id); + dbg_prn(" FW MAC : %02x:%02x:%02x:%02x:%02x:%02x\n", + bp->mac_addr[0], + bp->mac_addr[1], + bp->mac_addr[2], + bp->mac_addr[3], + bp->mac_addr[4], + bp->mac_addr[5]); +} + +void dbg_set_speed(u32 speed) +{ + u32 speed1 = ((speed & LINK_SPEED_DRV_MASK) >> LINK_SPEED_DRV_SHIFT); + + printf(" Set Link Speed : "); + switch (speed & LINK_SPEED_DRV_MASK) { + case LINK_SPEED_DRV_1G: + printf("1 GBPS"); + break; + case LINK_SPEED_DRV_10G: + printf("10 GBPS"); + break; + case LINK_SPEED_DRV_25G: + printf("25 GBPS"); + break; + case LINK_SPEED_DRV_40G: + printf("40 GBPS"); + break; + case LINK_SPEED_DRV_50G: + printf("50 GBPS"); + break; + case LINK_SPEED_DRV_100G: + printf("100 GBPS"); + break; + case LINK_SPEED_DRV_AUTONEG: + printf("AUTONEG"); + break; + default: + printf("%x", speed1); + break; + } + printf("\n"); +} + +void dbg_chip_info(struct bnxt *bp) +{ + printf(" Stat Ctx ID : %d\n", bp->stat_ctx_id); + printf(" Grp ID : %d\n", bp->ring_grp_id); + printf(" CQ Ring Id : %d\n", bp->cq_ring_id); + printf(" Tx Ring Id : %d\n", bp->tx_ring_id); + printf(" Rx ring Id : %d\n", bp->rx_ring_id); +} + +void print_num_rings(struct bnxt *bp) +{ + printf(" num_cmpl_rings : %d\n", bp->num_cmpl_rings); + printf(" num_tx_rings : %d\n", bp->num_tx_rings); + printf(" num_rx_rings : %d\n", bp->num_rx_rings); + printf(" num_ring_grps : %d\n", bp->num_hw_ring_grps); + printf(" num_stat_ctxs : %d\n", bp->num_stat_ctxs); +} + +void dbg_flags(const char *func, u32 flags) +{ + printf("- %s()\n", func); + printf(" bp->flags : 0x%04x\n", flags); +} +#else +#define print_fw_ver(resp, tmo) +#define dbg_func_resource_qcaps(bp) +#define print_func_qcaps(bp) +#define print_func_qcfg(bp) +#define dbg_set_speed(speed) +#define dbg_chip_info(bp) +#define print_num_rings(bp) +#define dbg_flags(func, flags) +#endif + +#if defined(DEBUG_HWRM_CMDS) || defined(DEBUG_FAIL) +void dump_hwrm_req(struct bnxt *bp, const char *func, u32 len, u32 tmo) +{ + dbg_prn("- %s(0x%04x) cmd_len %d cmd_tmo %d", + func, (u16)((struct input *)bp->hwrm_addr_req)->req_type, + len, tmo); +#if defined(DEBUG_HWRM_DUMP) + dump_mem((u8 *)bp->hwrm_addr_req, len, DISP_U8); +#else + printf("\n"); +#endif +} + +void debug_resp(struct bnxt *bp, const char *func, u32 resp_len, u16 err) +{ + dbg_prn("- %s(0x%04x) - ", + func, (u16)((struct input *)bp->hwrm_addr_req)->req_type); + if (err == STATUS_SUCCESS) + printf("Done"); + else if (err != STATUS_TIMEOUT) + printf("Fail err 0x%04x", err); + else + printf("timedout"); +#if defined(DEBUG_HWRM_DUMP) + if (err != STATUS_TIMEOUT) + dump_mem((u8 *)bp->hwrm_addr_resp, resp_len, DISP_U8); + else + printf("\n"); +#else + resp_len = resp_len; + printf("\n"); +#endif +} + +void dbg_hw_cmd(struct bnxt *bp, + const char *func, u16 cmd_len, + u16 resp_len, u32 cmd_tmo, u16 err) +{ +#if !defined(DEBUG_HWRM_CMDS) + if (err && err != STATUS_TIMEOUT) +#endif + { + dump_hwrm_req(bp, func, cmd_len, cmd_tmo); + debug_resp(bp, func, resp_len, err); + } +} +#else +#define dbg_hw_cmd(bp, func, cmd_len, resp_len, cmd_tmo, err) +#endif + +#if defined(DEBUG_HWRM_CMDS) +void dbg_short_cmd(u8 *req, const char *func, u32 len) +{ + struct hwrm_short_input *sreq; + + sreq = (struct hwrm_short_input *)req; + dbg_prn("- %s(0x%04x) short_cmd_len %d", + func, + sreq->req_type, + (int)len); +#if defined(DEBUG_HWRM_DUMP) + dump_mem((u8 *)sreq, len, DISP_U8); +#else + printf("\n"); +#endif +} +#else +#define dbg_short_cmd(sreq, func, len) +#endif + +#if defined(DEBUG_RX) +void dump_rx_bd(struct rx_pkt_cmpl *rx_cmp, + struct rx_pkt_cmpl_hi *rx_cmp_hi, + u32 desc_idx) +{ + printf(" RX desc_idx %d\n", desc_idx); + printf("- rx_cmp %llx", virt_to_bus(rx_cmp)); +#if defined(DEBUG_RX_DUMP) + dump_mem((u8 *)rx_cmp, (u32)sizeof(struct rx_pkt_cmpl), DISP_U8); +#else + printf("\n"); +#endif + printf("- rx_cmp_hi %llx", virt_to_bus(rx_cmp_hi)); +#if defined(DEBUG_RX_DUMP) + dump_mem((u8 *)rx_cmp_hi, (u32)sizeof(struct rx_pkt_cmpl_hi), DISP_U8); +#else + printf("\n"); +#endif +} + +void dbg_rxp(u8 *iob, u16 rx_len, u16 flag) +{ + printf("- RX iob %llx Len %d ", virt_to_bus(iob), rx_len); + if (flag == PKT_RECEIVED) + printf(" PKT RECEIVED"); + else if (flag == PKT_DROPPED) + printf(" PKT DROPPED"); +#if defined(DEBUG_RX_DUMP) + dump_mem(iob, (u32)rx_len, DISP_U8); +#else + printf("\n"); +#endif +} + +void dbg_rx_cid(u16 idx, u16 cid) +{ + dbg_prn("- RX old cid %d new cid %d\n", idx, cid); +} + +void dbg_rx_alloc_iob_fail(u16 idx, u16 cid) +{ + dbg_prn(" Rx alloc_iob (%d) failed", idx); + dbg_prn(" for cons_id %d\n", cid); +} + +void dbg_rx_iob(void *iob, u16 idx, u16 cid) +{ + dbg_prn(" Rx alloc_iob (%d) %p bd_virt (%d)\n", + idx, iob, cid); +} + +void dbg_rx_pkt(struct bnxt *bp, const char *func, uchar *pkt, int len) +{ + if (bp->rx.iob_recv == PKT_RECEIVED) { + dbg_prn("- %s: %llx %d\n", func, + virt_to_bus(pkt), len); + } +} +#else +#define dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx) +#define dbg_rxp(iob, rx_len, flag) +#define dbg_rx_cid(idx, cid) +#define dbg_rx_alloc_iob_fail(idx, cid) +#define dbg_rx_iob(iob, idx, cid) +#define dbg_rx_pkt(bp, func, pkt, len) +#endif + +#if defined(DEBUG_CQ) +void dump_CQ(struct cmpl_base *cmp, u16 cons_idx) +{ + printf("- CQ Type "); + + switch (cmp->type & CMPL_BASE_TYPE_MASK) { + case CMPL_BASE_TYPE_STAT_EJECT: + printf("(se)"); + break; + case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: + printf("(ae)"); + break; + case CMPL_BASE_TYPE_TX_L2: + printf("(tx)"); + break; + case CMPL_BASE_TYPE_RX_L2: + printf("(rx)"); + break; + default: + printf("%04x", (u16)(cmp->type & CMPL_BASE_TYPE_MASK)); + break; + } + printf(" cid %d", cons_idx); +#if defined(DEBUG_CQ_DUMP) + dump_mem((u8 *)cmp, (u32)sizeof(struct cmpl_base), DISP_U8); +#else + printf("\n"); +#endif +} +#else +#define dump_CQ(cq, id) +#endif + +#if defined(DEBUG_TX) +void dump_tx_stat(struct bnxt *bp) +{ + printf(" TX stats cnt %d req_cnt %d", bp->tx.cnt, bp->tx.cnt_req); + printf(" prod_id %d cons_id %d\n", bp->tx.prod_id, bp->tx.cons_id); +} + +void dump_tx_pkt(void *packet, dma_addr_t mapping, int len) +{ + printf(" TX Addr %llx Size %d", mapping, len); +#if defined(DEBUG_TX_DUMP) + dump_mem((u8 *)packet, len, DISP_U8); +#else + printf("\n"); +#endif +} + +void dump_tx_bd(struct tx_bd_short *tx_bd, u16 len) +{ + printf(" Tx BD Addr %llx Size %d", virt_to_bus(tx_bd), len); +#if defined(DEBUG_TX_DUMP) + dump_mem((u8 *)tx_bd, (u32)len, DISP_U8); +#else + printf("\n"); +#endif +} + +void dbg_no_tx_bd(void) +{ + printf(" Tx ring full\n"); +} +#else +#define dump_tx_stat(bp) +#define dump_tx_pkt(packet, mapping, len) +#define dump_tx_bd(prod_bd, len) +#define dbg_no_tx_bd() +#endif + +#if defined(DEBUG_MEMORY) +void dbg_mem_free_done(const char *func) +{ + printf("- %s - Done\n", func); +} +#else +#define dbg_mem_free_done(func) +#endif + +#if defined(DEBUG_FAIL) +void dbg_mem_alloc_fail(const char *func) +{ + printf("- %s() Fail\n", func); +} +#else +#define dbg_mem_alloc_fail(func) +#endif + +#if defined(DEBUG_LINK) +static void dump_evt(u8 *cmp, u32 type, u16 cid) +{ + u32 size = sizeof(struct cmpl_base); + u8 c = 'C'; + + switch (type) { + case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: + break; + default: + return; + } + dbg_prn("- %cQ Type (ae) cid %d", c, cid); + dump_mem(cmp, size, DISP_U8); +} + +void dbg_link_status(struct bnxt *bp) +{ + dbg_prn(" Port(%d) : Link", bp->port_idx); + if (bp->link_status == STATUS_LINK_ACTIVE) { + dbg_prn("Up"); + } else { + dbg_prn("Down\n"); + dbg_prn(" media_detect : %x", bp->media_detect); + } + dbg_prn("\n"); +} + +void dbg_link_state(struct bnxt *bp, u32 tmo) +{ + if (bp->link_status == STATUS_LINK_ACTIVE) + printf(" Link wait time : %d ms\n", tmo); +} + +void dbg_phy_speed(struct bnxt *bp, char *name) +{ + printf(" Current Speed : %s\n", name); +} +#else +#define dump_evt(cmp, ty, cid) +#define dbg_link_status(bp) +#define dbg_link_state(bp, tmo) +#define dbg_phy_speed(bp, name) +#endif + +#endif /* _BXNT_DBG_H_ */ diff --git a/drivers/net/bnxt/bnxt_hsi.h b/drivers/net/bnxt/bnxt_hsi.h new file mode 100644 index 0000000000..2d10c3d4d7 --- /dev/null +++ b/drivers/net/bnxt/bnxt_hsi.h @@ -0,0 +1,889 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + /* + * Copyright 2019 Broadcom. + */ + +#ifndef _BNXT_HSI_H_ +#define _BNXT_HSI_H_ + +/* input (size:128b/16B) */ +struct input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; +}; + +/* output (size:64b/8B) */ +struct output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; +}; + +/* hwrm_short_input (size:128b/16B) */ +struct hwrm_short_input { + __le16 req_type; + __le16 signature; +#define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL + __le16 unused_0; + __le16 size; + __le64 req_addr; +}; + +#define HWRM_VER_GET 0x0UL +#define HWRM_FUNC_RESET 0x11UL +#define HWRM_FUNC_QCAPS 0x15UL +#define HWRM_FUNC_QCFG 0x16UL +#define HWRM_FUNC_CFG 0x17UL +#define HWRM_FUNC_DRV_UNRGTR 0x1aUL +#define HWRM_FUNC_DRV_RGTR 0x1dUL +#define HWRM_PORT_PHY_CFG 0x20UL +#define HWRM_PORT_MAC_CFG 0x21UL +#define HWRM_PORT_PHY_QCFG 0x27UL +#define HWRM_VNIC_ALLOC 0x40UL +#define HWRM_VNIC_FREE 0x41UL +#define HWRM_VNIC_CFG 0x42UL +#define HWRM_RING_ALLOC 0x50UL +#define HWRM_RING_FREE 0x51UL +#define HWRM_RING_GRP_ALLOC 0x60UL +#define HWRM_RING_GRP_FREE 0x61UL +#define HWRM_CFA_L2_FILTER_ALLOC 0x90UL +#define HWRM_CFA_L2_FILTER_FREE 0x91UL +#define HWRM_CFA_L2_SET_RX_MASK 0x93UL +#define HWRM_STAT_CTX_ALLOC 0xb0UL +#define HWRM_STAT_CTX_FREE 0xb1UL +#define HWRM_FUNC_RESOURCE_QCAPS 0x190UL +#define HWRM_NVM_FLUSH 0xfff0UL +#define HWRM_NVM_GET_VARIABLE 0xfff1UL +#define HWRM_NVM_SET_VARIABLE 0xfff2UL + +#define HWRM_NA_SIGNATURE ((__le32)(-1)) +#define HWRM_MAX_REQ_LEN 128 +#define HWRM_VERSION_MAJOR 1 +#define HWRM_VERSION_MINOR 10 +#define HWRM_VERSION_UPDATE 0 + +/* hwrm_ver_get_input (size:192b/24B) */ +struct hwrm_ver_get_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + u8 hwrm_intf_maj; + u8 hwrm_intf_min; + u8 hwrm_intf_upd; + u8 unused_0[5]; +}; + +/* hwrm_ver_get_output (size:1408b/176B) */ +struct hwrm_ver_get_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + u8 hwrm_intf_maj_8b; + u8 hwrm_intf_min_8b; + u8 hwrm_intf_upd_8b; + u8 hwrm_intf_rsvd_8b; + u8 hwrm_fw_maj_8b; + u8 hwrm_fw_min_8b; + u8 hwrm_fw_bld_8b; + u8 hwrm_fw_rsvd_8b; + u8 mgmt_fw_maj_8b; + u8 mgmt_fw_min_8b; + u8 mgmt_fw_bld_8b; + u8 mgmt_fw_rsvd_8b; + u8 netctrl_fw_maj_8b; + u8 netctrl_fw_min_8b; + u8 netctrl_fw_bld_8b; + u8 netctrl_fw_rsvd_8b; + __le32 dev_caps_cfg; +#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL +#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL + u8 roce_fw_maj_8b; + u8 roce_fw_min_8b; + u8 roce_fw_bld_8b; + u8 roce_fw_rsvd_8b; + char hwrm_fw_name[16]; + char mgmt_fw_name[16]; + char netctrl_fw_name[16]; + u8 reserved2[16]; + char roce_fw_name[16]; + __le16 chip_num; + u8 chip_rev; + u8 chip_metal; + u8 chip_bond_id; + u8 chip_platform_type; + __le16 max_req_win_len; + __le16 max_resp_len; + __le16 def_req_timeout; + u8 flags; + u8 unused_0[2]; + u8 always_1; + __le16 hwrm_intf_major; + __le16 hwrm_intf_minor; + __le16 hwrm_intf_build; + __le16 hwrm_intf_patch; + __le16 hwrm_fw_major; + __le16 hwrm_fw_minor; + __le16 hwrm_fw_build; + __le16 hwrm_fw_patch; + __le16 mgmt_fw_major; + __le16 mgmt_fw_minor; + __le16 mgmt_fw_build; + __le16 mgmt_fw_patch; + __le16 netctrl_fw_major; + __le16 netctrl_fw_minor; + __le16 netctrl_fw_build; + __le16 netctrl_fw_patch; + __le16 roce_fw_major; + __le16 roce_fw_minor; + __le16 roce_fw_build; + __le16 roce_fw_patch; + __le16 max_ext_req_len; + u8 unused_1[5]; + u8 valid; +}; + +/* hwrm_async_event_cmpl (size:128b/16B) */ +struct hwrm_async_event_cmpl { + __le16 type; + __le16 event_id; +#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL + __le32 event_data2; + u8 opaque_v; + u8 timestamp_lo; + __le16 timestamp_hi; + __le32 event_data1; +}; + +/* hwrm_func_reset_input (size:192b/24B) */ +struct hwrm_func_reset_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 enables; + __le16 vf_id; + u8 func_reset_level; +#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL + u8 unused_0; +}; + +/* hwrm_func_qcaps_input (size:192b/24B) */ +struct hwrm_func_qcaps_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le16 fid; + u8 unused_0[6]; +}; + +/* hwrm_func_qcaps_output (size:640b/80B) */ +struct hwrm_func_qcaps_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + __le16 fid; + __le16 port_id; + __le32 flags; + u8 mac_address[6]; + __le16 max_rsscos_ctx; + __le16 max_cmpl_rings; + __le16 max_tx_rings; + __le16 max_rx_rings; + __le16 max_l2_ctxs; + __le16 max_vnics; + __le16 first_vf_id; + __le16 max_vfs; + __le16 max_stat_ctx; + __le32 max_encap_records; + __le32 max_decap_records; + __le32 max_tx_em_flows; + __le32 max_tx_wm_flows; + __le32 max_rx_em_flows; + __le32 max_rx_wm_flows; + __le32 max_mcast_filters; + __le32 max_flow_id; + __le32 max_hw_ring_grps; + __le16 max_sp_tx_rings; + u8 unused_0; + u8 valid; +}; + +/* hwrm_func_qcfg_input (size:192b/24B) */ +struct hwrm_func_qcfg_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le16 fid; + u8 unused_0[6]; +}; + +/* hwrm_func_qcfg_output (size:704b/88B) */ +struct hwrm_func_qcfg_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + __le16 fid; + __le16 port_id; + __le16 vlan; + __le16 flags; +#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL + u8 mac_address[6]; + __le16 pci_id; + __le16 alloc_rsscos_ctx; + __le16 alloc_cmpl_rings; + __le16 alloc_tx_rings; + __le16 alloc_rx_rings; + __le16 alloc_l2_ctx; + __le16 alloc_vnics; + __le16 mtu; + __le16 mru; + __le16 stat_ctx_id; + u8 port_partition_type; +#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL + u8 port_pf_cnt; + __le16 dflt_vnic_id; + __le16 max_mtu_configured; + __le32 min_bw; + __le32 max_bw; + u8 evb_mode; + u8 options; + __le16 alloc_vfs; + __le32 alloc_mcast_filters; + __le32 alloc_hw_ring_grps; + __le16 alloc_sp_tx_rings; + __le16 alloc_stat_ctx; + __le16 alloc_msix; + __le16 registered_vfs; + u8 unused_1[3]; + u8 always_1; + __le32 reset_addr_poll; + u8 unused_2[3]; + u8 valid; +}; + +/* hwrm_func_cfg_input (size:704b/88B) */ +struct hwrm_func_cfg_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le16 fid; + __le16 num_msix; + __le32 flags; + __le32 enables; +#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL +#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL +#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL +#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL +#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL +#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL + __le16 mtu; + __le16 mru; + __le16 num_rsscos_ctxs; + __le16 num_cmpl_rings; + __le16 num_tx_rings; + __le16 num_rx_rings; + __le16 num_l2_ctxs; + __le16 num_vnics; + __le16 num_stat_ctxs; + __le16 num_hw_ring_grps; + u8 dflt_mac_addr[6]; + __le16 dflt_vlan; + __be32 dflt_ip_addr[4]; + __le32 min_bw; + __le32 max_bw; + __le16 async_event_cr; + u8 vlan_antispoof_mode; + u8 allowed_vlan_pris; + u8 evb_mode; + u8 options; + __le16 num_mcast_filters; +}; + +/* hwrm_func_drv_rgtr_input (size:896b/112B) */ +struct hwrm_func_drv_rgtr_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 flags; + __le32 enables; +#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL +#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL +#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL + __le16 os_type; +#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL + u8 ver_maj_8b; + u8 ver_min_8b; + u8 ver_upd_8b; + u8 unused_0[3]; + __le32 timestamp; + u8 unused_1[4]; + __le32 vf_req_fwd[8]; + __le32 async_event_fwd[8]; + __le16 ver_maj; + __le16 ver_min; + __le16 ver_upd; + __le16 ver_patch; +}; + +/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ +struct hwrm_func_drv_unrgtr_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 flags; +#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL + u8 unused_0[4]; +}; + +/* hwrm_func_resource_qcaps_input (size:192b/24B) */ +struct hwrm_func_resource_qcaps_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le16 fid; + u8 unused_0[6]; +}; + +/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +struct hwrm_func_resource_qcaps_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + __le16 max_vfs; + __le16 max_msix; + __le16 vf_reservation_strategy; + __le16 min_rsscos_ctx; + __le16 max_rsscos_ctx; + __le16 min_cmpl_rings; + __le16 max_cmpl_rings; + __le16 min_tx_rings; + __le16 max_tx_rings; + __le16 min_rx_rings; + __le16 max_rx_rings; + __le16 min_l2_ctxs; + __le16 max_l2_ctxs; + __le16 min_vnics; + __le16 max_vnics; + __le16 min_stat_ctx; + __le16 max_stat_ctx; + __le16 min_hw_ring_grps; + __le16 max_hw_ring_grps; + __le16 max_tx_scheduler_inputs; + __le16 flags; + u8 unused_0[5]; + u8 valid; +}; + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le16 fid; + u8 unused_0[6]; +}; + +/* hwrm_port_phy_cfg_input (size:448b/56B) */ +struct hwrm_port_phy_cfg_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 flags; +#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL +#define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL + __le32 enables; +#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL +#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL +#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL +#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL + __le16 port_id; + __le16 force_link_speed; +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL +#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL + u8 auto_mode; +#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL + u8 auto_duplex; +#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL + u8 auto_pause; +#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL +#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL + u8 unused_0; + __le16 auto_link_speed; + __le16 auto_link_speed_mask; +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL +#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL + u8 wirespeed; + u8 lpbk; + u8 force_pause; + u8 unused_1; + __le32 preemphasis; + __le16 eee_link_speed_mask; + u8 unused_2[2]; + __le32 tx_lpi_timer; + __le32 unused_3; +}; + +/* hwrm_port_phy_qcfg_input (size:192b/24B) */ +struct hwrm_port_phy_qcfg_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le16 port_id; + u8 unused_0[6]; +}; + +/* hwrm_port_phy_qcfg_output (size:768b/96B) */ +struct hwrm_port_phy_qcfg_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + u8 link; +#define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL + u8 unused_0; + __le16 link_speed; +#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL +#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL + u8 duplex_cfg; + u8 pause; + __le16 support_speeds; +#define PORT_QCFG_SUPPORT_SPEEDS_100MBHD 0x1UL +#define PORT_QCFG_SUPPORT_SPEEDS_100MB 0x2UL +#define PORT_QCFG_SUPPORT_SPEEDS_1GBHD 0x4UL +#define PORT_QCFG_SUPPORT_SPEEDS_1GB 0x8UL +#define PORT_QCFG_SUPPORT_SPEEDS_2GB 0x10UL +#define PORT_QCFG_SUPPORT_SPEEDS_2_5GB 0x20UL +#define PORT_QCFG_SUPPORT_SPEEDS_10GB 0x40UL +#define PORT_QCFG_SUPPORT_SPEEDS_20GB 0x80UL +#define PORT_QCFG_SUPPORT_SPEEDS_25GB 0x100UL +#define PORT_QCFG_SUPPORT_SPEEDS_50GB 0x400UL +#define PORT_QCFG_SUPPORT_SPEEDS_100GB 0x800UL +#define PORT_QCFG_SUPPORT_SPEEDS_200GB 0x4000UL + __le16 force_link_speed; + u8 auto_mode; + u8 auto_pause; + __le16 auto_link_speed; + __le16 auto_link_speed_mask; + u8 wirespeed; + u8 lpbk; + u8 force_pause; + u8 module_status; + __le32 preemphasis; + u8 phy_maj; + u8 phy_min; + u8 phy_bld; + u8 phy_type; + u8 media_type; + u8 xcvr_pkg_type; + u8 eee_config_phy_addr; + u8 parallel_detect; + __le16 link_partner_adv_speeds; + u8 link_partner_adv_auto_mode; + u8 link_partner_adv_pause; + __le16 adv_eee_link_speed_mask; + __le16 link_partner_adv_eee_link_speed_mask; + __le32 xcvr_identifier_type_tx_lpi_timer; + __le16 fec_cfg; + u8 duplex_state; + u8 option_flags; + char phy_vendor_name[16]; + char phy_vendor_partnumber[16]; + u8 unused_2[7]; + u8 valid; +}; + +/* hwrm_port_mac_cfg_input (size:320b/40B) */ +struct hwrm_port_mac_cfg_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 flags; + __le32 enables; + __le16 port_id; + u8 ipg; + u8 lpbk; +#define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL + u8 vlan_pri2cos_map_pri; + u8 reserved1; + u8 tunnel_pri2cos_map_pri; + u8 dscp2pri_map_pri; + __le16 rx_ts_capture_ptp_msg_type; + __le16 tx_ts_capture_ptp_msg_type; + u8 cos_field_cfg; + u8 unused_0[3]; +}; + +/* hwrm_vnic_alloc_input (size:192b/24B) */ +struct hwrm_vnic_alloc_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 flags; +#define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL + u8 unused_0[4]; +}; + +/* hwrm_vnic_alloc_output (size:128b/16B) */ +struct hwrm_vnic_alloc_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + __le32 vnic_id; + u8 unused_0[3]; + u8 valid; +}; + +/* hwrm_vnic_free_input (size:192b/24B) */ +struct hwrm_vnic_free_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 vnic_id; + u8 unused_0[4]; +}; + +/* hwrm_vnic_cfg_input (size:320b/40B) */ +struct hwrm_vnic_cfg_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 flags; + __le32 enables; +#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL +#define VNIC_CFG_REQ_ENABLES_MRU 0x10UL + __le16 vnic_id; + __le16 dflt_ring_grp; + __le16 rss_rule; + __le16 cos_rule; + __le16 lb_rule; + __le16 mru; + __le16 default_rx_ring_id; + __le16 default_cmpl_ring_id; +}; + +/* hwrm_ring_alloc_input (size:704b/88B) */ +struct hwrm_ring_alloc_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 enables; +#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL + u8 ring_type; +#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL +#define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL +#define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL + u8 unused_0; + __le16 flags; + __le64 page_tbl_addr; + __le32 fbo; + u8 page_size; + u8 page_tbl_depth; + u8 unused_1[2]; + __le32 length; + __le16 logical_id; + __le16 cmpl_ring_id; + __le16 queue_id; + __le16 rx_buf_size; + __le16 rx_ring_id; + __le16 nq_ring_id; + __le16 ring_arb_cfg; + __le16 unused_3; + __le32 reserved3; + __le32 stat_ctx_id; + __le32 reserved4; + __le32 max_bw; + u8 int_mode; +#define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL + u8 unused_4[3]; + __le64 cq_handle; +}; + +/* hwrm_ring_alloc_output (size:128b/16B) */ +struct hwrm_ring_alloc_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + __le16 ring_id; + __le16 logical_ring_id; + u8 unused_0[3]; + u8 valid; +}; + +/* hwrm_ring_free_input (size:192b/24B) */ +struct hwrm_ring_free_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + u8 ring_type; +#define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL +#define RING_FREE_REQ_RING_TYPE_TX 0x1UL +#define RING_FREE_REQ_RING_TYPE_RX 0x2UL + u8 unused_0; + __le16 ring_id; + u8 unused_1[4]; +}; + +/* hwrm_ring_grp_alloc_input (size:192b/24B) */ +struct hwrm_ring_grp_alloc_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le16 cr; + __le16 rr; + __le16 ar; + __le16 sc; +}; + +/* hwrm_ring_grp_alloc_output (size:128b/16B) */ +struct hwrm_ring_grp_alloc_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + __le32 ring_group_id; + u8 unused_0[3]; + u8 valid; +}; + +/* hwrm_ring_grp_free_input (size:192b/24B) */ +struct hwrm_ring_grp_free_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 ring_group_id; + u8 unused_0[4]; +}; + +/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ +struct hwrm_cfa_l2_filter_alloc_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 flags; +#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL + __le32 enables; +#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL +#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL +#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL + u8 l2_addr[6]; + u8 unused_0[2]; + u8 l2_addr_mask[6]; + __le16 l2_ovlan; + __le16 l2_ovlan_mask; + __le16 l2_ivlan; + __le16 l2_ivlan_mask; + u8 unused_1[2]; + u8 t_l2_addr[6]; + u8 unused_2[2]; + u8 t_l2_addr_mask[6]; + __le16 t_l2_ovlan; + __le16 t_l2_ovlan_mask; + __le16 t_l2_ivlan; + __le16 t_l2_ivlan_mask; + u8 src_type; +#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL + u8 unused_3; + __le32 src_id; + u8 tunnel_type; + u8 unused_4; + __le16 dst_id; + __le16 mirror_vnic_id; + u8 pri_hint; + u8 unused_5; + __le32 unused_6; + __le64 l2_filter_id_hint; +}; + +/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_l2_filter_alloc_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + __le64 l2_filter_id; + __le32 flow_id; + u8 unused_0[3]; + u8 valid; +}; + +/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_l2_filter_free_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le64 l2_filter_id; +}; + +/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ +struct hwrm_cfa_l2_set_rx_mask_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 vnic_id; + __le32 mask; +#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL +#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL +#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL +#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL + __le64 mc_tbl_addr; + __le32 num_mc_entries; + u8 unused_0[4]; + __le64 vlan_tag_tbl_addr; + __le32 num_vlan_tags; + u8 unused_1[4]; +}; + +/* hwrm_stat_ctx_alloc_input (size:256b/32B) */ +struct hwrm_stat_ctx_alloc_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le64 stats_dma_addr; + __le32 update_period_ms; + u8 stat_ctx_flags; + u8 unused_0[3]; +}; + +/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ +struct hwrm_stat_ctx_alloc_output { + __le16 error_code; + __le16 req_type; + __le16 seq_id; + __le16 resp_len; + __le32 stat_ctx_id; + u8 unused_0[3]; + u8 valid; +}; + +/* hwrm_stat_ctx_free_input (size:192b/24B) */ +struct hwrm_stat_ctx_free_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le32 stat_ctx_id; + u8 unused_0[4]; +}; + +/* hwrm_nvm_flush_input (size:128b/16B) */ +struct hwrm_nvm_flush_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; +}; + +/* hwrm_nvm_get_variable_input (size:320b/40B) */ +struct hwrm_nvm_get_variable_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le64 dest_data_addr; + __le16 data_len; + __le16 option_num; + __le16 dimensions; + __le16 index_0; + __le16 index_1; + __le16 index_2; + __le16 index_3; + u8 flags; + u8 unused_0; +}; + +/* hwrm_nvm_set_variable_input (size:320b/40B) */ +struct hwrm_nvm_set_variable_input { + __le16 req_type; + __le16 cmpl_ring; + __le16 seq_id; + __le16 target_id; + __le64 resp_addr; + __le64 src_data_addr; + __le16 data_len; + __le16 option_num; + __le16 dimensions; + __le16 index_0; + __le16 index_1; + __le16 index_2; + __le16 index_3; + u8 flags; + u8 unused_0; +}; + +#endif /* _BNXT_HSI_H_ */ diff --git a/drivers/net/bnxt/bnxt_ver.h b/drivers/net/bnxt/bnxt_ver.h new file mode 100644 index 0000000000..f42fcc54ed --- /dev/null +++ b/drivers/net/bnxt/bnxt_ver.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom. + */ + +#ifndef _BNXT_VER_H_ +#define _BNXT_VER_H_ + +#ifndef BNXT_EXTRA_VER_H +#define BNXT_EXTRA_VER_H +#define DRV_MODULE_EXTRA_VER "-215.0.82.0" +#endif + +#define DRV_MODULE_NAME "bnxt" +#define DRV_MODULE_VERSION "1.0.0" DRV_MODULE_EXTRA_VER +#define UBOOT_MODULE_VER "1.0.0" +#define UBOOT_VERSION_MAJOR 1 +#define UBOOT_VERSION_MINOR 0 +#define UBOOT_VERSION_UPDATE 0 +#define DRV_MODULE_DESC "Broadcom NetXtreme-C/E driver" + +#endif /* _BNXT_VER_H_ */ diff --git a/drivers/net/bnxt/pci_ids.h b/drivers/net/bnxt/pci_ids.h new file mode 100644 index 0000000000..a6cc151a97 --- /dev/null +++ b/drivers/net/bnxt/pci_ids.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom. + */ + +#ifndef _PCI_IDS_H_ +#define _PCI_IDS_H_ + +#define PCI_VID_BROADCOM 0x14e4 +#define PCI_DID_NXT_57320_1 0x16F0 + +static struct pci_device_id bnxt_nics[] = { + {PCI_DEVICE(PCI_VID_BROADCOM, PCI_DID_NXT_57320_1)}, + {} +}; + +#endif /* _PCI_IDS_H_ */ -- 2.17.1

1 0

[PULL] u-boot-sh/master
by Marek Vasut 05 Dec '19

05 Dec '19

The following changes since commit 94d022bb400890f22fe35220d2519c3bce73f05e: Merge tag 'efi-2020-01-rc5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2019-12-03 18:12:58 -0500) are available in the Git repository at: git://git.denx.de/u-boot-sh.git master for you to fetch changes up to 019c9b3ea842514b3b4b90f7af01c3dc278a972e: ARM: rmobile: Convert M2N Gose to DM_SPI{,_FLASH} (2019-12-04 18:57:05 +0100) ---------------------------------------------------------------- Marek Vasut (3): ARM: rmobile: Convert H2 Lager to DM_SPI{,_FLASH} ARM: rmobile: Convert M2W Koelsch to DM_SPI{,_FLASH} ARM: rmobile: Convert M2N Gose to DM_SPI{,_FLASH} configs/gose_defconfig | 4 ++-- configs/koelsch_defconfig | 4 ++-- configs/lager_defconfig | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-)

2 1

[U-Boot] [PATCH v6 0/3] End of the MTD makefile cleanup
by Miquel Raynal 05 Dec '19

05 Dec '19

As rightfully pointed by Jagan, I should have dropped the dependency of cmd/sf.c and cmd/nand.c on mtd_uboot.c in patch 24/26 of the "MTD defconfigs/Kconfigs/Makefiles heavy cleanup" v5 series. Instead of sending the 40 patches again, here are only the last three patches with: * patch 1 (24/26) being corrected as per Jagan's comment * patch 2 (25/26) is untouched * patch 3 (26/26) is almost untouched but I had to resolve a conflict due to patch 1. Thanks, Miquèl Miquel Raynal (3): cmd: nand/sf: isolate legacy code cmd: make MTD commands depend on MTD mtd: Makefile: deep cleanup Makefile | 5 -- cmd/Kconfig | 10 ++-- cmd/Makefile | 3 ++ cmd/legacy-mtd-utils.c | 99 +++++++++++++++++++++++++++++++++++++++ cmd/legacy-mtd-utils.h | 14 ++++++ cmd/nand.c | 2 + cmd/sf.c | 2 + drivers/Makefile | 7 +-- drivers/mtd/Makefile | 50 ++++++++++++++------ drivers/mtd/mtd_uboot.c | 94 ------------------------------------- drivers/mtd/nand/Makefile | 5 ++ include/linux/mtd/mtd.h | 6 --- 12 files changed, 169 insertions(+), 128 deletions(-) create mode 100644 cmd/legacy-mtd-utils.c create mode 100644 cmd/legacy-mtd-utils.h -- 2.20.1

3 12

[U-Boot] [PATCH v5 00/26]MTD defconfigs/Kconfigs/Makefiles heavy cleanup
by Miquel Raynal 05 Dec '19

05 Dec '19

Hello, A year ago, while working on SPI-NAND support in U-Boot, I discovered when modifying Makefiles a confusing organization where: * Sub-directories/files are compiled from the root Makefile * Commands are at the root of everything First I sent a series to move Makefile entries in their respective directories. Then, I decided to continue working on the clarification of the Makefile hierarchy in MTD and I sent four iterations of this series which did not got merge at that time. Anyway, I revived this series by rebasing all my work and updating everything that needed an update. Here are the main points of the re-organization: * Rename CONFIG_MTD into CONFIG_DM_MTD to reserve CONFIG_MTD to what is called today CONFIG_MTD_DEVICE. * Fix build dependencies in defconfigs, like: "UBI and NAND depend on MTD". * Fix the Kconfig files to reflect these dependencies (as defconfigs have been updated, nothing should break). * Simplify the Makefiles: compiling the drivers/mtd/nand/raw/ sub-directory should just depend on MTD being compiled and the NAND core as well, there is absolutely no logic to make it depend on CMD_NAND. The New green Travis CI build for the fifth version of this series is there (yes, 53 iterations): Please note that the only red test fails because of timeout, not an actual error (at least I could not spot it). It is possible that this series will produce noticeable changes for the users. The only reason for that is because their configuration file was wrong. I have done my best to fix them one by one, but I am not omniscient. Thanks, Miquèl Note: as the number of Cc:'ed people reached 184 with get_maintainers.pl I decided to trim the list to: * People interested by the MTD subsystem. * A few maintainers: I had to tweak some defconfigs after more digging than with other boards (k2g, bcm11130, M54418TWR, ls104/108/208). Maintainers of these platforms are Cc:'ed. Changes since v4: ================= * Rebased on top of v2019.10-rc4. * Fixed tens of configurations that got broken since the last version of this series several months ago. * Added a specific commit for ls104/108/208 configurations. Changes since v3: ================= * As suggested by Vignesh, SPI_FLASH_MTD depends on MTD. Enforce this in Kconfig with a new patch. There is no defconfig to fix, all defconfigs with SPI_FLASH_MTD already use MTD. * s/coherent Makefile/appropriate Makefile/ in commit title of patch 1. * s/Kconfig/Makefile in commit message of "mtd: nand: remove dependency on commands in Kconfig" and "mtd: ubi: remove dependency on command in Kconfig". * Add Boris R-b tags. * Correct typos pointed by Boris. * Remove the if/endif in cmd/Kconfig about mtdparts, let the "depends on" that was already present. * Use an if/endif block to compile legacy-mtd-utils.c (to avoid failures when both 'sf' and 'nand' commands are compiled-in). * Merge all Makefile changes in one consistent commit as suggested by Boris. Changes since v2: ================= * Cleanup also applied to the SPL in an additional patch. * NOR dependency on MTD extracted from the patch adding MTD dependencies on commands only to do it in a separate change. * Typo s/copile/compile/ in "rename CONFIG_MTD_DEVICE..." commit log. * No more MTD depencency on SPI_FLASH, only kept on SPI_FLASH_MTD. * Same applies to the sf command. * Avoid compiling the NAND core while it is not needed (not speaking about the raw NAND core, really what is in drivers/mtd/nand:). * Last patch dropping CONFIG_MTD_PARTITIONS forgotten. We need them in order to reduce the final binary size. * Additional fixes in cmd/Kconfig. Changes since v1: ================= * Squashed both patches from the first series and included them in "mtd: simplify Makefiles". * Added all other patches. * Renamed CONFIG_NAND into CONFIG_MTD_RAW_NAND as suggested. Miquel Raynal (26): mtd: rename CONFIG_NAND -> CONFIG_MTD_RAW_NAND mtd: rename CONFIG_MTD -> CONFIG_DM_MTD mtd: rename CONFIG_MTD_DEVICE -> CONFIG_MTD mtd: ensure MTD is compiled when there is a NOR flash mtd: ensure MTD/the raw NAND core are compiled when there is a NAND flash mtd: ensure MTD is compiled when there is a SPI NOR flash using MTD mtd: ensure UBI is compiled when using fastmap mtd: ensure MTD is compiled when UBI is used mtd: ensure UBI is compiled when CMD_UBI is selected mtd: ensure UBI is compiled when ENV_IS_IN_UBI is selected mtd: ensure MTD_RAW_NAND is compiled when ENV_IS_IN_NAND is selected mtd: ensure CMD_NAND is compiled when its options are selected mtd: ensure MTD is compiled when CMD_MTDPARTS is selected configs: move CONFIG_MTD in defconfigs when set in arch includes configs: remove raw NAND core from k2g defconfigs configs: remove MTD support from bcm11130 and M54418TWR defconfigs configs: socfpga: mcvevk: Remove useless UBI infos configs: ls104x/ls108x/ls208x: Build the raw NAND core with TFABOOT mtd: nand: add includes in NAND core to avoid warnings dfu: add dependency on the raw NAND core mtd: nor: NOR flashes depend on MTD mtd: spi: SPI_FLASH_MTD depends on MTD cmd: mtdparts: Kconfig: join mtdparts command entry with its options cmd: nand/sf: isolate legacy code cmd: make MTD commands depend on MTD mtd: Makefile: deep cleanup Makefile | 5 - arch/arm/mach-omap2/mem-common.c | 6 +- board/BuR/brppt1/board.c | 2 +- board/BuR/brppt1/mux.c | 6 +- board/birdland/bav335x/board.c | 2 +- board/bosch/shc/board.c | 2 +- board/freescale/ls2080aqds/ls2080aqds.c | 2 +- board/freescale/t102xrdb/t102xrdb.c | 2 +- board/phytec/pcm051/mux.c | 4 +- board/siemens/pxm2/mux.c | 4 +- board/sunxi/README.nand | 2 +- board/ti/am335x/board.c | 2 +- board/ti/am335x/mux.c | 8 +- board/ti/am43xx/mux.c | 8 +- board/ti/ti816x/evm.c | 2 +- board/vscom/baltos/board.c | 2 +- board/vscom/baltos/mux.c | 2 +- cmd/Kconfig | 34 ++++--- cmd/Makefile | 3 + cmd/legacy-mtd-utils.c | 99 +++++++++++++++++++ cmd/legacy-mtd-utils.h | 14 +++ cmd/nand.c | 2 + cmd/sf.c | 2 + configs/10m50_defconfig | 2 +- configs/3c120_defconfig | 1 + configs/B4420QDS_NAND_defconfig | 3 +- configs/B4420QDS_SPIFLASH_defconfig | 1 + configs/B4420QDS_defconfig | 1 + configs/B4860QDS_NAND_defconfig | 3 +- configs/B4860QDS_SECURE_BOOT_defconfig | 1 + configs/B4860QDS_SPIFLASH_defconfig | 1 + configs/B4860QDS_defconfig | 1 + configs/BSC9131RDB_NAND_SYSCLK100_defconfig | 3 +- configs/BSC9131RDB_NAND_defconfig | 3 +- .../BSC9131RDB_SPIFLASH_SYSCLK100_defconfig | 1 + configs/BSC9131RDB_SPIFLASH_defconfig | 1 + ...BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig | 2 + configs/BSC9132QDS_NAND_DDRCLK100_defconfig | 3 +- ...BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig | 2 + configs/BSC9132QDS_NAND_DDRCLK133_defconfig | 3 +- .../BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK100_defconfig | 1 + .../BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK133_defconfig | 1 + ...C9132QDS_SDCARD_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig | 1 + ...C9132QDS_SDCARD_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig | 1 + ...132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig | 1 + .../BSC9132QDS_SPIFLASH_DDRCLK100_defconfig | 1 + ...132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig | 1 + .../BSC9132QDS_SPIFLASH_DDRCLK133_defconfig | 1 + configs/C29XPCIE_NAND_defconfig | 3 +- configs/C29XPCIE_NOR_SECBOOT_defconfig | 1 + configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 1 + configs/C29XPCIE_SPIFLASH_defconfig | 1 + configs/C29XPCIE_defconfig | 1 + configs/CHIP_pro_defconfig | 5 +- configs/M5208EVBE_defconfig | 1 + configs/M52277EVB_defconfig | 1 + configs/M52277EVB_stmicro_defconfig | 1 + configs/M5235EVB_Flash32_defconfig | 1 + configs/M5235EVB_defconfig | 1 + configs/M5249EVB_defconfig | 1 + configs/M5253DEMO_defconfig | 1 + configs/M5272C3_defconfig | 1 + configs/M5275EVB_defconfig | 1 + configs/M5282EVB_defconfig | 1 + configs/M53017EVB_defconfig | 1 + configs/M5329AFEE_defconfig | 1 + configs/M5329BFEE_defconfig | 1 + configs/M5373EVB_defconfig | 1 + configs/M54418TWR_nand_mii_defconfig | 1 + configs/M54418TWR_nand_rmii_defconfig | 1 + configs/M54418TWR_nand_rmii_lowfreq_defconfig | 1 + configs/M54451EVB_defconfig | 1 + configs/M54451EVB_stmicro_defconfig | 1 + configs/M54455EVB_a66_defconfig | 1 + configs/M54455EVB_defconfig | 1 + configs/M54455EVB_i66_defconfig | 1 + configs/M54455EVB_intel_defconfig | 1 + configs/M54455EVB_stm33_defconfig | 1 + configs/M5475AFE_defconfig | 1 + configs/M5475BFE_defconfig | 1 + configs/M5475CFE_defconfig | 1 + configs/M5475DFE_defconfig | 1 + configs/M5475EFE_defconfig | 1 + configs/M5475FFE_defconfig | 1 + configs/M5475GFE_defconfig | 1 + configs/M5485AFE_defconfig | 1 + configs/M5485BFE_defconfig | 1 + configs/M5485CFE_defconfig | 1 + configs/M5485DFE_defconfig | 1 + configs/M5485EFE_defconfig | 1 + configs/M5485FFE_defconfig | 1 + configs/M5485GFE_defconfig | 1 + configs/M5485HFE_defconfig | 1 + configs/MCR3000_defconfig | 1 + configs/MPC8308RDB_defconfig | 1 + configs/MPC8313ERDB_33_defconfig | 1 + configs/MPC8313ERDB_66_defconfig | 1 + configs/MPC8313ERDB_NAND_33_defconfig | 3 +- configs/MPC8313ERDB_NAND_66_defconfig | 3 +- configs/MPC8315ERDB_defconfig | 1 + configs/MPC8323ERDB_defconfig | 1 + configs/MPC832XEMDS_ATM_defconfig | 1 + configs/MPC832XEMDS_HOST_33_defconfig | 1 + configs/MPC832XEMDS_HOST_66_defconfig | 1 + configs/MPC832XEMDS_SLAVE_defconfig | 1 + configs/MPC832XEMDS_defconfig | 1 + configs/MPC8349EMDS_PCI64_defconfig | 1 + configs/MPC8349EMDS_SDRAM_defconfig | 1 + configs/MPC8349EMDS_SLAVE_defconfig | 1 + configs/MPC8349EMDS_defconfig | 1 + configs/MPC8349ITXGP_defconfig | 1 + configs/MPC8349ITX_LOWBOOT_defconfig | 1 + configs/MPC8349ITX_defconfig | 1 + configs/MPC837XEMDS_HOST_defconfig | 1 + configs/MPC837XEMDS_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/MPC8536DS_36BIT_defconfig | 1 + configs/MPC8536DS_SDCARD_defconfig | 1 + configs/MPC8536DS_SPIFLASH_defconfig | 1 + configs/MPC8536DS_defconfig | 1 + configs/MPC8541CDS_defconfig | 1 + configs/MPC8541CDS_legacy_defconfig | 1 + configs/MPC8544DS_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/MPC8555CDS_defconfig | 1 + configs/MPC8555CDS_legacy_defconfig | 1 + configs/MPC8568MDS_defconfig | 1 + configs/MPC8569MDS_ATM_defconfig | 1 + configs/MPC8569MDS_defconfig | 1 + configs/MPC8572DS_36BIT_defconfig | 1 + configs/MPC8572DS_defconfig | 1 + configs/MPC8610HPCD_defconfig | 1 + configs/MPC8641HPCN_36BIT_defconfig | 1 + configs/MPC8641HPCN_defconfig | 1 + configs/MigoR_defconfig | 1 + .../Nintendo_NES_Classic_Edition_defconfig | 3 +- .../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 2 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 3 +- .../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + ...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 2 + configs/P1010RDB-PA_NAND_defconfig | 3 +- configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + .../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + .../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 2 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 3 +- .../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + ...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 2 + configs/P1010RDB-PB_NAND_defconfig | 3 +- configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + .../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020MBG-PC_36BIT_defconfig | 1 + configs/P1020MBG-PC_SDCARD_defconfig | 1 + configs/P1020MBG-PC_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 3 +- configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 3 +- configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020UTM-PC_36BIT_defconfig | 1 + configs/P1020UTM-PC_SDCARD_defconfig | 1 + configs/P1020UTM-PC_defconfig | 1 + configs/P1021RDB-PC_36BIT_NAND_defconfig | 3 +- configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1021RDB-PC_36BIT_defconfig | 1 + configs/P1021RDB-PC_NAND_defconfig | 3 +- configs/P1021RDB-PC_SDCARD_defconfig | 1 + configs/P1021RDB-PC_SPIFLASH_defconfig | 1 + configs/P1021RDB-PC_defconfig | 1 + configs/P1022DS_36BIT_NAND_defconfig | 3 +- configs/P1022DS_36BIT_SDCARD_defconfig | 1 + configs/P1022DS_36BIT_SPIFLASH_defconfig | 1 + configs/P1022DS_36BIT_defconfig | 1 + configs/P1022DS_NAND_defconfig | 3 +- configs/P1022DS_SDCARD_defconfig | 1 + configs/P1022DS_SPIFLASH_defconfig | 1 + configs/P1022DS_defconfig | 1 + configs/P1023RDB_defconfig | 1 + configs/P1024RDB_36BIT_defconfig | 1 + configs/P1024RDB_NAND_defconfig | 3 +- configs/P1024RDB_SDCARD_defconfig | 1 + configs/P1024RDB_SPIFLASH_defconfig | 1 + configs/P1024RDB_defconfig | 1 + configs/P1025RDB_36BIT_defconfig | 1 + configs/P1025RDB_NAND_defconfig | 3 +- configs/P1025RDB_SDCARD_defconfig | 1 + configs/P1025RDB_SPIFLASH_defconfig | 1 + configs/P1025RDB_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 3 +- configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/P2041RDB_NAND_defconfig | 3 +- configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SECURE_BOOT_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/P3041DS_NAND_SECURE_BOOT_defconfig | 3 +- configs/P3041DS_NAND_defconfig | 3 +- configs/P3041DS_SDCARD_defconfig | 1 + configs/P3041DS_SECURE_BOOT_defconfig | 1 + configs/P3041DS_SPIFLASH_defconfig | 1 + configs/P3041DS_defconfig | 1 + configs/P4080DS_SDCARD_defconfig | 1 + configs/P4080DS_SECURE_BOOT_defconfig | 1 + configs/P4080DS_SPIFLASH_defconfig | 1 + configs/P4080DS_defconfig | 1 + configs/P5020DS_NAND_SECURE_BOOT_defconfig | 3 +- configs/P5020DS_NAND_defconfig | 3 +- configs/P5020DS_SDCARD_defconfig | 1 + configs/P5020DS_SECURE_BOOT_defconfig | 1 + configs/P5020DS_SPIFLASH_defconfig | 1 + configs/P5020DS_defconfig | 1 + configs/P5040DS_NAND_SECURE_BOOT_defconfig | 3 +- configs/P5040DS_NAND_defconfig | 3 +- configs/P5040DS_SDCARD_defconfig | 1 + configs/P5040DS_SECURE_BOOT_defconfig | 1 + configs/P5040DS_SPIFLASH_defconfig | 1 + configs/P5040DS_defconfig | 1 + configs/T1023RDB_NAND_defconfig | 3 +- configs/T1023RDB_SDCARD_defconfig | 1 + configs/T1023RDB_SECURE_BOOT_defconfig | 1 + configs/T1023RDB_SPIFLASH_defconfig | 1 + configs/T1023RDB_defconfig | 1 + configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 1 + configs/T1024QDS_DDR4_defconfig | 1 + configs/T1024QDS_NAND_defconfig | 3 +- configs/T1024QDS_SDCARD_defconfig | 1 + configs/T1024QDS_SECURE_BOOT_defconfig | 1 + configs/T1024QDS_SPIFLASH_defconfig | 1 + configs/T1024QDS_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 3 +- configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SECURE_BOOT_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1040D4RDB_NAND_defconfig | 3 +- configs/T1040D4RDB_SDCARD_defconfig | 1 + configs/T1040D4RDB_SECURE_BOOT_defconfig | 1 + configs/T1040D4RDB_SPIFLASH_defconfig | 1 + configs/T1040D4RDB_defconfig | 1 + configs/T1040QDS_DDR4_defconfig | 1 + configs/T1040QDS_SECURE_BOOT_defconfig | 1 + configs/T1040QDS_defconfig | 1 + configs/T1040RDB_NAND_defconfig | 3 +- configs/T1040RDB_SDCARD_defconfig | 1 + configs/T1040RDB_SECURE_BOOT_defconfig | 1 + configs/T1040RDB_SPIFLASH_defconfig | 1 + configs/T1040RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 3 +- configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SECURE_BOOT_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + .../T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 3 +- configs/T1042RDB_PI_NAND_defconfig | 3 +- configs/T1042RDB_PI_SDCARD_defconfig | 1 + configs/T1042RDB_PI_SPIFLASH_defconfig | 1 + configs/T1042RDB_PI_defconfig | 1 + configs/T1042RDB_SECURE_BOOT_defconfig | 1 + configs/T1042RDB_defconfig | 1 + configs/T2080QDS_NAND_defconfig | 3 +- configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 3 +- configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SECURE_BOOT_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_defconfig | 1 + configs/T2081QDS_NAND_defconfig | 3 +- configs/T2081QDS_SDCARD_defconfig | 1 + configs/T2081QDS_SPIFLASH_defconfig | 1 + configs/T2081QDS_defconfig | 1 + configs/T4160QDS_NAND_defconfig | 3 +- configs/T4160QDS_SDCARD_defconfig | 1 + configs/T4160QDS_SECURE_BOOT_defconfig | 1 + configs/T4160QDS_defconfig | 1 + configs/T4160RDB_defconfig | 1 + configs/T4240QDS_NAND_defconfig | 3 +- configs/T4240QDS_SDCARD_defconfig | 1 + configs/T4240QDS_SECURE_BOOT_defconfig | 1 + configs/T4240QDS_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + configs/TQM834x_defconfig | 2 +- configs/TWR-P1025_defconfig | 2 +- configs/UCP1020_defconfig | 1 + configs/adp-ae3xx_defconfig | 3 +- configs/adp-ag101p_defconfig | 1 + configs/ae350_rv32_defconfig | 1 + configs/alt_defconfig | 2 +- configs/am335x_baltos_defconfig | 4 +- configs/am335x_evm_defconfig | 3 +- configs/am335x_guardian_defconfig | 3 +- configs/am335x_hs_evm_defconfig | 3 +- configs/am335x_hs_evm_uart_defconfig | 3 +- configs/am335x_igep003x_defconfig | 4 +- configs/am3517_crane_defconfig | 3 +- configs/am3517_evm_defconfig | 4 +- configs/am43xx_evm_defconfig | 3 +- configs/am43xx_evm_rtconly_defconfig | 3 +- configs/am43xx_evm_usbhost_boot_defconfig | 3 +- configs/am43xx_hs_evm_defconfig | 3 +- configs/amcore_defconfig | 1 + configs/ap121_defconfig | 1 + configs/ap143_defconfig | 1 + configs/apf27_defconfig | 5 +- configs/apx4devkit_defconfig | 4 +- configs/aristainetos2_defconfig | 5 +- configs/aristainetos2b_defconfig | 5 +- configs/aristainetos_defconfig | 5 +- configs/astro_mcf5373l_defconfig | 1 + configs/at91rm9200ek_defconfig | 1 + configs/at91rm9200ek_ram_defconfig | 1 + configs/at91sam9260ek_dataflash_cs0_defconfig | 3 +- configs/at91sam9260ek_dataflash_cs1_defconfig | 3 +- configs/at91sam9260ek_nandflash_defconfig | 3 +- configs/at91sam9261ek_dataflash_cs0_defconfig | 3 +- configs/at91sam9261ek_dataflash_cs3_defconfig | 3 +- configs/at91sam9261ek_nandflash_defconfig | 3 +- configs/at91sam9263ek_dataflash_cs0_defconfig | 3 +- configs/at91sam9263ek_dataflash_defconfig | 3 +- configs/at91sam9263ek_nandflash_defconfig | 3 +- configs/at91sam9263ek_norflash_boot_defconfig | 3 +- configs/at91sam9263ek_norflash_defconfig | 3 +- configs/at91sam9g10ek_dataflash_cs0_defconfig | 3 +- configs/at91sam9g10ek_dataflash_cs3_defconfig | 3 +- configs/at91sam9g10ek_nandflash_defconfig | 3 +- configs/at91sam9g20ek_2mmc_defconfig | 3 +- .../at91sam9g20ek_2mmc_nandflash_defconfig | 3 +- configs/at91sam9g20ek_dataflash_cs0_defconfig | 3 +- configs/at91sam9g20ek_dataflash_cs1_defconfig | 3 +- configs/at91sam9g20ek_nandflash_defconfig | 3 +- configs/at91sam9m10g45ek_mmc_defconfig | 3 +- configs/at91sam9m10g45ek_nandflash_defconfig | 2 + configs/at91sam9n12ek_mmc_defconfig | 3 +- configs/at91sam9n12ek_nandflash_defconfig | 2 + configs/at91sam9n12ek_spiflash_defconfig | 3 +- configs/at91sam9rlek_dataflash_defconfig | 3 +- configs/at91sam9rlek_mmc_defconfig | 3 +- configs/at91sam9rlek_nandflash_defconfig | 3 +- configs/at91sam9x5ek_dataflash_defconfig | 4 +- configs/at91sam9x5ek_mmc_defconfig | 4 +- configs/at91sam9x5ek_nandflash_defconfig | 3 + configs/at91sam9x5ek_spiflash_defconfig | 4 +- configs/at91sam9xeek_dataflash_cs0_defconfig | 3 +- configs/at91sam9xeek_dataflash_cs1_defconfig | 3 +- configs/at91sam9xeek_nandflash_defconfig | 3 +- configs/axm_defconfig | 3 +- configs/bcm11130_nand_defconfig | 1 - configs/bcm963158_ram_defconfig | 3 +- configs/bcm968380gerg_ram_defconfig | 3 +- configs/bcm968580xref_ram_defconfig | 3 +- configs/bg0900_defconfig | 4 +- configs/bitmain_antminer_s9_defconfig | 7 +- configs/bk4r1_defconfig | 6 +- configs/blanche_defconfig | 1 + configs/boston32r2_defconfig | 1 + configs/boston32r2el_defconfig | 1 + configs/boston32r6_defconfig | 1 + configs/boston32r6el_defconfig | 1 + configs/boston64r2_defconfig | 1 + configs/boston64r2el_defconfig | 1 + configs/boston64r6_defconfig | 1 + configs/boston64r6el_defconfig | 1 + configs/brppt1_nand_defconfig | 3 +- configs/brppt1_spi_defconfig | 2 +- configs/caddy2_defconfig | 1 + configs/cairo_defconfig | 3 +- configs/chiliboard_defconfig | 3 +- configs/clearfog_defconfig | 1 + configs/cm_fx6_defconfig | 3 +- configs/cm_t335_defconfig | 3 +- configs/cm_t35_defconfig | 3 +- configs/cm_t43_defconfig | 3 +- configs/cobra5272_defconfig | 1 + configs/colibri-imx6ull_defconfig | 7 +- configs/colibri_imx7_defconfig | 5 +- configs/colibri_pxa270_defconfig | 1 + configs/colibri_t20_defconfig | 3 + configs/colibri_vf_defconfig | 5 +- configs/comtrend_ar5315u_ram_defconfig | 1 + configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_ct5361_ram_defconfig | 1 + configs/comtrend_wap5813n_ram_defconfig | 1 + configs/corvus_defconfig | 3 +- configs/crs305-1g-4s_defconfig | 2 +- configs/da850evm_defconfig | 1 - configs/da850evm_nand_defconfig | 2 +- configs/db-88f6820-amc_defconfig | 3 +- configs/db-mv784mp-gp_defconfig | 3 +- configs/db-xc3-24g4xg_defconfig | 4 +- configs/devkit3250_defconfig | 3 +- configs/devkit8000_defconfig | 3 +- configs/display5_defconfig | 2 +- configs/display5_factory_defconfig | 2 +- configs/dns325_defconfig | 3 + configs/dockstar_defconfig | 3 + configs/dra7xx_evm_defconfig | 3 +- configs/dra7xx_hs_evm_defconfig | 3 +- configs/draco_defconfig | 4 +- configs/ds414_defconfig | 3 +- configs/eb_cpu5282_defconfig | 1 + configs/eb_cpu5282_internal_defconfig | 1 + configs/edb9315a_defconfig | 1 + configs/edminiv2_defconfig | 1 + configs/etamin_defconfig | 4 +- configs/ethernut5_defconfig | 4 +- configs/evb-rv1108_defconfig | 1 + configs/flea3_defconfig | 3 +- .../gardena-smart-gateway-at91sam_defconfig | 2 + ...gardena-smart-gateway-mt7688-ram_defconfig | 2 + .../gardena-smart-gateway-mt7688_defconfig | 2 + configs/gazerbeam_defconfig | 1 + configs/goflexhome_defconfig | 3 + configs/gose_defconfig | 2 +- configs/gurnard_defconfig | 3 +- configs/guruplug_defconfig | 3 + configs/gwventana_emmc_defconfig | 3 +- configs/gwventana_gw5904_defconfig | 3 +- configs/gwventana_nand_defconfig | 5 +- configs/harmony_defconfig | 3 + configs/helios4_defconfig | 1 + configs/hrcon_defconfig | 1 + configs/hrcon_dh_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/ib62x0_defconfig | 3 + configs/iconnect_defconfig | 3 + configs/ids8313_defconfig | 3 + configs/igep00x0_defconfig | 4 +- configs/imx6dl_icore_nand_defconfig | 4 +- configs/imx6q_icore_nand_defconfig | 4 +- configs/imx6q_logic_defconfig | 5 +- configs/imx6qdl_icore_mmc_defconfig | 4 +- configs/imx6qdl_icore_nand_defconfig | 4 +- configs/imx6ul_geam_nand_defconfig | 4 +- configs/imx6ul_isiot_nand_defconfig | 4 +- configs/integratorap_cm720t_defconfig | 1 + configs/integratorap_cm920t_defconfig | 1 + configs/integratorap_cm926ejs_defconfig | 1 + configs/integratorap_cm946es_defconfig | 1 + configs/integratorcp_cm1136_defconfig | 1 + configs/integratorcp_cm920t_defconfig | 1 + configs/integratorcp_cm926ejs_defconfig | 1 + configs/integratorcp_cm946es_defconfig | 1 + configs/k2e_evm_defconfig | 4 +- configs/k2e_hs_evm_defconfig | 4 +- configs/k2g_evm_defconfig | 5 +- configs/k2g_hs_evm_defconfig | 5 +- configs/k2hk_evm_defconfig | 4 +- configs/k2hk_hs_evm_defconfig | 4 +- configs/k2l_evm_defconfig | 4 +- configs/k2l_hs_evm_defconfig | 4 +- configs/khadas-vim2_defconfig | 2 +- configs/km_kirkwood_128m16_defconfig | 3 + configs/km_kirkwood_defconfig | 3 + configs/km_kirkwood_pci_defconfig | 3 + configs/kmcoge4_defconfig | 2 + configs/kmcoge5ne_defconfig | 2 + configs/kmcoge5un_defconfig | 3 + configs/kmeter1_defconfig | 3 +- configs/kmnusa_defconfig | 3 + configs/kmopti2_defconfig | 3 +- configs/kmsugp1_defconfig | 3 + configs/kmsupx5_defconfig | 3 +- configs/kmsuv31_defconfig | 3 + configs/kmtegr1_defconfig | 2 + configs/kmtepr2_defconfig | 3 +- configs/koelsch_defconfig | 2 +- configs/kzm9g_defconfig | 1 + configs/lager_defconfig | 2 +- configs/libretech-ac_defconfig | 2 +- configs/linkit-smart-7688-ram_defconfig | 1 + configs/linkit-smart-7688_defconfig | 1 + configs/lion-rk3368_defconfig | 1 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 2 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 2 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1043aqds_tfa_defconfig | 2 + configs/ls1043ardb_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_defconfig | 1 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_nand_defconfig | 2 + .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_tfa_defconfig | 2 + configs/ls1046afrwy_tfa_defconfig | 2 + configs/ls1046aqds_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_defconfig | 2 + configs/ls1046aqds_lpuart_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 2 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1046aqds_tfa_defconfig | 2 + configs/ls1046ardb_emmc_defconfig | 2 + configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1046ardb_qspi_defconfig | 2 + configs/ls1046ardb_qspi_spl_defconfig | 2 + .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 + configs/ls1046ardb_sdcard_defconfig | 2 + configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1046ardb_tfa_defconfig | 2 + configs/ls1088aqds_defconfig | 2 + configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1088aqds_qspi_defconfig | 2 + configs/ls1088aqds_sdcard_ifc_defconfig | 2 + configs/ls1088aqds_sdcard_qspi_defconfig | 2 + configs/ls1088aqds_tfa_defconfig | 2 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1088ardb_qspi_defconfig | 2 + ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1088ardb_sdcard_qspi_defconfig | 2 + configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1088ardb_tfa_defconfig | 2 + configs/ls2080a_simu_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 2 + configs/ls2080aqds_qspi_defconfig | 2 + configs/ls2080aqds_sdcard_defconfig | 2 + configs/ls2080ardb_SECURE_BOOT_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 2 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + configs/m53menlo_defconfig | 5 +- configs/malta64_defconfig | 1 + configs/malta64el_defconfig | 1 + configs/malta_defconfig | 1 + configs/maltael_defconfig | 1 + configs/mccmon6_nor_defconfig | 4 +- configs/mccmon6_sd_defconfig | 4 +- configs/medcom-wide_defconfig | 2 + configs/meesc_defconfig | 3 +- configs/mgcoge3un_defconfig | 3 + configs/microblaze-generic_defconfig | 2 +- configs/mpc8308_p1m_defconfig | 1 + configs/mscc_ocelot_defconfig | 1 + configs/mx28evk_auart_console_defconfig | 5 +- configs/mx28evk_defconfig | 5 +- configs/mx28evk_nand_defconfig | 5 +- configs/mx28evk_spi_defconfig | 5 +- configs/mx31pdk_defconfig | 3 +- configs/mx35pdk_defconfig | 3 +- configs/mx53ard_defconfig | 3 +- configs/mx6sabreauto_defconfig | 4 +- configs/mx6sxsabreauto_defconfig | 4 +- configs/nas220_defconfig | 3 + configs/netgear_cg3100d_ram_defconfig | 1 + configs/nsa310s_defconfig | 3 + configs/omap35_logic_defconfig | 4 +- configs/omap35_logic_somlv_defconfig | 4 +- configs/omap3_beagle_defconfig | 4 +- configs/omap3_evm_defconfig | 4 +- configs/omap3_ha_defconfig | 4 +- configs/omap3_logic_defconfig | 4 +- configs/omap3_logic_somlv_defconfig | 4 +- configs/omap3_overo_defconfig | 4 +- configs/omap3_pandora_defconfig | 4 +- configs/omap3_zoom1_defconfig | 3 +- configs/omapl138_lcdk_defconfig | 3 +- configs/openrd_base_defconfig | 3 + configs/openrd_client_defconfig | 3 + configs/openrd_ultimate_defconfig | 3 + configs/pcm052_defconfig | 4 + configs/pcm058_defconfig | 5 +- configs/pengwyn_defconfig | 3 +- configs/pfla02_defconfig | 4 +- configs/phycore-am335x-r2-wega_defconfig | 2 +- configs/phycore_pcl063_defconfig | 3 +- configs/platinum_picon_defconfig | 5 +- configs/platinum_titanium_defconfig | 5 +- configs/plutux_defconfig | 2 + configs/pm9261_defconfig | 3 +- configs/pm9263_defconfig | 3 +- configs/pm9g45_defconfig | 2 + configs/pogo_e02_defconfig | 3 + configs/porter_defconfig | 2 +- configs/pxm2_defconfig | 4 +- configs/qemu_arm64_defconfig | 2 +- configs/qemu_arm_defconfig | 2 +- configs/qemu_mips64_defconfig | 1 + configs/qemu_mips64el_defconfig | 1 + configs/qemu_mips_defconfig | 1 + configs/qemu_mipsel_defconfig | 1 + configs/r2dplus_defconfig | 1 + configs/r7780mp_defconfig | 1 + configs/r8a77995_draak_defconfig | 2 +- configs/rastaban_defconfig | 4 +- configs/rut_defconfig | 4 +- configs/s5pc210_universal_defconfig | 2 +- configs/sagem_f@st1704_ram_defconfig | 1 + configs/sama5d2_ptc_ek_mmc_defconfig | 3 +- configs/sama5d2_ptc_ek_nandflash_defconfig | 2 + configs/sama5d36ek_cmp_mmc_defconfig | 3 +- configs/sama5d36ek_cmp_nandflash_defconfig | 2 + configs/sama5d36ek_cmp_spiflash_defconfig | 3 +- configs/sama5d3_xplained_mmc_defconfig | 4 +- configs/sama5d3_xplained_nandflash_defconfig | 3 + configs/sama5d3xek_mmc_defconfig | 3 +- configs/sama5d3xek_nandflash_defconfig | 2 + configs/sama5d3xek_spiflash_defconfig | 3 +- configs/sama5d4_xplained_mmc_defconfig | 3 +- configs/sama5d4_xplained_nandflash_defconfig | 2 + configs/sama5d4_xplained_spiflash_defconfig | 3 +- configs/sama5d4ek_mmc_defconfig | 3 +- configs/sama5d4ek_nandflash_defconfig | 2 + configs/sama5d4ek_spiflash_defconfig | 3 +- configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sbc8349_PCI_33_defconfig | 1 + configs/sbc8349_PCI_66_defconfig | 1 + configs/sbc8349_defconfig | 1 + configs/sbc8548_PCI_33_PCIE_defconfig | 1 + configs/sbc8548_PCI_33_defconfig | 1 + configs/sbc8548_PCI_66_PCIE_defconfig | 1 + configs/sbc8548_PCI_66_defconfig | 1 + configs/sbc8548_defconfig | 1 + configs/sbc8641d_defconfig | 1 + configs/seaboard_defconfig | 2 + configs/sfr_nb4-ser_ram_defconfig | 1 + configs/sh7763rdp_defconfig | 1 + configs/sheevaplug_defconfig | 3 + configs/silk_defconfig | 2 +- configs/smartweb_defconfig | 3 +- configs/smdkc100_defconfig | 2 +- configs/snapper9260_defconfig | 3 +- configs/snapper9g20_defconfig | 3 +- configs/socfpga_arria10_defconfig | 2 +- configs/socfpga_arria5_defconfig | 3 +- configs/socfpga_cyclone5_defconfig | 3 +- configs/socfpga_dbm_soc1_defconfig | 2 +- configs/socfpga_de0_nano_soc_defconfig | 3 +- configs/socfpga_de10_nano_defconfig | 2 +- configs/socfpga_de1_soc_defconfig | 2 +- configs/socfpga_is1_defconfig | 3 +- configs/socfpga_mcvevk_defconfig | 3 - configs/socfpga_sockit_defconfig | 3 +- configs/socfpga_socrates_defconfig | 3 +- configs/socfpga_sr1500_defconfig | 3 +- configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 3 +- configs/socrates_defconfig | 1 + configs/spear300_defconfig | 2 +- configs/spear300_nand_defconfig | 4 +- configs/spear300_usbtty_defconfig | 2 +- configs/spear300_usbtty_nand_defconfig | 4 +- configs/spear310_defconfig | 2 +- configs/spear310_nand_defconfig | 4 +- configs/spear310_pnor_defconfig | 2 +- configs/spear310_usbtty_defconfig | 2 +- configs/spear310_usbtty_nand_defconfig | 4 +- configs/spear310_usbtty_pnor_defconfig | 2 +- configs/spear320_defconfig | 2 +- configs/spear320_nand_defconfig | 4 +- configs/spear320_pnor_defconfig | 2 +- configs/spear320_usbtty_defconfig | 2 +- configs/spear320_usbtty_nand_defconfig | 4 +- configs/spear320_usbtty_pnor_defconfig | 2 +- configs/spear600_defconfig | 2 +- configs/spear600_nand_defconfig | 4 +- configs/spear600_usbtty_defconfig | 2 +- configs/spear600_usbtty_nand_defconfig | 4 +- configs/stm32f429-discovery_defconfig | 1 + configs/stm32f429-evaluation_defconfig | 1 + configs/stm32f469-discovery_defconfig | 2 +- configs/stm32f746-disco_defconfig | 3 +- configs/stm32mp15_basic_defconfig | 3 +- configs/stm32mp15_trusted_defconfig | 3 +- configs/stmark2_defconfig | 2 +- configs/stout_defconfig | 2 +- configs/strider_con_defconfig | 1 + configs/strider_con_dp_defconfig | 1 + configs/strider_cpu_defconfig | 1 + configs/strider_cpu_dp_defconfig | 1 + configs/suvd3_defconfig | 3 +- configs/tao3530_defconfig | 4 +- configs/taurus_defconfig | 3 +- configs/tec_defconfig | 2 + configs/thuban_defconfig | 4 +- configs/ti816x_evm_defconfig | 3 +- configs/titanium_defconfig | 5 +- configs/tplink_wdr4300_defconfig | 1 + configs/tricorder_defconfig | 4 +- configs/tricorder_flash_defconfig | 4 +- configs/tuge1_defconfig | 3 +- configs/turris_mox_defconfig | 1 + configs/tuxx1_defconfig | 3 +- configs/uDPU_defconfig | 2 +- configs/uniphier_ld4_sld8_defconfig | 4 +- configs/uniphier_v7_defconfig | 4 +- configs/uniphier_v8_defconfig | 4 +- configs/usb_a9263_dataflash_defconfig | 3 +- configs/vct_platinum_defconfig | 1 + configs/vct_platinum_onenand_defconfig | 3 +- configs/vct_platinum_onenand_small_defconfig | 3 +- configs/vct_platinum_small_defconfig | 1 + configs/vct_platinumavc_defconfig | 1 + configs/vct_platinumavc_onenand_defconfig | 3 +- .../vct_platinumavc_onenand_small_defconfig | 3 +- configs/vct_platinumavc_small_defconfig | 1 + configs/vct_premium_defconfig | 1 + configs/vct_premium_onenand_defconfig | 3 +- configs/vct_premium_onenand_small_defconfig | 3 +- configs/vct_premium_small_defconfig | 1 + configs/ve8313_defconfig | 1 + configs/vexpress_aemv8a_juno_defconfig | 2 +- configs/vexpress_aemv8a_semi_defconfig | 2 +- configs/vexpress_ca15_tc2_defconfig | 2 +- configs/vexpress_ca5x2_defconfig | 2 +- configs/vexpress_ca9x4_defconfig | 2 +- configs/vf610twr_defconfig | 4 + configs/vf610twr_nand_defconfig | 4 + configs/vme8349_defconfig | 1 + configs/wb45n_defconfig | 3 +- configs/wb50n_defconfig | 3 +- configs/woodburn_defconfig | 3 +- configs/woodburn_sd_defconfig | 4 +- configs/work_92105_defconfig | 2 + configs/x530_defconfig | 3 +- configs/x600_defconfig | 3 + configs/xilinx_zynqmp_mini_nand_defconfig | 3 +- .../xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 5 +- .../xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 4 +- configs/xpedite517x_defconfig | 1 + configs/xpedite520x_defconfig | 1 + configs/xpedite537x_defconfig | 1 + configs/xpedite550x_defconfig | 1 + configs/xtfpga_defconfig | 1 + configs/zmx25_defconfig | 1 + configs/zynq_cse_nand_defconfig | 4 +- configs/zynq_cse_nor_defconfig | 1 + configs/zynq_zc770_xm011_defconfig | 5 +- configs/zynq_zc770_xm011_x16_defconfig | 5 +- configs/zynq_zc770_xm012_defconfig | 1 + drivers/Makefile | 7 +- drivers/dfu/Kconfig | 1 + drivers/mtd/Kconfig | 13 +-- drivers/mtd/Makefile | 50 +++++++--- drivers/mtd/mtd_uboot.c | 96 +----------------- drivers/mtd/nand/Makefile | 5 + drivers/mtd/nand/bbt.c | 1 + drivers/mtd/nand/core.c | 1 + drivers/mtd/nand/raw/Kconfig | 4 +- drivers/mtd/nand/raw/nand.c | 2 +- drivers/mtd/onenand/onenand_uboot.c | 2 +- drivers/mtd/spi/Kconfig | 2 +- env/Kconfig | 2 + include/configs/B4860QDS.h | 10 +- include/configs/BSC9131RDB.h | 4 +- include/configs/BSC9132QDS.h | 8 +- include/configs/C29XPCIE.h | 8 +- include/configs/P1010RDB.h | 12 +-- include/configs/P1022DS.h | 10 +- include/configs/P2041RDB.h | 6 +- include/configs/T102xQDS.h | 8 +- include/configs/T102xRDB.h | 8 +- include/configs/T1040QDS.h | 6 +- include/configs/T104xRDB.h | 12 +-- include/configs/T208xQDS.h | 8 +- include/configs/T208xRDB.h | 8 +- include/configs/T4240QDS.h | 10 +- include/configs/T4240RDB.h | 6 +- include/configs/am335x_evm.h | 6 +- include/configs/am335x_guardian.h | 4 +- include/configs/am3517_evm.h | 6 +- include/configs/am43xx_evm.h | 6 +- include/configs/baltos.h | 6 +- include/configs/bav335x.h | 8 +- include/configs/broadcom_bcm963158.h | 4 +- include/configs/broadcom_bcm968380gerg.h | 4 +- include/configs/broadcom_bcm968580xref.h | 4 +- include/configs/brppt1.h | 16 +-- include/configs/corenet_ds.h | 8 +- include/configs/da850evm.h | 4 +- include/configs/dra7xx_evm.h | 4 +- include/configs/ls2080ardb.h | 2 +- include/configs/mvebu_armada-37xx.h | 1 - include/configs/omap3_beagle.h | 10 +- include/configs/omap3_evm.h | 10 +- include/configs/omap3_logic.h | 2 +- include/configs/omap3_overo.h | 6 +- include/configs/omap3_pandora.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/p1_p2_rdb_pc.h | 8 +- include/configs/phycore_am335x_r2.h | 6 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/socfpga_stratix10_socdk.h | 1 - include/configs/ti_armv7_common.h | 2 +- include/configs/ti_armv7_omap.h | 2 +- include/configs/ti_omap3_common.h | 2 +- include/configs/x530.h | 1 - include/env_internal.h | 4 +- include/environment/ti/dfu.h | 2 +- include/environment/ti/nand.h | 2 +- include/flash.h | 2 +- include/linux/mtd/mtd.h | 6 -- 849 files changed, 1591 insertions(+), 640 deletions(-) create mode 100644 cmd/legacy-mtd-utils.c create mode 100644 cmd/legacy-mtd-utils.h -- 2.20.1

4 66

[PATCH] RFE: tools: fix parallel build of tools-all
by Peter Robinson 05 Dec '19

05 Dec '19

Commit 4d90f6cd9813 breaks parallel builds in 2020.01-rc series. This fixes the issue, reverting it also fixes it. Not sure which is the best route. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 8024baaddf..4330c2f3a4 100644 --- a/Makefile +++ b/Makefile @@ -1895,14 +1895,14 @@ checkarmreloc: u-boot false; \ fi -tools/version.h: include/version.h +version.h: include/version.h $(call if_changed,copy) -envtools: scripts_basic $(version_h) $(timestamp_h) tools/version.h +envtools: scripts_basic $(version_h) $(timestamp_h) version.h $(Q)$(MAKE) $(build)=tools/env tools-only: export TOOLS_ONLY=y -tools-only: scripts_basic $(version_h) $(timestamp_h) tools/version.h +tools-only: scripts_basic $(version_h) $(timestamp_h) version.h $(Q)$(MAKE) $(build)=tools tools-all: export HOST_TOOLS_ALL=y -- 2.23.0

2 4

[PATCH 16/20] ram: add SDRAM driver for i.MXRT SoCs
by Giulio Benetti 04 Dec '19

04 Dec '19

Add SDRAM driver for i.MXRT SoCs. Signed-off-by: Giulio Benetti <giulio.benetti(a)benettiengineering.com> --- drivers/ram/Kconfig | 8 + drivers/ram/Makefile | 2 + drivers/ram/imxrt_sdram.c | 439 +++++++++++++++++++++++ include/dt-bindings/memory/imxrt-sdram.h | 100 ++++++ 4 files changed, 549 insertions(+) create mode 100644 drivers/ram/imxrt_sdram.c create mode 100644 include/dt-bindings/memory/imxrt-sdram.h diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index b454ceb599..56fea7c94c 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -65,5 +65,13 @@ config K3_J721E_DDRSS Enabling this config adds support for the DDR memory controller on J721E family of SoCs. +config IMXRT_SDRAM + bool "Enable i.MXRT SDRAM support" + depends on RAM + help + i.MXRT family devices support smart external memory controller(SEMC) + to support external memories like sdram, psram & nand. + This driver is for the sdram memory interface with the SEMC. + source "drivers/ram/rockchip/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 4b77969b39..5c897410c6 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -15,3 +15,5 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/ + +obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c new file mode 100644 index 0000000000..af7400be82 --- /dev/null +++ b/drivers/ram/imxrt_sdram.c @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti <giulio.benetti(a)benettiengineering.com> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> +#include <asm/io.h> + +/* SDRAM Command Code */ +#define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */ +#define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */ +#define SD_CC_IRD 0x8 /* IP command - Read */ +#define SD_CC_IWR 0x9 /* IP command - Write */ +#define SD_CC_IMS 0xA /* IP command - Set Mode Register */ +#define SD_CC_IACT 0xB /* IP command - ACTIVE */ +#define SD_CC_IAF 0xC /* IP command - Auto Refresh */ +#define SD_CC_ISF 0xD /* IP Command - Self Refresh */ +#define SD_CC_IPRE 0xE /* IP command - Precharge */ +#define SD_CC_IPREA 0xF /* IP command - Precharge ALL */ + +#define SEMC_MCR_MDIS BIT(1) +#define SEMC_MCR_DQSMD BIT(2) + +#define SEMC_INTR_IPCMDERR BIT(1) +#define SEMC_INTR_IPCMDDONE BIT(0) + +#define SEMC_IPCMD_KEY 0xA55A0000 + +struct imxrt_semc_regs { + /* 0x0 */ + u32 mcr; + u32 iocr; + u32 bmcr0; + u32 bmcr1; + u32 br[9]; + + /* 0x34 */ + u32 res1; + u32 inten; + u32 intr; + /* 0x40 */ + u32 sdramcr0; + u32 sdramcr1; + u32 sdramcr2; + u32 sdramcr3; + /* 0x50 */ + u32 nandcr0; + u32 nandcr1; + u32 nandcr2; + u32 nandcr3; + /* 0x60 */ + u32 norcr0; + u32 norcr1; + u32 norcr2; + u32 norcr3; + /* 0x70 */ + u32 sramcr0; + u32 sramcr1; + u32 sramcr2; + u32 sramcr3; + /* 0x80 */ + u32 dbicr0; + u32 dbicr1; + u32 res2[2]; + /* 0x90 */ + u32 ipcr0; + u32 ipcr1; + u32 ipcr2; + u32 ipcmd; + /* 0xA0 */ + u32 iptxdat; + u32 res3[3]; + /* 0xB0 */ + u32 iprxdat; + u32 res4[3]; + /* 0xC0 */ + u32 sts[16]; +}; + +#define SEMC_IOCR_MUX_A8_SHIFT 0 +#define SEMC_IOCR_MUX_CSX0_SHIFT 3 +#define SEMC_IOCR_MUX_CSX1_SHIFT 6 +#define SEMC_IOCR_MUX_CSX2_SHIFT 9 +#define SEMC_IOCR_MUX_CSX3_SHIFT 12 +#define SEMC_IOCR_MUX_RDY_SHIFT 15 + +struct imxrt_sdram_mux { + u8 a8; + u8 csx0; + u8 csx1; + u8 csx2; + u8 csx3; + u8 rdy; +}; + +#define SEMC_SDRAMCR0_PS_SHIFT 0 +#define SEMC_SDRAMCR0_BL_SHIFT 4 +#define SEMC_SDRAMCR0_COL_SHIFT 8 +#define SEMC_SDRAMCR0_CL_SHIFT 10 + +struct imxrt_sdram_control { + u8 memory_width; + u8 burst_len; + u8 no_columns; + u8 cas_latency; +}; + +#define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0 +#define SEMC_SDRAMCR1_ACT2RW_SHIFT 4 +#define SEMC_SDRAMCR1_RFRC_SHIFT 8 +#define SEMC_SDRAMCR1_WRC_SHIFT 13 +#define SEMC_SDRAMCR1_CKEOFF_SHIFT 16 +#define SEMC_SDRAMCR1_ACT2PRE_SHIFT 20 + +#define SEMC_SDRAMCR2_SRRC_SHIFT 0 +#define SEMC_SDRAMCR2_REF2REF_SHIFT 8 +#define SEMC_SDRAMCR2_ACT2ACT_SHIFT 16 +#define SEMC_SDRAMCR2_ITO_SHIFT 24 + +#define SEMC_SDRAMCR3_REN BIT(0) +#define SEMC_SDRAMCR3_REBL_SHIFT 1 +#define SEMC_SDRAMCR3_PRESCALE_SHIFT 8 +#define SEMC_SDRAMCR3_RT_SHIFT 16 +#define SEMC_SDRAMCR3_UT_SHIFT 24 + +struct imxrt_sdram_timing { + u8 pre2act; + u8 act2rw; + u8 rfrc; + u8 wrc; + u8 ckeoff; + u8 act2pre; + + u8 srrc; + u8 ref2ref; + u8 act2act; + u8 ito; + + u8 rebl; + u8 prescale; + u8 rt; + u8 ut; +}; + +enum imxrt_semc_bank { + SDRAM_BANK1, + SDRAM_BANK2, + SDRAM_BANK3, + SDRAM_BANK4, + MAX_SDRAM_BANK, +}; + +#define SEMC_BR_VLD_MASK 1 +#define SEMC_BR_MS_SHIFT 1 + +struct bank_params { + enum imxrt_semc_bank target_bank; + u32 base_address; + u32 memory_size; +}; + +struct imxrt_sdram_params { + struct imxrt_semc_regs *base; + + struct imxrt_sdram_mux *sdram_mux; + struct imxrt_sdram_control *sdram_control; + struct imxrt_sdram_timing *sdram_timing; + + struct bank_params bank_params[MAX_SDRAM_BANK]; + u8 no_sdram_banks; +}; + +static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs) +{ + do { + readl(&regs->intr); + + if (regs->intr & SEMC_INTR_IPCMDDONE) + return 0; + if (regs->intr & SEMC_INTR_IPCMDERR) + return -EIO; + + mdelay(50); + } while (1); +} + +static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr, + u32 ipcmd, u32 wd, u32 *rd) +{ + int ret; + + if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS) + writel(wd, &regs->iptxdat); + + /* set slave address for every command as specified on RM */ + writel(mem_addr, &regs->ipcr0); + + /* execute command */ + writel(SEMC_IPCMD_KEY | ipcmd, &regs->ipcmd); + + ret = imxrt_sdram_wait_ipcmd_done(regs); + if (ret < 0) + return ret; + + if (ipcmd == SD_CC_IRD) { + if (!rd) + return -EINVAL; + + *rd = readl(&regs->iprxdat); + } + + return 0; +} + +int imxrt_sdram_init(struct udevice *dev) +{ + struct imxrt_sdram_params *params = dev_get_platdata(dev); + struct imxrt_sdram_mux *mux = params->sdram_mux; + struct imxrt_sdram_control *ctrl = params->sdram_control; + struct imxrt_sdram_timing *time = params->sdram_timing; + struct imxrt_semc_regs *regs = params->base; + struct bank_params *bank_params; + u32 rd; + int i; + + /* enable the SEMC controller */ + clrbits_le32(&regs->mcr, SEMC_MCR_MDIS); + /* set DQS mode from DQS pad */ + setbits_le32(&regs->mcr, SEMC_MCR_DQSMD); + + for (i = 0, bank_params = params->bank_params; + i < params->no_sdram_banks; bank_params++, + i++) + writel((bank_params->base_address & 0xfffff000) + | bank_params->memory_size << SEMC_BR_MS_SHIFT + | SEMC_BR_VLD_MASK, + &regs->br[bank_params->target_bank]); + + writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT + | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT + | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT + | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT + | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT + | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT, + &regs->iocr); + + writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT + | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT + | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT + | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT, + &regs->sdramcr0); + + writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT + | time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT + | time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT + | time->wrc << SEMC_SDRAMCR1_WRC_SHIFT + | time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT + | time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT, + &regs->sdramcr1); + + writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT + | time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT + | time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT + | time->ito << SEMC_SDRAMCR2_ITO_SHIFT, + &regs->sdramcr2); + + writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT + | time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT + | time->rt << SEMC_SDRAMCR3_RT_SHIFT + | time->ut << SEMC_SDRAMCR3_UT_SHIFT + | SEMC_SDRAMCR3_REN, + &regs->sdramcr3); + + writel(2, &regs->ipcr1); + + for (i = 0, bank_params = params->bank_params; + i < params->no_sdram_banks; bank_params++, + i++) { + mdelay(250); + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA, + 0, &rd); + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF, + 0, &rd); + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF, + 0, &rd); + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS, + ctrl->burst_len | (ctrl->cas_latency << 4), + &rd); + mdelay(250); + } + + return 0; +} + +static int imxrt_semc_ofdata_to_platdata(struct udevice *dev) +{ + struct imxrt_sdram_params *params = dev_get_platdata(dev); + ofnode bank_node; + u8 bank = 0; + + params->sdram_mux = + (struct imxrt_sdram_mux *) + dev_read_u8_array_ptr(dev, + "fsl,sdram-mux", + sizeof(struct imxrt_sdram_mux)); + if (!params->sdram_mux) { + pr_err("fsl,sdram-mux not found"); + return -EINVAL; + } + + params->sdram_control = + (struct imxrt_sdram_control *) + dev_read_u8_array_ptr(dev, + "fsl,sdram-control", + sizeof(struct imxrt_sdram_control)); + if (!params->sdram_control) { + pr_err("fsl,sdram-control not found"); + return -EINVAL; + } + + params->sdram_timing = + (struct imxrt_sdram_timing *) + dev_read_u8_array_ptr(dev, + "fsl,sdram-timing", + sizeof(struct imxrt_sdram_timing)); + if (!params->sdram_timing) { + pr_err("fsl,sdram-timing not found"); + return -EINVAL; + } + + dev_for_each_subnode(bank_node, dev) { + struct bank_params *bank_params; + char *bank_name; + int ret; + + /* extract the bank index from DT */ + bank_name = (char *)ofnode_get_name(bank_node); + strsep(&bank_name, "@"); + if (!bank_name) { + pr_err("missing sdram bank index"); + return -EINVAL; + } + + bank_params = &params->bank_params[bank]; + strict_strtoul(bank_name, 10, + (unsigned long *)&bank_params->target_bank); + if (bank_params->target_bank >= MAX_SDRAM_BANK) { + pr_err("Found bank %d , but only bank 0,1,2,3 are supported", + bank_params->target_bank); + return -EINVAL; + } + + ret = ofnode_read_u32(bank_node, + "fsl,memory-size", + &bank_params->memory_size); + if (ret < 0) { + pr_err("fsl,memory-size not found"); + return -EINVAL; + } + + ret = ofnode_read_u32(bank_node, + "fsl,base-address", + &bank_params->base_address); + if (ret < 0) { + pr_err("fsl,base-address not found"); + return -EINVAL; + } + + debug("Found bank %s %u\n", bank_name, + bank_params->target_bank); + bank++; + } + + params->no_sdram_banks = bank; + debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + + return 0; +} + +static int imxrt_semc_probe(struct udevice *dev) +{ + struct imxrt_sdram_params *params = dev_get_platdata(dev); + int ret; + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + params->base = (struct imxrt_semc_regs *)addr; + +#ifdef CONFIG_CLK + struct clk clk; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } +#endif + ret = imxrt_sdram_init(dev); + if (ret) + return ret; + + return 0; +} + +static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info) +{ + return 0; +} + +static struct ram_ops imxrt_semc_ops = { + .get_info = imxrt_semc_get_info, +}; + +static const struct udevice_id imxrt_semc_ids[] = { + { .compatible = "fsl,imxrt-semc", .data = 0 }, + { } +}; + +U_BOOT_DRIVER(imxrt_semc) = { + .name = "imxrt_semc", + .id = UCLASS_RAM, + .of_match = imxrt_semc_ids, + .ops = &imxrt_semc_ops, + .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata, + .probe = imxrt_semc_probe, + .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params), +}; diff --git a/include/dt-bindings/memory/imxrt-sdram.h b/include/dt-bindings/memory/imxrt-sdram.h new file mode 100644 index 0000000000..acb35bce27 --- /dev/null +++ b/include/dt-bindings/memory/imxrt-sdram.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti <giulio.benetti(a)benettiengineering.com> + */ + +#ifndef DT_BINDINGS_IMXRT_SDRAM_H +#define DT_BINDINGS_IMXRT_SDRAM_H + +#define MEM_SIZE_4K 0x00 +#define MEM_SIZE_8K 0x01 +#define MEM_SIZE_16K 0x02 +#define MEM_SIZE_32K 0x03 +#define MEM_SIZE_64K 0x04 +#define MEM_SIZE_128K 0x05 +#define MEM_SIZE_256K 0x06 +#define MEM_SIZE_512K 0x07 +#define MEM_SIZE_1M 0x08 +#define MEM_SIZE_2M 0x09 +#define MEM_SIZE_4M 0x0A +#define MEM_SIZE_8M 0x0B +#define MEM_SIZE_16M 0x0C +#define MEM_SIZE_32M 0x0D +#define MEM_SIZE_64M 0x0E +#define MEM_SIZE_128M 0x0F +#define MEM_SIZE_256M 0x10 +#define MEM_SIZE_512M 0x11 +#define MEM_SIZE_1G 0x12 +#define MEM_SIZE_2G 0x13 +#define MEM_SIZE_4G 0x14 + +#define MUX_A8_SDRAM_A8 0x0 +#define MUX_A8_NAND_CE 0x1 +#define MUX_A8_NOR_CE 0x2 +#define MUX_A8_PSRAM_CE 0x3 +#define MUX_A8_DBI_CSX 0x4 + +#define MUX_CSX0_NOR_PSRAM_A24 0x0 +#define MUX_CSX0_SDRAM_CS1 0x1 +#define MUX_CSX0_SDRAM_CS2 0x2 +#define MUX_CSX0_SDRAM_CS3 0x3 +#define MUX_CSX0_NAND_CE 0x4 +#define MUX_CSX0_NOR_CE 0x5 +#define MUX_CSX0_PSRAM_CE 0x6 +#define MUX_CSX0_DBI_CSX 0x7 + +#define MUX_CSX1_NOR_PSRAM_A25 0x0 +#define MUX_CSX1_SDRAM_CS1 0x1 +#define MUX_CSX1_SDRAM_CS2 0x2 +#define MUX_CSX1_SDRAM_CS3 0x3 +#define MUX_CSX1_NAND_CE 0x4 +#define MUX_CSX1_NOR_CE 0x5 +#define MUX_CSX1_PSRAM_CE 0x6 +#define MUX_CSX1_DBI_CSX 0x7 + +#define MUX_CSX2_NOR_PSRAM_A26 0x0 +#define MUX_CSX2_SDRAM_CS1 0x1 +#define MUX_CSX2_SDRAM_CS2 0x2 +#define MUX_CSX2_SDRAM_CS3 0x3 +#define MUX_CSX2_NAND_CE 0x4 +#define MUX_CSX2_NOR_CE 0x5 +#define MUX_CSX2_PSRAM_CE 0x6 +#define MUX_CSX2_DBI_CSX 0x7 + +#define MUX_CSX3_NOR_PSRAM_A27 0x0 +#define MUX_CSX3_SDRAM_CS1 0x1 +#define MUX_CSX3_SDRAM_CS2 0x2 +#define MUX_CSX3_SDRAM_CS3 0x3 +#define MUX_CSX3_NAND_CE 0x4 +#define MUX_CSX3_NOR_CE 0x5 +#define MUX_CSX3_PSRAM_CE 0x6 +#define MUX_CSX3_DBI_CSX 0x7 + +#define MUX_RDY_NAND_RDY_WAIT 0x0 +#define MUX_RDY_SDRAM_CS1 0x1 +#define MUX_RDY_SDRAM_CS2 0x2 +#define MUX_RDY_SDRAM_CS3 0x3 +#define MUX_RDY_NOR_CE 0x4 +#define MUX_RDY_PSRAM_CE 0x5 +#define MUX_RDY_DBI_CSX 0x6 +#define MUX_RDY_NOR_PSRAM_A27 0x7 + +#define MEM_WIDTH_8BITS 0x0 +#define MEM_WIDTH_16BITS 0x1 + +#define BL_1 0x0 +#define BL_2 0x1 +#define BL_4 0x2 +#define BL_8 0x3 + +#define COL_12BITS 0x0 +#define COL_11BITS 0x1 +#define COL_10BITS 0x2 +#define COL_9BITS 0x3 + +#define CL_1 0x0 +#define CL_2 0x2 +#define CL_3 0x3 + +#endif -- 2.20.1

1 4

What is the difference between ARCH_XXX MACH_XXX TARGET_XXX macros
by Tim Williams 04 Dec '19

04 Dec '19

Hello, I am trying to port u-boot to a new board, There are several macros, how to use them properly? CONFIG_ARCH_XXX CONFIG_MACH_XXX CONFIG_TARGET_XXX for example, my board has: SoC: LS2K1000 ISA: MIPS32r1, MIPS32r2, MIPS64r1, MIPS64r2 Board: UselessRouter or HelloRouter, TBD NIC: 4 1000Mbps NIC(No built in switcher) thanks very much! Regards, Tim

2 1

[U-Boot] [PATCH] arm64: zynqmp: Point zcu216 defconfig to correct dts file
by Michal Simek 04 Dec '19

04 Dec '19

Defconfig is pointing to incorrect DT file which needs to be fix. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/xilinx_zynqmp_zcu216_revA_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/xilinx_zynqmp_zcu216_revA_defconfig b/configs/xilinx_zynqmp_zcu216_revA_defconfig index ccc5303c2f83..74a8eec40cbd 100644 --- a/configs/xilinx_zynqmp_zcu216_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu216_revA_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu216-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y -- 2.17.1

2 1