December 2019 - U-Boot

Re: [PATCH 3/4] riscv: add option to wait for ack from secondary harts in smp functions
by Rick Chen 06 Dec '19

06 Dec '19

Hi Lukas, > From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > Sent: Wednesday, December 04, 2019 5:40 AM > To: u-boot(a)lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas Auer; Anup Patel; Atish Patra; Marcus Comstedt > Subject: [PATCH 3/4] riscv: add option to wait for ack from secondary harts in smp functions > > Add a wait option to smp_call_function() to wait for the secondary harts to acknowledge the call-function request. The request is considered to be acknowledged once each secondary hart has cleared the corresponding IPI. > > As part of the call-function request, the secondary harts invalidate the instruction cache after clearing the IPI. This adds a delay between acknowledgment (clear IPI) and fulfillment (call function) of the request. We want to use the acknowledgment to be able to judge when the request has been completed. Remove the delay by clearing the IPI after cache invalidation and just before calling the function from the request. > > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > --- > Reviewed-by: Rick Chen <rick(a)andestech.com> Tested-by: Rick Chen <rick(a)andestech.com> > arch/riscv/cpu/start.S | 2 ++ > arch/riscv/include/asm/smp.h | 3 ++- > arch/riscv/lib/bootm.c | 2 +- > arch/riscv/lib/smp.c | 31 ++++++++++++++++++++++--------- > arch/riscv/lib/spl.c | 2 +- > common/spl/spl_opensbi.c | 2 +- > 6 files changed, 29 insertions(+), 13 deletions(-) > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 0a2ce6d691..60631638dd 100644 > --- a/arch/riscv/cpu/start.S > +++ b/arch/riscv/cpu/start.S > @@ -197,6 +197,7 @@ spl_secondary_hart_stack_gd_setup: > la a0, secondary_hart_relocate > mv a1, s0 > mv a2, s0 > + mv a3, zero > jal smp_call_function > > /* hang if relocation of secondary harts has failed */ @@ -337,6 +338,7 @@ relocate_secondary_harts: > > mv a1, s2 > mv a2, s3 > + mv a3, zero > jal smp_call_function > > /* hang if relocation of secondary harts has failed */ diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index bc863fdbaf..74de92ed13 100644 > --- a/arch/riscv/include/asm/smp.h > +++ b/arch/riscv/include/asm/smp.h > @@ -46,8 +46,9 @@ void handle_ipi(ulong hart); > * @addr: Address of function > * @arg0: First argument of function > * @arg1: Second argument of function > + * @wait: Wait for harts to acknowledge request > * @return 0 if OK, -ve on error > */ > -int smp_call_function(ulong addr, ulong arg0, ulong arg1); > +int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait); > > #endif > diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index efbd3e23e7..e96137a50c 100644 > --- a/arch/riscv/lib/bootm.c > +++ b/arch/riscv/lib/bootm.c > @@ -99,7 +99,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) > if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { #ifdef CONFIG_SMP > ret = smp_call_function(images->ep, > - (ulong)images->ft_addr, 0); > + (ulong)images->ft_addr, 0, 0); > if (ret) > hang(); > #endif > diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index 6ff0de4b74..d575e904c2 100644 > --- a/arch/riscv/lib/smp.c > +++ b/arch/riscv/lib/smp.c > @@ -43,11 +43,11 @@ extern int riscv_clear_ipi(int hart); > */ > extern int riscv_get_ipi(int hart, int *pending); > > -static int send_ipi_many(struct ipi_data *ipi) > +static int send_ipi_many(struct ipi_data *ipi, int wait) > { > ofnode node, cpus; > u32 reg; > - int ret; > + int ret, pending; > > cpus = ofnode_path("/cpus"); > if (!ofnode_valid(cpus)) { > @@ -90,6 +90,15 @@ static int send_ipi_many(struct ipi_data *ipi) > pr_err("Cannot send IPI to hart %d\n", reg); > return ret; > } > + > + if (wait) { > + pending = 1; > + while (pending) { > + ret = riscv_get_ipi(reg, &pending); > + if (ret) > + return ret; > + } > + } > } > > return 0; > @@ -103,21 +112,25 @@ void handle_ipi(ulong hart) > if (hart >= CONFIG_NR_CPUS) > return; > > + __smp_mb(); > + > + smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr; > + invalidate_icache_all(); > + > + /* > + * Clear the IPI to acknowledge the request before jumping to the > + * requested function. > + */ > ret = riscv_clear_ipi(hart); > if (ret) { > pr_err("Cannot clear IPI of hart %ld\n", hart); > return; > } > > - __smp_mb(); > - > - smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr; > - invalidate_icache_all(); > - > smp_function(hart, gd->arch.ipi[hart].arg0, gd->arch.ipi[hart].arg1); } > > -int smp_call_function(ulong addr, ulong arg0, ulong arg1) > +int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait) > { > int ret = 0; > struct ipi_data ipi; > @@ -126,7 +139,7 @@ int smp_call_function(ulong addr, ulong arg0, ulong arg1) > ipi.arg0 = arg0; > ipi.arg1 = arg1; > > - ret = send_ipi_many(&ipi); > + ret = send_ipi_many(&ipi, wait); > > return ret; > } > diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index bea8695987..fd3c2efc5b 100644 > --- a/arch/riscv/lib/spl.c > +++ b/arch/riscv/lib/spl.c > @@ -40,7 +40,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) > > debug("image entry point: 0x%lX\n", spl_image->entry_point); #ifdef CONFIG_SMP > - ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0); > + ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0, > +0); > if (ret) > hang(); > #endif > diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 79ee7edcf9..91a411a3db 100644 > --- a/common/spl/spl_opensbi.c > +++ b/common/spl/spl_opensbi.c > @@ -77,7 +77,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) #ifdef CONFIG_SMP > ret = smp_call_function((ulong)spl_image->entry_point, > (ulong)spl_image->fdt_addr, > - (ulong)&opensbi_info); > + (ulong)&opensbi_info, 0); > if (ret) > hang(); > #endif > -- > 2.21.0 >

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Re: [PATCH 1/4] spl: opensbi: specify main hart as preferred boot hart
by Rick Chen 06 Dec '19

06 Dec '19

> From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > Sent: Wednesday, December 04, 2019 5:40 AM > To: u-boot(a)lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas Auer; Anup Patel > Subject: [PATCH 1/4] spl: opensbi: specify main hart as preferred boot hart > > OpenSBI uses a relocation lottery to determine the hart to relocate OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart schedules the secondary harts to enter OpenSBI before doing so itself. > One of the secondary harts will therefore always be the winner of the relocation lottery. This is problematic if the link address ranges of OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore overwrite U-Boot SPL while some harts may still run it, leading to code corruption. > > Avoid this problem by specifying the main hart as the preferred boot hart to perform the OpenSBI relocation. The main hart will be the last hart to enter OpenSBI, relocation can therefore occur safely. > > The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC info structure. The header file include/opensbi.h is synchronized with include/sbi/fw_dynamic.h from the OpenSBI project to update the info structure. The header file is recent as of commit > 7a13beb21326 ("firmware: Add preferred boot HART field in struct fw_dynamic_info"). > > Reported-by: Rick Chen <rick(a)andestech.com> > Suggested-by: Anup Patel <Anup.Patel(a)wdc.com> > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > --- > Reviewed-by: Rick Chen <rick(a)andestech.com> Tested-by: Rick Chen <rick(a)andestech.com> > common/spl/spl_opensbi.c | 1 + > include/opensbi.h | 18 +++++++++++++++++- > 2 files changed, 18 insertions(+), 1 deletion(-) > > diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index a6b4480ed2..79ee7edcf9 100644 > --- a/common/spl/spl_opensbi.c > +++ b/common/spl/spl_opensbi.c > @@ -69,6 +69,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) > opensbi_info.next_addr = uboot_entry; > opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S; > opensbi_info.options = SBI_SCRATCH_NO_BOOT_PRINTS; > + opensbi_info.boot_hart = gd->arch.boot_hart; > > opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point; > invalidate_icache_all(); > diff --git a/include/opensbi.h b/include/opensbi.h index 9f1d62e7dd..d812cc8ccd 100644 > --- a/include/opensbi.h > +++ b/include/opensbi.h > @@ -11,7 +11,7 @@ > #define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f > > /** Maximum supported info version */ > -#define FW_DYNAMIC_INFO_VERSION 0x1 > +#define FW_DYNAMIC_INFO_VERSION 0x2 > > /** Possible next mode values */ > #define FW_DYNAMIC_INFO_NEXT_MODE_U 0x0 > @@ -35,6 +35,22 @@ struct fw_dynamic_info { > unsigned long next_mode; > /** Options for OpenSBI library */ > unsigned long options; > + /** > + * Preferred boot HART id > + * > + * It is possible that the previous booting stage uses same link > + * address as the FW_DYNAMIC firmware. In this case, the relocation > + * lottery mechanism can potentially overwrite the previous booting > + * stage while other HARTs are still running in the previous booting > + * stage leading to boot-time crash. To avoid this boot-time crash, > + * the previous booting stage can specify last HART that will jump > + * to the FW_DYNAMIC firmware as the preferred boot HART. > + * > + * To avoid specifying a preferred boot HART, the previous booting > + * stage can set it to -1UL which will force the FW_DYNAMIC firmware > + * to use the relocation lottery mechanism. > + */ > + unsigned long boot_hart; > } __packed; > > #endif > -- > 2.21.0 >

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[PATCH 0/2] travis-ci: provide 'addr' in file2env()
by Heinrich Schuchardt 06 Dec '19

06 Dec '19

Function fetch_tftp_file() in test/py/tests/test_efi_loader.py expects that the dictionary describing a file contains an entry 'addr' specifying the loading address. Otherwise it defaults to the start of RAM. On qemu_arm64_defconfig and qemu_arm_defconfig this collides with the hardware supplied device tree. Add an optional parameter in function file2env() to set the 'addr' entry. Set the load address for files to the value of $kernel_addr_r for the qemu_arm64_defconfig and qemu_arm_defconfig boards to avoid collisions with the device tree. Heinrich Schuchardt (2): travis-ci: provide 'addr' in file2env() travis-ci: set load address for files py/travis-ci/travis_tftp.py | 18 ++++++++++++++++-- py/travis-ci/u_boot_boardenv_qemu_arm64_na.py | 6 +++--- py/travis-ci/u_boot_boardenv_qemu_arm_na.py | 6 +++--- 3 files changed, 22 insertions(+), 8 deletions(-) -- 2.24.0

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[U-Boot] Maximum size of u-boot.imx for TBS2910 board
by Heinrich Schuchardt 06 Dec '19

06 Dec '19

Hello Soeren, when trying to add support for function key support in the USB keyboard driver u-boot.imx for the TBS2910 surpassed the maximum size for u-boot.imx. https://travis-ci.org/marex/u-boot-usb/builds/614059004 Do you remember why on the TBS2910 board this size is limited to 0x5fc00? Other i.MX6 boards like the Wandboard allow a much larger u-boot.imx. The limit is defined here: include/configs/tbs2910.h:80: #define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */ Could the value CONFIG_ENV_OFFSET=0x60000 be enlarged? Many i.MX6 defconfigs use CONFIG_ENV_OFFSET=0xC0000. Best regards Heinrich

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[PATCH v1] colibri_imx6: fix broken fsl_esdhc_imx conversion
by Igor Opaniuk 06 Dec '19

06 Dec '19

From: Igor Opaniuk <igor.opaniuk(a)toradex.com> Not all CONFIG_FSL_ESDHC defines were properly replaced with CONFIG_FSL_ESDHC_IMX, which broke U-boot proper booting on Colibri iMX6 SoMs. U-boot is stuck after this message: Commercial temperature grade DDR3 timings, 64bit bus width. Trying to boot from MMC1 Fixes: e37ac717d7("Convert to use fsl_esdhc_imx for i.MX platforms") Signed-off-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> --- board/toradex/colibri_imx6/colibri_imx6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index ad40b589c1..44173dde1f 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -83,7 +83,7 @@ iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) /* Colibri MMC */ iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -304,7 +304,7 @@ int board_ehci_hcd_init(int port) } #endif -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) /* use the following sequence: eMMC, MMC */ struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, -- 2.17.1

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[PATCH] rockchip: px30: Change RK809 PMIC interrupt polarity
by Miquel Raynal 06 Dec '19

06 Dec '19

PMIC interrupt can be active high or active low depending on BIT(1) of the GPIO_INT_CFG pin. The default is 0x1, which means active high. Change the polarity in the device tree to reflect the default state. This change does not impact U-Boot directly as there are no interrupts at this stage but it keeps the device tree synced with Linux. Signed-off-by: Miquel Raynal <miquel.raynal(a)bootlin.com> --- arch/arm/dts/px30-evb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts index 53ab8bc7db..b1a4f72152 100644 --- a/arch/arm/dts/px30-evb.dts +++ b/arch/arm/dts/px30-evb.dts @@ -179,7 +179,7 @@ compatible = "rockchip,rk809"; reg = <0x20>; interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pmic_int>; rockchip,system-power-controller; -- 2.20.1

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[U-Boot] [PATCH] Add -pthread to HOSTLOADLIBES_mkimage
by Benedikt-Alexander Mokroß 06 Dec '19

06 Dec '19

On some unix distributions, pthread is not automatically linked. This results in unresolved symbols when e.g. building u-boot via OpenWRT (using LibreSSL) in dumpimage and other host tools when i.E. CONFIG_FIT_SIGNATURE is set. Using -pthread to link pthread should be portable across all distributions and OS X. CHANGELOG: * Added -pthread to HOSTLOADLIBES_mkimage --- tools/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index 24581adccd..2f122bed8e 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -150,7 +150,8 @@ ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CON HOSTCFLAGS_kwbimage.o += \ $(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "") HOSTLOADLIBES_mkimage += \ -$(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl -lcrypto") +$(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl -lcrypto") \ +-pthread # OS X deprecate openssl in favour of CommonCrypto, supress deprecation # warnings on those systems -- 2.20.1 Benedikt-Alexander Mokroß Head of Research iCOGNIZE GmbH Tel.: +49 (0)60 74 - 310 36 31 Email: benedikt-alexander.mokross(a)iCOGNIZE.de ________________________________ [iCOGNIZE]<https://www.icognize.de> iCOGNIZE GmbH Justus-von-Liebig-Straße 9 63128 Dietzenbach (Germany) Tel.: +49 (0)6074 3103600 Fax: +49 (0)6074 3103640 Web: www.iCOGNIZE.de<https://www.icognize.de> Geschäftsführer/Board: Dr. Alexander W. Lenhardt USt.-ID.: DE 814 952 849, Registergericht: Amtsgericht Offenbach a. M., HRB 43145 ________________________________ WICHTIGER HINWEIS: Die in dieser E-Mail und in den dazugehoerigen Anhaengen enthaltenen Informationen (die "Nachricht") sind nur fuer den Adressaten bestimmt und koennen vertrauliche und/oder rechtlich geschuetzte Angaben enthalten. Falls Sie nicht der Adressat sind, loeschen Sie bitte diese Nachricht und benachrichtigen Sie den Absender; Sie duerfen diese Nachricht nicht kopieren, verteilen oder ihren Inhalt an andere Personen weitergeben. Die in dieser E-Mail geaeusserten Ansichten spiegeln lediglich die Meinung des Autors wider und stellen nicht notwendigerweise die Meinung der iCOGNIZE GmbH dar. Diese Nachricht ist nicht rechtsverbindlich, wenn Sie keine schriftliche Bestaetigung ihres Inhalts durch einen autorisierten Vertreter erhalten. Wir schliessen ausser fuer den Fall von Vorsatz oder grober Fahrlaessigkeit die Haftung fuer jeglichen Verlust oder Schaeden durch virenbefallene Software oder E-Mails aus. Danke. IMPORTANT NOTICE: This message is intended only for the use of the individual or entity to which it is addressed, and may contain information that is privileged, confidential and exempt from disclosure under applicable law. If the reader of this message is not the intended recipient, or the employee or agent responsible for delivering the message to the intended recipient, you are hereby notified that any dissemination, distribution or copying of this communication is strictly prohibited. If you have received this communication in error, please notify the sender immediately by email and delete this message. Thank you.

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Sourcing a signed boot script
by Diego Rondini 06 Dec '19

06 Dec '19

Hi, I would like to ask if it is possible to source a script after verifying its signature. Currently I've been able to source a script from a signed FIT image, before doing "bootm", with: source <addr>:<name> But this way the signature is not checked yet, so the script cannot be trusted. According to the docs[1] it seems that it's not possible yet to verify a FIT image signature without also booting the corresponding image. Is that right? [1] https://gitlab.denx.de/u-boot/u-boot/blob/v2019.10/doc/uImage.FIT/signature… Thank you, Diego Rondini

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[U-Boot] [PATCH] clk: imx: imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
by Schrempf Frieder 06 Dec '19

06 Dec '19

From: Frieder Schrempf <frieder.schrempf(a)kontron.de> The 24MHz oscillator clock is referenced by "clock-osc-24m" and not "osc_24m". Signed-off-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> --- drivers/clk/imx/clk-imx8mm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 091b092bbb..a05dac7c7a 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -74,7 +74,7 @@ static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; -static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", +static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", -- 2.17.1

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Re: [PATCH 2/4] riscv: add functions for reading the IPI status
by Rick Chen 06 Dec '19

06 Dec '19

Hi Lukas > From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > Sent: Wednesday, December 04, 2019 5:40 AM > To: u-boot(a)lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas Auer; Anup Patel; Atish Patra > Subject: [PATCH 2/4] riscv: add functions for reading the IPI status > > Add the function riscv_get_ipi() for reading the pending status of IPIs. > The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). > > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > --- > I do not have access to the datasheet of the Andes PLIC. The > riscv_clear_ipi() implementation seems to read the IPI status from the claim register before writing back the results to clear them. Based on this, I also used the claim register. Rick, please let me know if that is ok or if I should use the pending register instead. Yes. Please use pending register instead of claim register. Thanks Rick > > arch/riscv/lib/andes_plic.c | 9 +++++++++ > arch/riscv/lib/sbi_ipi.c | 11 +++++++++++ > arch/riscv/lib/sifive_clint.c | 9 +++++++++ > arch/riscv/lib/smp.c | 12 ++++++++++++ > 4 files changed, 41 insertions(+) > > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 28568e4e2b..731ac3a148 100644 > --- a/arch/riscv/lib/andes_plic.c > +++ b/arch/riscv/lib/andes_plic.c > @@ -114,6 +114,15 @@ int riscv_clear_ipi(int hart) > return 0; > } > > +int riscv_get_ipi(int hart, int *pending) { > + PLIC_BASE_GET(); > + > + *pending = !!readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); > + > + return 0; > +} > + > static const struct udevice_id andes_plic_ids[] = { > { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC }, > { } > diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c index 170346da68..9a698ce74e 100644 > --- a/arch/riscv/lib/sbi_ipi.c > +++ b/arch/riscv/lib/sbi_ipi.c > @@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart) > > return 0; > } > + > +int riscv_get_ipi(int hart, int *pending) { > + /* > + * The SBI does not support reading the IPI status. We always return 0 > + * to indicate that no IPI is pending. > + */ > + *pending = 0; > + > + return 0; > +} > diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index d24e0d585b..d7899d16d7 100644 > --- a/arch/riscv/lib/sifive_clint.c > +++ b/arch/riscv/lib/sifive_clint.c > @@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart) > return 0; > } > > +int riscv_get_ipi(int hart, int *pending) { > + CLINT_BASE_GET(); > + > + *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); > + > + return 0; > +} > + > static const struct udevice_id sifive_clint_ids[] = { > { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT }, > { } > diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index cc66f15567..6ff0de4b74 100644 > --- a/arch/riscv/lib/smp.c > +++ b/arch/riscv/lib/smp.c > @@ -31,6 +31,18 @@ extern int riscv_send_ipi(int hart); > */ > extern int riscv_clear_ipi(int hart); > > +/** > + * riscv_get_ipi() - Get status of inter-processor interrupt (IPI) > + * > + * Platform code must provide this function. > + * > + * @hart: Hart ID of hart to be checked > + * @pending: Pointer to variable with result of the check, > + * 1 if IPI is pending, 0 otherwise > + * @return 0 if OK, -ve on error > + */ > +extern int riscv_get_ipi(int hart, int *pending); > + > static int send_ipi_many(struct ipi_data *ipi) { > ofnode node, cpus; > -- > 2.21.0 >

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