November 2019 - U-Boot

[U-Boot] [PATCH v2] configs: spi: Add the SPI_FLASH_BAR for ESPI
by Xiaowei Bao 11 Nov '19

11 Nov '19

Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry is missed by commit 6d825178364. Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- v2: - Modify the commit message. drivers/spi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8dd3213..77731af 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -367,6 +367,7 @@ config CF_SPI config FSL_ESPI bool "Freescale eSPI driver" + imply SPI_FLASH_BAR help Enable the Freescale eSPI driver. This driver can be used to access the SPI interface and SPI NOR flash on platforms embedding -- 2.9.5

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[U-Boot] [PATCH v2] armv8: fsl-layerscape: fix warning if no hwconfig is defined
by Pankaj Bansal 11 Nov '19

11 Nov '19

if no hwconfig variable is defined for a platform and we try to get the subarg of hwconfig, we receive a warning: WARNING: Calling __hwconfig without a buffer and before environment is ready Therefore, if hwconfig is not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> --- Notes: V2: - Add copyright year in file that has been updated arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 8fd6c751c6..b42beca6e1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -1072,6 +1072,8 @@ static void config_core_prefetch(void) if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; + else + return; prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable", &arglen, buf); -- 2.17.1

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[U-Boot] [PATCH 1/2] drivers: net: fsl_enetc: set phydev->node
by Michael Walle 11 Nov '19

11 Nov '19

The saved ofnode is used by some PHY drivers to access the device tree node of the PHY. Signed-off-by: Michael Walle <michael(a)walle.cc> --- drivers/net/fsl_enetc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index e7c5062c39..86b80c8941 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -248,6 +248,7 @@ static void enetc_start_phy(struct udevice *dev) supported = GENMASK(6, 0); /* speeds up to 1G & AN */ phy->advertising = phy->supported & supported; + phy->node = phy_node; phy_config(phy); phy_startup(phy); } -- 2.20.1

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[U-Boot] [PATCH] armv8: fsl-layerscape: introduce fsl_board_late_init()
by Michael Walle 11 Nov '19

11 Nov '19

The fsl-layerscape already occupies board_late_init(), therefore it is not possible for a board to have its own board_late_init(). Introduce fsl_board_late_init() which can be implemented in the board specific code. Signed-off-by: Michael Walle <michael(a)walle.cc> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 3fd34e3a43..7a9f9df9e8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -819,6 +819,11 @@ int fsl_setenv_mcinitcmd(void) #endif #ifdef CONFIG_BOARD_LATE_INIT +__weak int fsl_board_late_init(void) +{ + return 0; +} + int board_late_init(void) { #ifdef CONFIG_CHAIN_OF_TRUST @@ -853,6 +858,6 @@ int board_late_init(void) qspi_ahb_init(); #endif - return 0; + return fsl_board_late_init(); } #endif -- 2.20.1

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[U-Boot] [PATCH] armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x
by Michael Walle 11 Nov '19

11 Nov '19

The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael(a)walle.cc> --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index b3e67321b4..bbd550b036 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -64,7 +64,7 @@ void get_sys_info(struct sys_info *sys_info) }; uint i, cluster; -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) uint rcw_tmp; #endif uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -131,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) CONFIG_SYS_FSL_IFC_CLK_DIV; #endif -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) #define HWA_CGA_M2_CLK_SEL 0x00380000 #define HWA_CGA_M2_CLK_SHIFT 19 rcw_tmp = in_le32(&gur->rcwsr[5]); @@ -159,7 +159,7 @@ void get_sys_info(struct sys_info *sys_info) break; } #endif -#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) sys_info->freq_cga_m2 = sys_info->freq_systembus; #endif } @@ -176,10 +176,10 @@ int get_clocks(void) #endif #if defined(CONFIG_FSL_ESDHC) #if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; #endif -#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) gd->arch.sdhc_clk = sys_info.freq_cga_m2; #endif #else -- 2.20.1

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[U-Boot] Add support for imxrt
by Giulio Benetti 11 Nov '19

11 Nov '19

Hello everybody, I would like to port imxrt to u-boot and I would like to ask you: - do you have the interest on upstreaming it? if yes: I've seen how they've dealt with 'stm32' and 'stm32mp' that is similar to 'imxrt' and 'imx'. So should follow the same criterias for porting? I mean adding the new folder 'mach-imxrt'? Also, do I find some of you in IRC sometimes? Thanks in advance Best regards -- Giulio Benetti Benetti Engineering sas

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[U-Boot] [PATCH v3 1/2] riscv: dts: Add hifive-unleashed-a00 dts from Linux
by Jagan Teki 11 Nov '19

11 Nov '19

Sync the hifive-unleashed-a00 dts from Linux with below commit details: commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive Unleashed: add default chosen/stdout-path") Idea is to periodically sync the dts from Linux instead of tweaking internal changes one after another, so better not add any intermediate changes in between. This would help to maintain the dts files easy and meaningful since we are reusing device tree files from Linux. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v3: - none arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu540-c000.dtsi | 251 ++++++++++++++++++++++++ arch/riscv/dts/hifive-unleashed-a00.dts | 96 +++++++++ 3 files changed, 348 insertions(+) create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f9cd606a9a..4f30e6936f 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi new file mode 100644 index 0000000000..afa43c7ea3 --- /dev/null +++ b/arch/riscv/dts/fu540-c000.dtsi @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include <dt-bindings/clock/sifive-fu540-prci.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = &eth0; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci PRCI_CLK_TLCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm0: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <42 43 44 45>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm@10021000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10021000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <46 47 48 49>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + + }; +}; diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..88cfcb96bf --- /dev/null +++ b/arch/riscv/dts/hifive-unleashed-a00.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <RTCCLK_FREQ>; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +&eth0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines
by Laurentiu Tudor 11 Nov '19

11 Nov '19

From: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> These macros should only be used when CONFIG_FSL_CAAM is present. Signed-off-by: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> Reviewed-by: Horia Geant?? <horia.geanta(a)nxp.com> --- Changes in v2: - added Reviewed-by tag arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++ arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index d9d125e8ba..9462298fbf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = { SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID), SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID), SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID), +#ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = { SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), +#endif }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c index 49e27553b1..23743ae10c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = { SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID), +#ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = { SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), +#endif }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -- 2.17.1

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[U-Boot] [PATCH 0/2] armv8: fsl-layerscape: Allow use of PSCI handlers for ls1088a
by Mathew McBride 11 Nov '19

11 Nov '19

This patch allows the use of PSCI for power operations - this is desirable if the target board has implemented it's own power operation handlers in Trusted Firmware/EL3. Layerscape has it's own EFI service handlers for power operations - if PSCI is used the generic handlers will be used instead. Note that all of the existing Layerscape boards in-tree are blacklisted from PSCI_RESET by default - to use this you must enable it for your board. Mathew McBride (2): armv8: dts: ls1088a: add PSCI binding for LS1088A armv8: fsl-layerscape: do not use layerscape EFI reset if PSCI used arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- arch/arm/dts/fsl-ls1088a.dtsi | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) -- 2.19.1

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[U-Boot] [PATCH] pci: layerscape: Only set EP CFG READY bit
by Pankaj Bansal 11 Nov '19

11 Nov '19

As part of EP setup, we want to set the config ready bit of controller, so that RC can read the config space of EP. Now, when we set the config ready bit we are inadvertently clearing the LTSSM_EN bit in same register, which restarts the link tarining between RC and EP. Therefore, just set the desired CFG_READY bit (bit 0), while leaving the other bits unchanged. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> --- drivers/pci/pcie_layerscape.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index d8a7b7c865..bb2ec7c2ce 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -407,7 +407,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base) static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) { - ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG); + u32 config; + + config = ctrl_readl(pcie, PCIE_PF_CONFIG); + config |= PCIE_CONFIG_READY; + ctrl_writel(pcie, config, PCIE_PF_CONFIG); } static void ls_pcie_setup_ep(struct ls_pcie *pcie) -- 2.17.1

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