November 2019 - U-Boot

[U-Boot] [PATCH] Makefile: Only build dtc if needed
by Simon Glass 28 Apr '20

28 Apr '20

At present U-Boot always builds dtc if CONFIG_OF_CONTROL is defined. This is wasteful when the system already has a suitable version available. Update the Makefile logic to build dtc only if the version available is too old. This saves about 3 seconds of CPU time on a clean build for me. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Makefile | 17 +++++++++++++++-- dts/Kconfig | 4 ---- scripts/Kbuild.include | 4 +++- scripts/Makefile | 1 - scripts/dtc-version.sh | 25 ++++++++++++++++++++----- 5 files changed, 38 insertions(+), 13 deletions(-) diff --git a/Makefile b/Makefile index 250eb6c3c39..fec2b2d8fb5 100644 --- a/Makefile +++ b/Makefile @@ -361,7 +361,12 @@ PERL = perl PYTHON ?= python PYTHON2 = python2 PYTHON3 = python3 -DTC ?= $(objtree)/scripts/dtc/dtc + +# DTC is automatically built if the version of $(DTC) is older that needed. +# Use the system dtc if it is new enough. +DTC ?= dtc +DTC_MIN_VERSION := 010406 + CHECK = sparse CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ @@ -926,7 +931,7 @@ endif PHONY += dtbs dtbs: dts/dt.dtb @: -dts/dt.dtb: u-boot +dts/dt.dtb: checkdtc u-boot $(Q)$(MAKE) $(build)=dts dtbs quiet_cmd_copy = COPY $@ @@ -1579,6 +1584,14 @@ SYSTEM_MAP = \ System.map: u-boot @$(call SYSTEM_MAP,$<) > $@ +build_dtc := $(objtree)/scripts/dtc/dtc + +checkdtc: + $(eval DTC := $(call dtc-version,010406,$(build_dtc))) + if test "$(DTC)" = "$(build_dtc)"; then \ + $(MAKE) $(build)=scripts/dtc; \ + fi + ######################################################################### # ARM relocations should all be R_ARM_RELATIVE (32-bit) or diff --git a/dts/Kconfig b/dts/Kconfig index 8917f424445..7e600e28f6c 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -5,9 +5,6 @@ config SUPPORT_OF_CONTROL bool -config DTC - bool - config PYLIBFDT bool @@ -24,7 +21,6 @@ menu "Device Tree Control" config OF_CONTROL bool "Run-time configuration via Device Tree" - select DTC help This feature provides for run-time configuration of U-Boot via a flattened device tree. diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index 13ebddda65c..82be40cbe78 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -147,8 +147,10 @@ cc-fullversion = $(shell $(CONFIG_SHELL) \ cc-ifversion = $(shell [ $(cc-version) $(1) $(2) ] && echo $(3) || echo $(4)) # added for U-Boot +# $1: min_version +# #2: build_dtc binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS)) -dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC)) +dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC) $1 $2) # cc-ldoption # Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both) diff --git a/scripts/Makefile b/scripts/Makefile index e7b353f77f4..cfe9fef8044 100644 --- a/scripts/Makefile +++ b/scripts/Makefile @@ -10,4 +10,3 @@ always := $(hostprogs-y) # Let clean descend into subdirs subdir- += basic kconfig -subdir-$(CONFIG_DTC) += dtc diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh index 0744c39eb04..ec988e18daf 100755 --- a/scripts/dtc-version.sh +++ b/scripts/dtc-version.sh @@ -1,12 +1,22 @@ #!/bin/sh # -# dtc-version dtc-command +# dtc-version dtc_command min_version build_dtc # -# Prints the dtc version of `dtc-command' in a canonical 6-digit form -# such as `010404' for dtc 1.4.4 +# Selects which version of dtc to use +# +# If the version of dtc_command is < min_version, prints build_dtc else +# prints dtc_command. The min_version is in the format MMmmpp where: +# +# MM is the major version +# mm is the minor version +# pp is the patch level +# +# For example 010406 means 1.4.6 # -dtc="$*" +dtc="$1" +min_version="$2" +build_dtc="$3" if [ ${#dtc} -eq 0 ]; then echo "Error: No dtc command specified." @@ -18,4 +28,9 @@ MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1) MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2) PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1) -printf "%02d%02d%02d\\n" $MAJOR $MINOR $PATCH +version="$(printf "%02d%02d%02d" $MAJOR $MINOR $PATCH)" +if test $version -lt $min_version; then \ + echo $build_dtc +else + echo $dtc +fi -- 2.19.1.930.g4563a0d9d0-goog

3 7

[U-Boot] [PATCH v2 0/5] riscv: sifive/fu540: Enable SPI-NOR support
by Jagan Teki 18 Apr '20

18 Apr '20

This is v2 patchset, enable SPI-NOR flash on SiFive hifive-unleashed-a00 board, here is v1 [1]. Changes for v2: - use latest sifive commit from linux-next - fix typos in commit message - rebased on master patch 0001 - 02: support devicetree patch 0003: add is25wp256 chip patch 0004 - 05: enable spi-nor flash All tested in Sifive fuse540 hifive-unleashed-a00 board. [1] https://patchwork.ozlabs.org/cover/1168959/ Any inputs? Jagan. Jagan Teki (5): riscv: dts: Add hifive-unleashed-a00 dts from Linux sifive: fu540: Enable OF_SEPARATE mtd: spi-nor: ids: Add is25wp256 chip riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi sifive: fu540: Enable spi-nor flash support arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu540-c000.dtsi | 251 ++++++++++++++++++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 11 + arch/riscv/dts/hifive-unleashed-a00.dts | 96 +++++++ board/sifive/fu540/Kconfig | 3 + configs/sifive_fu540_defconfig | 3 +- doc/board/sifive/fu540.rst | 21 +- drivers/mtd/spi/spi-nor-ids.c | 2 + 8 files changed, 386 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts -- 2.18.0.321.gffc6fa0e3

3 27

[U-Boot] [PATCH v2] imx: Introduce CONFIG_SPL_FORCE_MMC_BOOT to force MMC boot on falcon mode
by Lukasz Majewski 08 Apr '20

08 Apr '20

This change tries to fix the following problem: - The board boots (to be more precise - ROM loads SPL) from a slow SPI-NOR memory. As a result the spl_boot_device() will return SPI-NOR as a boot device (which is correct). - The problem is that in 'falcon boot' the eMMC is used as a boot medium to load kernel from its partition. Calling spl_boot_device() will break things as it returns SPI-NOR device. To fix this issue the new CONFIG_SPL_FORCE_MMC_BOOT Kconfig flag is introduced to handle this special use case. By default it is not defined, so there is no change in the legacy code flow. Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- Changes in v2: - Update/enhance the Kconfig description of the SPL_FORCE_MMC_BOOT. This patch is a follow up of previous discussion/fix: https://patchwork.ozlabs.org/patch/796237/ Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/580272414 --- arch/arm/mach-imx/spl.c | 11 +++++++++++ common/spl/Kconfig | 9 +++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 1f230aca3397..daa3d8f7ed94 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -178,7 +178,18 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ u32 spl_boot_mode(const u32 boot_device) { +/* + * When CONFIG_SPL_FORCE_MMC_BOOT is defined the 'boot_device' is used + * unconditionally to decide about device to use for booting. + * This is crucial for falcon boot mode, when board boots up (i.e. ROM + * loads SPL) from slow SPI-NOR memory and afterwards the SPL's 'falcon' boot + * mode is used to load Linux OS from eMMC partition. + */ +#ifdef CONFIG_SPL_FORCE_MMC_BOOT + switch (boot_device) { +#else switch (spl_boot_device()) { +#endif /* for MMC return either RAW or FAT mode */ case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f467eca2be72..fe800840beb6 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -607,6 +607,15 @@ config SPL_MMC_SUPPORT this option to build the drivers in drivers/mmc as part of an SPL build. +config SPL_FORCE_MMC_BOOT + bool "Force SPL booting from MMC" + depends on SPL_MMC_SUPPORT + default n + help + Force SPL to use MMC device for Linux kernel booting even when the + SoC ROM recognized boot medium is not eMMC/SD. This is crucial for + factory or 'falcon mode' booting. + config SPL_MMC_TINY bool "Tiny MMC framework in SPL" depends on SPL_MMC_SUPPORT -- 2.11.0

3 4

[U-Boot] [PATCH 0/2] Add Broadcom SPI driver
by Vladimir Olovyannikov 03 Apr '20

03 Apr '20

This patchset: - adds Broadcom SPI driver for iproc-based platforms and - extends Micron SPI commands for dual and quad SPI transfers on Micon SPI. Shreesha Rajashekar (1): drivers: spi: Add brcm iproc spi driver Corneliu Doban (1): drivers: spi: Add commands for Micron SPI drivers/spi/Kconfig | 26 + drivers/spi/Makefile | 4 + drivers/spi/iproc_qspi.c | 1161 ++++++++++++++++++++++++++++++++++++++ drivers/spi/iproc_qspi.h | 47 ++ drivers/spi/iproc_spi.c | 71 +++ include/spi.h | 6 + 6 files changed, 1315 insertions(+) create mode 100644 drivers/spi/iproc_qspi.c create mode 100644 drivers/spi/iproc_qspi.h create mode 100644 drivers/spi/iproc_spi.c -- 2.17.1

2 3

[U-Boot] [PATCH v1 0/2] stm32f7 gpio driver fixes
by Patrice Chotard 31 Mar '20

31 Mar '20

This series adds: - Fix gpio bank hole management for stm32 F7 and H7 - Fix SPL code size for stm32 F7 Patrice Chotard (2): gpio: stm32f7: Fix gpio bank hole management gpio: stm32f7: Fix SPL code size drivers/gpio/stm32f7_gpio.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) -- 1.9.1

6 11

[U-Boot] [PATCH] rockchip: rk3399: Add Pinebook Pro laptop support
by Peter Robinson 28 Mar '20

28 Mar '20

Add initial support for Pinebook Pro laptop. Specification - Rockchip RK3399 - 4GB Dual-Channel LPDDR4 - SD card slot - eMMC socket - 128Mb SPI Flash - PCIe 4X slot - AP6256 for WiFi + BT - 1920*1080 screen - USB 3.0, 2.0 - USB Type C power and data - DC 12V/2A Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- Initial v1 for feedback U-Boot TPL 2020.01-rc2-00005-g7d87be0ff5 (Nov 14 2019 - 00:27:33) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2020.01-rc2-00005-g7d87be0ff5 (Nov 14 2019 - 00:27:33 +0000) Trying to boot from MMC1 U-Boot 2020.01-rc2-00005-g7d87be0ff5 (Nov 14 2019 - 00:27:33 +0000) Model: Pine64 Pinebook Pro DRAM: 3.9 GiB PMIC: RK808 MMC: dwmmc@fe320000: 1, sdhci@fe330000: 0 In: serial@ff1a0000 Out: serial@ff1a0000 Err: serial@ff1a0000 Model: Pine64 Pinebook Pro ## Error: Can't overwrite "serial#" ## Error inserting "serial#" variable, errno=1 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net: No ethernet found. Hit any key to stop autoboot: 0 => arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 25 + arch/arm/dts/rk3399-pinebook-pro.dts | 631 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 8 + board/pine64/pinebook_pro_rk3399/Kconfig | 15 + board/pine64/pinebook_pro_rk3399/MAINTAINERS | 8 + board/pine64/pinebook_pro_rk3399/Makefile | 1 + .../pinebook_pro_rk3399/pinebook-pro-rk3399.c | 192 ++++++ configs/pinebook_pro-rk3399_defconfig | 76 +++ include/configs/pinebook_pro_rk3399.h | 29 + 10 files changed, 986 insertions(+) create mode 100644 arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-pinebook-pro.dts create mode 100644 board/pine64/pinebook_pro_rk3399/Kconfig create mode 100644 board/pine64/pinebook_pro_rk3399/MAINTAINERS create mode 100644 board/pine64/pinebook_pro_rk3399/Makefile create mode 100644 board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c create mode 100644 configs/pinebook_pro-rk3399_defconfig create mode 100644 include/configs/pinebook_pro_rk3399.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5a64fcc5a7..affedfd666 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -116,6 +116,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-m4.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi new file mode 100644 index 0000000000..9b0cb7010f --- /dev/null +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&spiflash { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts new file mode 100644 index 0000000000..85ce0206d7 --- /dev/null +++ b/arch/arm/dts/rk3399-pinebook-pro.dts @@ -0,0 +1,631 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Pine64 Pinebook Pro"; + compatible = "pine64,pinebook-pro", "rockchip,rk3399"; + + chosen { + stdout-path = &uart2; + }; + + aliases { + spi0 = &spi1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pwms = <&pwm0 0 740740 0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + work-led { + label = "work"; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + standby-led { + label = "standby"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + }; + + vcc5v0_usb3_host: vcc5v0-usb3-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_usb3_drv>; + regulator-name = "vcc5v0_usb3_host"; + regulator-always-on; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <950000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_usb3_host>; + status = "okay"; + }; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_vbus_drv: host-vbus-drv { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_usb3_drv: host-usb3-drv { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + status = "okay"; + max-frequency = <20000000>; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <25000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&spi1 { + status = "okay"; + + spiflash: spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <10000000>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@8000 { + label = "loader"; + reg = <0x0 0x3F8000>; + }; + + env@3f8000 { + label = "env"; + reg = <0x3F8000 0x8000>; + }; + + vendor@7c0000 { + label = "vendor"; + reg = <0x7C0000 0x40000>; + }; + }; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index f781eacd16..f694ce0119 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -10,6 +10,13 @@ config TARGET_EVB_RK3399 with full function and phisical connectors support like type-C ports, usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... +config TARGET_PINEBOOK_PRO_RK3399 + bool "Pinebook Pro" + help + Pinebook Pro is a laptop based on the Rockchip rk3399 SoC + with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, + 1920*1080 screen and all the usual laptop features. + config TARGET_PUMA_RK3399 bool "Theobroma Systems RK3399-Q7 (Puma)" help @@ -94,6 +101,7 @@ config TPL_TEXT_BASE config SPL_STACK_R_ADDR default 0x04000000 +source "board/pine64/pinebook_pro_rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/board/pine64/pinebook_pro_rk3399/Kconfig b/board/pine64/pinebook_pro_rk3399/Kconfig new file mode 100644 index 0000000000..c37c643d6f --- /dev/null +++ b/board/pine64/pinebook_pro_rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PINEBOOK_PRO_RK3399 + +config SYS_BOARD + default "pinebook_pro_rk3399" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "pinebook_pro_rk3399" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + +endif diff --git a/board/pine64/pinebook_pro_rk3399/MAINTAINERS b/board/pine64/pinebook_pro_rk3399/MAINTAINERS new file mode 100644 index 0000000000..58400ebd28 --- /dev/null +++ b/board/pine64/pinebook_pro_rk3399/MAINTAINERS @@ -0,0 +1,8 @@ +PINEBOOK_PRO +M: Peter Robinson <pbrobinson at gmail.com> +S: Maintained +F: board/pine64/pinebook_pro_rk3399/ +F: include/configs/pinebook_pro_rk3399.h +F: arch/arm/dts/rk3399-pinebook-pro.dts +F: arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +F: configs/pinebook_pro-rk3399_defconfig diff --git a/board/pine64/pinebook_pro_rk3399/Makefile b/board/pine64/pinebook_pro_rk3399/Makefile new file mode 100644 index 0000000000..2f692a12a6 --- /dev/null +++ b/board/pine64/pinebook_pro_rk3399/Makefile @@ -0,0 +1 @@ +obj-y += pinebook-pro-rk3399.o diff --git a/board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c new file mode 100644 index 0000000000..b1a2ed3b77 --- /dev/null +++ b/board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <misc.h> +#include <syscon.h> +#include <dm/pinctrl.h> +#include <dm/uclass-internal.h> +#include <asm/io.h> +#include <asm/setup.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/misc.h> +#include <asm/arch-rockchip/periph.h> +#include <power/regulator.h> +#include <usb.h> +#include <dwc3-uboot.h> + +#define RK3399_CPUID_OFF 0x7 +#define RK3399_CPUID_LEN 0x10 + +static int fix_lcd_backling_pull_mode(void) +{ +#include <asm/arch-rockchip/grf_rk3399.h> + +#define PMU_GRF_BASE 0xff320000 + + // set pull of GPIO1_A0 + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMU_GRF_BASE; + rk_clrsetreg(&pmugrf->gpio1_p[0], 3 << (2 * 0), 0 << (2 * 0)); + return 0; +} + +#ifndef CONFIG_SPL_BUILD +int board_early_init_f(void) +{ + struct udevice *regulator; + int ret; + + ret = regulator_get_by_platname("vcc5v0_host", &regulator); + if (ret) { + debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); + goto out; + } + + ret = regulator_set_enable(regulator, true); + if (ret) + debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret); + + fix_lcd_backling_pull_mode(); + +out: + return 0; +} +#endif + +static void setup_serial(void) +{ +#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) + struct udevice *dev; + int ret, i; + u8 cpuid[RK3399_CPUID_LEN]; + u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2]; + char cpuid_str[RK3399_CPUID_LEN * 2 + 1]; + u64 serialno; + char serialno_str[16]; + + /* retrieve the device */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(rockchip_efuse), &dev); + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid)); + if (ret) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return; + } + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < 16; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < 8; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, 8); + serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); + + env_set("cpuid#", cpuid_str); + env_set("serial#", serialno_str); +#endif + + return; +} + +#define GRF_IO_VSEL_BT565_SHIFT 0 +#define PMUGRF_CON0_VSEL_SHIFT 8 + +#ifdef CONFIG_MISC_INIT_R +static void setup_iodomain(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3399_pmugrf_regs *pmugrf = + syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + + /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ + rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); +} + +int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + setup_iodomain(); + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + + setup_serial(); + + return ret; +} +#endif + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial_string; + u64 serial = 0; + + serial_string = env_get("serial#"); + + if (serial_string) + serial = simple_strtoull(serial_string, NULL, 16); + + serialnr->high = (u32)(serial >> 32); + serialnr->low = (u32)(serial & 0xffffffff); +} +#endif + +#ifdef CONFIG_USB_DWC3 +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = 0xfe800000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .dis_u2_susphy_quirk = 1, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + return dwc3_uboot_init(&dwc3_device_data); +} +#endif diff --git a/configs/pinebook_pro-rk3399_defconfig b/configs/pinebook_pro-rk3399_defconfig new file mode 100644 index 0000000000..28577256e7 --- /dev/null +++ b/configs/pinebook_pro-rk3399_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_PINEBOOK_PRO_RK3399=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MTDPARTS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_BOOTDELAY=3 +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +# CONFIG_USB_XHCI_ROCKCHIP is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/pinebook_pro_rk3399.h b/include/configs/pinebook_pro_rk3399.h new file mode 100644 index 0000000000..f383becbf8 --- /dev/null +++ b/include/configs/pinebook_pro_rk3399.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd + * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PINEBOOKPRO_RK3399_H +#define __PINEBOOKPRO_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3399_common.h> + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#endif + +#undef CONFIG_SYS_SPI_U_BOOT_OFFS +#define CONFIG_SYS_SPI_U_BOOT_OFFS 1024 * 512 + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif -- 2.23.0

4 5

[U-Boot] Sharing a hardware lab
by Simon Glass 26 Mar '20

26 Mar '20

Hi Tom, I have been meaning to have a crack at setting up a little hardware lab for a while. I made some progress recently and hooked up a rpi_3 with sdwire for USB/SD, ykush for power and a little computer to control it. It builds U-Boot, sticks it on the SD card and runs pytest. I pushed a tree here and hopefully you can see the 'hwlab' thing at the end: https://gitlab.denx.de/u-boot/custodians/u-boot-dm/pipelines/148 So far it is just running the 'help' test. It seems to hang with serial console problems if I try to do more. It is not 100% reliable yet. I based it on Stephen's test hooks: https://github.com/sglass68/uboot-test-hooks Is it possible to share this so that others can use the lab when they push trees? Is it as simple as adding to the .gitlab-ci.yml file as I have done here? https://gitlab.denx.de/u-boot/custodians/u-boot-dm/blob/gitlab-working/.git… I also got tbot going in a similar way, to test booting into Linux. Should we look at integrating that at the same time? It should be fairly easy to do. I have quite a lot of random boards and in principle it should not be too hard to hook up some more of them, with sufficient SDwires, hubs and patience. Regards, Simon

6 18

[U-Boot] [PATCH 1/1] drivers: i2c: Add brcm iproc I2C driver support
by Vladimir Olovyannikov 26 Mar '20

26 Mar '20

From: Arjun Jyothi <arjun.jyothi(a)broadcom.com> Add I2C driver support for Broadcom iproc-based socs. Signed-off-by: Arjun Jyothi <arjun.jyothi(a)broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur(a)broadcom.com> Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli(a)broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov(a)broadcom.com> --- drivers/i2c/Kconfig | 623 ++++++++++++++++---------------- drivers/i2c/Makefile | 2 +- drivers/i2c/iproc_i2c.c | 765 ++++++++++++++++++++++++++++++++++++++++ drivers/i2c/iproc_i2c.h | 356 +++++++++++++++++++ 4 files changed, 1437 insertions(+), 309 deletions(-) create mode 100644 drivers/i2c/iproc_i2c.c create mode 100644 drivers/i2c/iproc_i2c.h diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 03d2fed341..7a80971b12 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -5,454 +5,461 @@ menu "I2C support" config DM_I2C - bool "Enable Driver Model for I2C drivers" - depends on DM - help - Enable driver model for I2C. The I2C uclass interface: probe, read, - write and speed, is implemented with the bus drivers operations, - which provide methods for bus setting and data transfer. Each chip - device (bus child) info is kept as parent platdata. The interface - is defined in include/i2c.h. + bool "Enable Driver Model for I2C drivers" + depends on DM + help + Enable driver model for I2C. The I2C uclass interface: probe, read, + write and speed, is implemented with the bus drivers operations, + which provide methods for bus setting and data transfer. Each chip + device (bus child) info is kept as parent platdata. The interface + is defined in include/i2c.h. config I2C_CROS_EC_TUNNEL - tristate "Chrome OS EC tunnel I2C bus" - depends on CROS_EC - help - This provides an I2C bus that will tunnel i2c commands through to - the other side of the Chrome OS EC to the I2C bus connected there. - This will work whatever the interface used to talk to the EC (SPI, - I2C or LPC). Some Chromebooks use this when the hardware design - does not allow direct access to the main PMIC from the AP. + tristate "Chrome OS EC tunnel I2C bus" + depends on CROS_EC + help + This provides an I2C bus that will tunnel i2c commands through to + the other side of the Chrome OS EC to the I2C bus connected there. + This will work whatever the interface used to talk to the EC (SPI, + I2C or LPC). Some Chromebooks use this when the hardware design + does not allow direct access to the main PMIC from the AP. config I2C_CROS_EC_LDO - bool "Provide access to LDOs on the Chrome OS EC" - depends on CROS_EC - ---help--- - On many Chromebooks the main PMIC is inaccessible to the AP. This is - often dealt with by using an I2C pass-through interface provided by - the EC. On some unfortunate models (e.g. Spring) the pass-through - is not available, and an LDO message is available instead. This - option enables a driver which provides very basic access to those - regulators, via the EC. We implement this as an I2C bus which - emulates just the TPS65090 messages we know about. This is done to - avoid duplicating the logic in the TPS65090 regulator driver for - enabling/disabling an LDO. + bool "Provide access to LDOs on the Chrome OS EC" + depends on CROS_EC + ---help--- + On many Chromebooks the main PMIC is inaccessible to the AP. This is + often dealt with by using an I2C pass-through interface provided by + the EC. On some unfortunate models (e.g. Spring) the pass-through + is not available, and an LDO message is available instead. This + option enables a driver which provides very basic access to those + regulators, via the EC. We implement this as an I2C bus which + emulates just the TPS65090 messages we know about. This is done to + avoid duplicating the logic in the TPS65090 regulator driver for + enabling/disabling an LDO. config I2C_SET_DEFAULT_BUS_NUM - bool "Set default I2C bus number" - depends on DM_I2C - help - Set default number of I2C bus to be accessed. This option provides - behaviour similar to old (i.e. pre DM) I2C bus driver. + bool "Set default I2C bus number" + depends on DM_I2C + help + Set default number of I2C bus to be accessed. This option provides + behaviour similar to old (i.e. pre DM) I2C bus driver. config I2C_DEFAULT_BUS_NUMBER - hex "I2C default bus number" - depends on I2C_SET_DEFAULT_BUS_NUM - default 0x0 - help - Number of default I2C bus to use + hex "I2C default bus number" + depends on I2C_SET_DEFAULT_BUS_NUM + default 0x0 + help + Number of default I2C bus to use config DM_I2C_GPIO - bool "Enable Driver Model for software emulated I2C bus driver" - depends on DM_I2C && DM_GPIO - help - Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO - configuration is given by the device tree. Kernel-style device tree - bindings are supported. - Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt + bool "Enable Driver Model for software emulated I2C bus driver" + depends on DM_I2C && DM_GPIO + help + Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO + configuration is given by the device tree. Kernel-style device tree + bindings are supported. + Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt config SYS_I2C_AT91 - bool "Atmel I2C driver" - depends on DM_I2C && ARCH_AT91 - help - Add support for the Atmel I2C driver. A serious problem is that there - is no documented way to issue repeated START conditions for more than - two messages, as needed to support combined I2C messages. Use the - i2c-gpio driver unless your system can cope with this limitation. - Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt + bool "Atmel I2C driver" + depends on DM_I2C && ARCH_AT91 + help + Add support for the Atmel I2C driver. A serious problem is that there + is no documented way to issue repeated START conditions for more than + two messages, as needed to support combined I2C messages. Use the + i2c-gpio driver unless your system can cope with this limitation. + Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt + +config IPROC_I2C + bool "Broadcom iProc I2C driver" + depends on DM_I2C + help + Add support for Broadcom iProc I2C driver. + The driver is used in iProc SoCs. config SYS_I2C_FSL bool "Freescale I2C bus driver" depends on DM_I2C help - Add support for Freescale I2C busses as used on MPC8240, MPC8245, and - MPC85xx processors. + Add support for Freescale I2C busses as used on MPC8240, MPC8245, and + MPC85xx processors. config SYS_I2C_CADENCE - tristate "Cadence I2C Controller" - depends on DM_I2C && (ARCH_ZYNQ || ARM64) - help - Say yes here to select Cadence I2C Host Controller. This controller is - e.g. used by Xilinx Zynq. + tristate "Cadence I2C Controller" + depends on DM_I2C && (ARCH_ZYNQ || ARM64) + help + Say yes here to select Cadence I2C Host Controller. This controller is + e.g. used by Xilinx Zynq. config SYS_I2C_DAVINCI - bool "Davinci I2C Controller" - depends on (ARCH_KEYSTONE || ARCH_DAVINCI) - help - Say yes here to add support for Davinci and Keystone I2C controller + bool "Davinci I2C Controller" + depends on (ARCH_KEYSTONE || ARCH_DAVINCI) + help + Say yes here to add support for Davinci and Keystone I2C controller config SYS_I2C_DW - bool "Designware I2C Controller" - default n - help - Say yes here to select the Designware I2C Host Controller. This - controller is used in various SoCs, e.g. the ST SPEAr, Altera - SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. + bool "Designware I2C Controller" + default n + help + Say yes here to select the Designware I2C Host Controller. This + controller is used in various SoCs, e.g. the ST SPEAr, Altera + SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED - bool "DW I2C Enable Status Register not supported" - depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \ - TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600) - default y - help - Some versions of the Designware I2C controller do not support the - enable status register. This config option can be enabled in such - cases. + bool "DW I2C Enable Status Register not supported" + depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \ + TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600) + default y + help + Some versions of the Designware I2C controller do not support the + enable status register. This config option can be enabled in such + cases. config SYS_I2C_ASPEED - bool "Aspeed I2C Controller" - depends on DM_I2C && ARCH_ASPEED - help - Say yes here to select Aspeed I2C Host Controller. The driver - supports AST2500 and AST2400 controllers, but is very limited. - Only single master mode is supported and only byte-by-byte - synchronous reads and writes are supported, no Pool Buffers or DMA. + bool "Aspeed I2C Controller" + depends on DM_I2C && ARCH_ASPEED + help + Say yes here to select Aspeed I2C Host Controller. The driver + supports AST2500 and AST2400 controllers, but is very limited. + Only single master mode is supported and only byte-by-byte + synchronous reads and writes are supported, no Pool Buffers or DMA. config SYS_I2C_INTEL - bool "Intel I2C/SMBUS driver" - depends on DM_I2C - help - Add support for the Intel SMBUS driver. So far this driver is just - a stub which perhaps some basic init. There is no implementation of - the I2C API meaning that any I2C operations will immediately fail - for now. + bool "Intel I2C/SMBUS driver" + depends on DM_I2C + help + Add support for the Intel SMBUS driver. So far this driver is just + a stub which perhaps some basic init. There is no implementation of + the I2C API meaning that any I2C operations will immediately fail + for now. config SYS_I2C_IMX_LPI2C - bool "NXP i.MX LPI2C driver" - help - Add support for the NXP i.MX LPI2C driver. + bool "NXP i.MX LPI2C driver" + help + Add support for the NXP i.MX LPI2C driver. config SYS_I2C_MESON - bool "Amlogic Meson I2C driver" - depends on DM_I2C && ARCH_MESON - help - Add support for the I2C controller available in Amlogic Meson - SoCs. The controller supports programmable bus speed including - standard (100kbits/s) and fast (400kbit/s) speed and allows the - software to define a flexible format of the bit streams. It has an - internal buffer holding up to 8 bytes for transfers and supports - both 7-bit and 10-bit addresses. + bool "Amlogic Meson I2C driver" + depends on DM_I2C && ARCH_MESON + help + Add support for the I2C controller available in Amlogic Meson + SoCs. The controller supports programmable bus speed including + standard (100kbits/s) and fast (400kbit/s) speed and allows the + software to define a flexible format of the bit streams. It has an + internal buffer holding up to 8 bytes for transfers and supports + both 7-bit and 10-bit addresses. config SYS_I2C_MXC - bool "NXP MXC I2C driver" - help - Add support for the NXP I2C driver. This supports up to four bus - channels and operating on standard mode up to 100 kbits/s and fast - mode up to 400 kbits/s. + bool "NXP MXC I2C driver" + help + Add support for the NXP I2C driver. This supports up to four bus + channels and operating on standard mode up to 100 kbits/s and fast + mode up to 400 kbits/s. # These settings are not used with DM_I2C, however SPL doesn't use # DM_I2C even if DM_I2C is enabled, and so might use these settings even # when main u-boot does not! if SYS_I2C_MXC && (!DM_I2C || SPL) config SYS_I2C_MXC_I2C1 - bool "NXP MXC I2C1" - help - Add support for NXP MXC I2C Controller 1. - Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A + bool "NXP MXC I2C1" + help + Add support for NXP MXC I2C Controller 1. + Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C2 - bool "NXP MXC I2C2" - help - Add support for NXP MXC I2C Controller 2. - Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A + bool "NXP MXC I2C2" + help + Add support for NXP MXC I2C Controller 2. + Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C3 - bool "NXP MXC I2C3" - help - Add support for NXP MXC I2C Controller 3. - Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A + bool "NXP MXC I2C3" + help + Add support for NXP MXC I2C Controller 3. + Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C4 - bool "NXP MXC I2C4" - help - Add support for NXP MXC I2C Controller 4. - Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A + bool "NXP MXC I2C4" + help + Add support for NXP MXC I2C Controller 4. + Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C5 - bool "NXP MXC I2C5" - help - Add support for NXP MXC I2C Controller 5. - Required for SoCs which have I2C MXC controller 5 eg LX2160A + bool "NXP MXC I2C5" + help + Add support for NXP MXC I2C Controller 5. + Required for SoCs which have I2C MXC controller 5 eg LX2160A config SYS_I2C_MXC_I2C6 - bool "NXP MXC I2C6" - help - Add support for NXP MXC I2C Controller 6. - Required for SoCs which have I2C MXC controller 6 eg LX2160A + bool "NXP MXC I2C6" + help + Add support for NXP MXC I2C Controller 6. + Required for SoCs which have I2C MXC controller 6 eg LX2160A config SYS_I2C_MXC_I2C7 - bool "NXP MXC I2C7" - help - Add support for NXP MXC I2C Controller 7. - Required for SoCs which have I2C MXC controller 7 eg LX2160A + bool "NXP MXC I2C7" + help + Add support for NXP MXC I2C Controller 7. + Required for SoCs which have I2C MXC controller 7 eg LX2160A config SYS_I2C_MXC_I2C8 - bool "NXP MXC I2C8" - help - Add support for NXP MXC I2C Controller 8. - Required for SoCs which have I2C MXC controller 8 eg LX2160A + bool "NXP MXC I2C8" + help + Add support for NXP MXC I2C Controller 8. + Required for SoCs which have I2C MXC controller 8 eg LX2160A endif if SYS_I2C_MXC_I2C1 config SYS_MXC_I2C1_SPEED - int "I2C Channel 1 speed" - default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU - default 100000 - help - MXC I2C Channel 1 speed + int "I2C Channel 1 speed" + default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 100000 + help + MXC I2C Channel 1 speed config SYS_MXC_I2C1_SLAVE - int "I2C1 Slave" - default 0 - help - MXC I2C1 Slave + int "I2C1 Slave" + default 0 + help + MXC I2C1 Slave endif if SYS_I2C_MXC_I2C2 config SYS_MXC_I2C2_SPEED - int "I2C Channel 2 speed" - default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU - default 100000 - help - MXC I2C Channel 2 speed + int "I2C Channel 2 speed" + default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 100000 + help + MXC I2C Channel 2 speed config SYS_MXC_I2C2_SLAVE - int "I2C2 Slave" - default 0 - help - MXC I2C2 Slave + int "I2C2 Slave" + default 0 + help + MXC I2C2 Slave endif if SYS_I2C_MXC_I2C3 config SYS_MXC_I2C3_SPEED - int "I2C Channel 3 speed" - default 100000 - help - MXC I2C Channel 3 speed + int "I2C Channel 3 speed" + default 100000 + help + MXC I2C Channel 3 speed config SYS_MXC_I2C3_SLAVE - int "I2C3 Slave" - default 0 - help - MXC I2C3 Slave + int "I2C3 Slave" + default 0 + help + MXC I2C3 Slave endif if SYS_I2C_MXC_I2C4 config SYS_MXC_I2C4_SPEED - int "I2C Channel 4 speed" - default 100000 - help - MXC I2C Channel 4 speed + int "I2C Channel 4 speed" + default 100000 + help + MXC I2C Channel 4 speed config SYS_MXC_I2C4_SLAVE - int "I2C4 Slave" - default 0 - help - MXC I2C4 Slave + int "I2C4 Slave" + default 0 + help + MXC I2C4 Slave endif if SYS_I2C_MXC_I2C5 config SYS_MXC_I2C5_SPEED - int "I2C Channel 5 speed" - default 100000 - help - MXC I2C Channel 5 speed + int "I2C Channel 5 speed" + default 100000 + help + MXC I2C Channel 5 speed config SYS_MXC_I2C5_SLAVE - int "I2C5 Slave" - default 0 - help - MXC I2C5 Slave + int "I2C5 Slave" + default 0 + help + MXC I2C5 Slave endif if SYS_I2C_MXC_I2C6 config SYS_MXC_I2C6_SPEED - int "I2C Channel 6 speed" - default 100000 - help - MXC I2C Channel 6 speed + int "I2C Channel 6 speed" + default 100000 + help + MXC I2C Channel 6 speed config SYS_MXC_I2C6_SLAVE - int "I2C6 Slave" - default 0 - help - MXC I2C6 Slave + int "I2C6 Slave" + default 0 + help + MXC I2C6 Slave endif if SYS_I2C_MXC_I2C7 config SYS_MXC_I2C7_SPEED - int "I2C Channel 7 speed" - default 100000 - help - MXC I2C Channel 7 speed + int "I2C Channel 7 speed" + default 100000 + help + MXC I2C Channel 7 speed config SYS_MXC_I2C7_SLAVE - int "I2C7 Slave" - default 0 - help - MXC I2C7 Slave + int "I2C7 Slave" + default 0 + help + MXC I2C7 Slave endif if SYS_I2C_MXC_I2C8 config SYS_MXC_I2C8_SPEED - int "I2C Channel 8 speed" - default 100000 - help - MXC I2C Channel 8 speed + int "I2C Channel 8 speed" + default 100000 + help + MXC I2C Channel 8 speed config SYS_MXC_I2C8_SLAVE - int "I2C8 Slave" - default 0 - help - MXC I2C8 Slave + int "I2C8 Slave" + default 0 + help + MXC I2C8 Slave endif config SYS_I2C_OMAP24XX - bool "TI OMAP2+ I2C driver" - depends on ARCH_OMAP2PLUS || ARCH_K3 - help - Add support for the OMAP2+ I2C driver. + bool "TI OMAP2+ I2C driver" + depends on ARCH_OMAP2PLUS || ARCH_K3 + help + Add support for the OMAP2+ I2C driver. if SYS_I2C_OMAP24XX config SYS_OMAP24_I2C_SLAVE - int "I2C Slave addr channel 0" - default 1 - help - OMAP24xx I2C Slave address channel 0 + int "I2C Slave addr channel 0" + default 1 + help + OMAP24xx I2C Slave address channel 0 config SYS_OMAP24_I2C_SPEED - int "I2C Slave channel 0 speed" - default 100000 - help - OMAP24xx Slave speed channel 0 + int "I2C Slave channel 0 speed" + default 100000 + help + OMAP24xx Slave speed channel 0 endif config SYS_I2C_RCAR_I2C - bool "Renesas RCar I2C driver" - depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C - help - Support for Renesas RCar I2C controller. + bool "Renesas RCar I2C driver" + depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C + help + Support for Renesas RCar I2C controller. config SYS_I2C_RCAR_IIC - bool "Renesas RCar Gen3 IIC driver" - depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C - help - Support for Renesas RCar Gen3 IIC controller. + bool "Renesas RCar Gen3 IIC driver" + depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C + help + Support for Renesas RCar Gen3 IIC controller. config SYS_I2C_ROCKCHIP - bool "Rockchip I2C driver" - depends on DM_I2C - help - Add support for the Rockchip I2C driver. This is used with various - Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips - have several I2C ports and all are provided, controlled by the - device tree. + bool "Rockchip I2C driver" + depends on DM_I2C + help + Add support for the Rockchip I2C driver. This is used with various + Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips + have several I2C ports and all are provided, controlled by the + device tree. config SYS_I2C_SANDBOX - bool "Sandbox I2C driver" - depends on SANDBOX && DM_I2C - help - Enable I2C support for sandbox. This is an emulation of a real I2C - bus. Devices can be attached to the bus using the device tree - which specifies the driver to use. See sandbox.dts as an example. + bool "Sandbox I2C driver" + depends on SANDBOX && DM_I2C + help + Enable I2C support for sandbox. This is an emulation of a real I2C + bus. Devices can be attached to the bus using the device tree + which specifies the driver to use. See sandbox.dts as an example. config SYS_I2C_S3C24X0 - bool "Samsung I2C driver" - depends on ARCH_EXYNOS4 && DM_I2C - help - Support for Samsung I2C controller as Samsung SoCs. + bool "Samsung I2C driver" + depends on ARCH_EXYNOS4 && DM_I2C + help + Support for Samsung I2C controller as Samsung SoCs. config SYS_I2C_STM32F7 - bool "STMicroelectronics STM32F7 I2C support" - depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C - help - Enable this option to add support for STM32 I2C controller - introduced with STM32F7/H7 SoCs. This I2C controller supports : - _ Slave and master modes - _ Multimaster capability - _ Standard-mode (up to 100 kHz) - _ Fast-mode (up to 400 kHz) - _ Fast-mode Plus (up to 1 MHz) - _ 7-bit and 10-bit addressing mode - _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) - _ All 7-bit addresses acknowledge mode - _ General call - _ Programmable setup and hold times - _ Easy to use event management - _ Optional clock stretching - _ Software reset + bool "STMicroelectronics STM32F7 I2C support" + depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C + help + Enable this option to add support for STM32 I2C controller + introduced with STM32F7/H7 SoCs. This I2C controller supports : + _ Slave and master modes + _ Multimaster capability + _ Standard-mode (up to 100 kHz) + _ Fast-mode (up to 400 kHz) + _ Fast-mode Plus (up to 1 MHz) + _ 7-bit and 10-bit addressing mode + _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) + _ All 7-bit addresses acknowledge mode + _ General call + _ Programmable setup and hold times + _ Easy to use event management + _ Optional clock stretching + _ Software reset config SYS_I2C_TEGRA - bool "NVIDIA Tegra internal I2C controller" - depends on TEGRA - help - Support for NVIDIA I2C controller available in Tegra SoCs. + bool "NVIDIA Tegra internal I2C controller" + depends on TEGRA + help + Support for NVIDIA I2C controller available in Tegra SoCs. config SYS_I2C_UNIPHIER - bool "UniPhier I2C driver" - depends on ARCH_UNIPHIER && DM_I2C - default y - help - Support for UniPhier I2C controller driver. This I2C controller - is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. + bool "UniPhier I2C driver" + depends on ARCH_UNIPHIER && DM_I2C + default y + help + Support for UniPhier I2C controller driver. This I2C controller + is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. config SYS_I2C_UNIPHIER_F - bool "UniPhier FIFO-builtin I2C driver" - depends on ARCH_UNIPHIER && DM_I2C - default y - help - Support for UniPhier FIFO-builtin I2C controller driver. - This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. + bool "UniPhier FIFO-builtin I2C driver" + depends on ARCH_UNIPHIER && DM_I2C + default y + help + Support for UniPhier FIFO-builtin I2C controller driver. + This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. config SYS_I2C_VERSATILE - bool "Arm Ltd Versatile I2C bus driver" - depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO) - help - Add support for the Arm Ltd Versatile Express I2C driver. The I2C host - controller is present in the development boards manufactured by Arm Ltd. + bool "Arm Ltd Versatile I2C bus driver" + depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO) + help + Add support for the Arm Ltd Versatile Express I2C driver. The I2C host + controller is present in the development boards manufactured by Arm Ltd. config SYS_I2C_MVTWSI - bool "Marvell I2C driver" - depends on DM_I2C - help - Support for Marvell I2C controllers as used on the orion5x and - kirkwood SoC families. + bool "Marvell I2C driver" + depends on DM_I2C + help + Support for Marvell I2C controllers as used on the orion5x and + kirkwood SoC families. config TEGRA186_BPMP_I2C - bool "Enable Tegra186 BPMP-based I2C driver" - depends on TEGRA186_BPMP - help - Support for Tegra I2C controllers managed by the BPMP (Boot and - Power Management Processor). On Tegra186, some I2C controllers are - directly controlled by the main CPU, whereas others are controlled - by the BPMP, and can only be accessed by the main CPU via IPC - requests to the BPMP. This driver covers the latter case. + bool "Enable Tegra186 BPMP-based I2C driver" + depends on TEGRA186_BPMP + help + Support for Tegra I2C controllers managed by the BPMP (Boot and + Power Management Processor). On Tegra186, some I2C controllers are + directly controlled by the main CPU, whereas others are controlled + by the BPMP, and can only be accessed by the main CPU via IPC + requests to the BPMP. This driver covers the latter case. config SYS_I2C_BUS_MAX - int "Max I2C busses" - depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA - default 2 if TI816X - default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE - default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X - default 5 if OMAP54XX - help - Define the maximum number of available I2C buses. + int "Max I2C busses" + depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA + default 2 if TI816X + default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE + default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X + default 5 if OMAP54XX + help + Define the maximum number of available I2C buses. config SYS_I2C_XILINX_XIIC - bool "Xilinx AXI I2C driver" - depends on DM_I2C - help - Support for Xilinx AXI I2C controller. + bool "Xilinx AXI I2C driver" + depends on DM_I2C + help + Support for Xilinx AXI I2C controller. config SYS_I2C_IHS bool "gdsys IHS I2C driver" diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index c2f75d8755..7cfe68e088 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -38,5 +38,5 @@ obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o - +obj-$(CONFIG_IPROC_I2C) += iproc_i2c.o obj-$(CONFIG_I2C_MUX) += muxes/ diff --git a/drivers/i2c/iproc_i2c.c b/drivers/i2c/iproc_i2c.c new file mode 100644 index 0000000000..692035666c --- /dev/null +++ b/drivers/i2c/iproc_i2c.c @@ -0,0 +1,765 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C)) 2018 Broadcom + */ + +#include <common.h> +#include <config.h> +#include <dm.h> +#include <i2c.h> +#include <asm/io.h> +#include "errno.h" +#include "iproc_i2c.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int i2c_init_done; + +struct iproc_i2c_regs { + u32 cfg_reg; + u32 timg_cfg; + u32 addr_reg; + u32 mstr_fifo_ctrl; + u32 slv_fifo_ctrl; + u32 bitbng_ctrl; + u32 blnks[6]; /* Not to be used */ + u32 mstr_cmd; + u32 slv_cmd; + u32 evt_en; + u32 evt_sts; + u32 mstr_datawr; + u32 mstr_datard; + u32 slv_datawr; + u32 slv_datard; +}; + +struct iproc_i2c { + struct iproc_i2c_regs __iomem *base; /* register base */ + int bus_speed; +}; + +/* Function to read a value from specified register. */ +static unsigned int iproc_i2c_reg_read(u32 *reg_addr) +{ + unsigned int val; + + val = readl((void *)(reg_addr)); + return cpu_to_le32(val); +} + +/* Function to write a value ('val') in to a specified register. */ +static int iproc_i2c_reg_write(u32 *reg_addr, unsigned int val) +{ + val = cpu_to_le32(val); + writel(val, (void *)(reg_addr)); + return 0; +} + +#ifdef IPROC_I2C_DBG +static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata) +{ + struct iproc_i2c_regs *base = bus_prvdata->base; + unsigned int regval; + + debug("\n----------------------------------------------\n"); + debug("%s: Dumping SMBus registers...\n", __func__); + + regval = iproc_i2c_reg_read(&base->cfg_reg); + debug("CCB_SMB_CFG_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->timg_cfg); + debug("CCB_SMB_TIMGCFG_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->addr_reg); + debug("CCB_SMB_ADDR_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->mstr_fifo_ctrl); + debug("CCB_SMB_MSTRFIFOCTL_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->slv_fifo_ctrl); + debug("CCB_SMB_SLVFIFOCTL_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->bitbng_ctrl); + debug("CCB_SMB_BITBANGCTL_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->mstr_cmd); + debug("CCB_SMB_MSTRCMD_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->slv_cmd); + debug("CCB_SMB_SLVCMD_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->evt_en); + debug("CCB_SMB_EVTEN_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->evt_sts); + debug("CCB_SMB_EVTSTS_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->mstr_datawr); + debug("CCB_SMB_MSTRDATAWR_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->mstr_datard); + debug("CCB_SMB_MSTRDATARD_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->slv_datawr); + debug("CCB_SMB_SLVDATAWR_REG=0x%08X\n", regval); + + regval = iproc_i2c_reg_read(&base->slv_datard); + debug("CCB_SMB_SLVDATARD_REG=0x%08X\n", regval); + + debug("----------------------------------------------\n\n"); + return 0; +} +#endif + +/* + * Function to ensure that the previous transaction was completed before + * initiating a new transaction. It can also be used in polling mode to + * check status of completion of a command + */ +static int iproc_i2c_startbusy_wait(struct iproc_i2c *bus_prvdata) +{ + struct iproc_i2c_regs *base = bus_prvdata->base; + unsigned int regval; + + regval = iproc_i2c_reg_read(&base->mstr_cmd); + + /* Check if an operation is in progress. During probe it won't be. + * But when shutdown/remove was called we want to make sure that + * the transaction in progress completed + */ + if (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) { + unsigned int i = 0; + + do { + mdelay(10); /* Wait for 10 msec */ + i++; + regval = iproc_i2c_reg_read(&base->mstr_cmd); + + /* If start-busy bit cleared, exit the loop */ + } while ((regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) && + (i < IPROC_SMB_MAX_RETRIES)); + + if (i >= IPROC_SMB_MAX_RETRIES) { + pr_err("%s: START_BUSY bit didn't clear, exiting\n", + __func__); + + return -ETIMEDOUT; + } + } + return 0; +} + +/* + * This function set clock frequency for SMBus block. As per hardware + * engineering, the clock frequency can be changed dynamically. + */ +static int iproc_i2c_set_clk_freq(struct iproc_i2c *bus_prvdata) +{ + struct iproc_i2c_regs *base = bus_prvdata->base; + unsigned int regval; + + regval = iproc_i2c_reg_read(&base->timg_cfg); + + switch (bus_prvdata->bus_speed) { + case I2C_SPEED_100KHZ: + SETREGFLDVAL(regval, SMBUS_BLOCK_MODE_100, + CCB_SMB_TIMGCFG_MODE400_MASK, + CCB_SMB_TIMGCFG_MODE400_SHIFT); + break; + + case I2C_SPEED_400KHZ: + SETREGFLDVAL(regval, SMBUS_BLOCK_MODE_400, + CCB_SMB_TIMGCFG_MODE400_MASK, + CCB_SMB_TIMGCFG_MODE400_SHIFT); + break; + + default: + return -EINVAL; + } + + iproc_i2c_reg_write(&base->timg_cfg, regval); + return 0; +} + +static int iproc_i2c_init(struct iproc_i2c *bus_prvdata) +{ + struct iproc_i2c_regs *base = bus_prvdata->base; + unsigned int regval; + +#ifdef IPROC_I2C_DBG + debug("\n%s: Entering", __func__); +#endif /* IPROC_I2C_DBG */ + + /* Flush Tx, Rx FIFOs. Note we are setting the Rx FIFO threshold to 0. + * May be OK since we are setting RX_EVENT and RX_FIFO_FULL interrupts + */ + regval = CCB_SMB_MSTRRXFIFOFLSH_MASK | CCB_SMB_MSTRTXFIFOFLSH_MASK; + iproc_i2c_reg_write(&base->mstr_fifo_ctrl, regval); + + /* Enable SMbus block. Note, we are setting MASTER_RETRY_COUNT to zero + * since there will be only one master + */ + + regval = iproc_i2c_reg_read(&base->cfg_reg); + regval |= CCB_SMB_CFG_SMBEN_MASK; + iproc_i2c_reg_write(&base->cfg_reg, regval); +#if defined(CONFIG_CYGNUS) || defined(CONFIG_TARGET_BCMOMEGA) + regval = iproc_i2c_reg_read(&base->cfg_reg); + regval |= CCB_SMB_CFG_RST_MASK; + iproc_i2c_reg_write(&base->cfg_reg, regval); + regval &= ~CCB_SMB_CFG_RST_MASK; + iproc_i2c_reg_write(&base->cfg_reg, regval); +#endif + /* Wait a minimum of 50 Usec, as per SMB hw doc */ + udelay(50); + + /* Set default clock frequency */ + iproc_i2c_set_clk_freq(bus_prvdata); + + /* Disable intrs */ + iproc_i2c_reg_write(&base->evt_en, 0); + + /* Clear intrs (W1TC) */ + regval = iproc_i2c_reg_read(&base->evt_sts); + iproc_i2c_reg_write(&base->evt_sts, regval); + + i2c_init_done = 1; + +#ifdef IPROC_I2C_DBG + iproc_dump_i2c_regs(bus_prvdata); + + debug("%s: Init successful\n", __func__); +#endif /* IPROC_I2C_DBG */ + + return 0; +} + +/* + * This function copies data to SMBus's Tx FIFO. Valid for write transactions + * only + * + * base_addr: Mapped address of this SMBus instance + * dev_addr: SMBus (I2C) device address. We are assuming 7-bit addresses + * initially + * info: Data to copy in to Tx FIFO. For read commands, the size should be + * set to zero by the caller + * + */ +static void iproc_i2c_write_trans_data(struct iproc_i2c *bus_prvdata, + unsigned short dev_addr, + struct iproc_xact_info *info) +{ + struct iproc_i2c_regs *base = bus_prvdata->base; + unsigned int regval; + unsigned int i; + unsigned int num_data_bytes = 0; + +#ifdef IPROC_I2C_DBG + debug("%s: dev_addr=0x%X cmd_valid=%d cmd=0x%02x size=%u proto=%d\n" + "buf[] %x\n", + __func__, + dev_addr, + info->cmd_valid, + info->command, + info->size, + info->smb_proto, + info->data[0]); +#endif /* IPROC_I2C_DBG */ + + /* Write SMBus device address first */ + /* Note, we are assuming 7-bit addresses for now. For 10-bit addresses, + * we may have one more write to send the upper 3 bits of 10-bit addr + */ + iproc_i2c_reg_write(&base->mstr_datawr, dev_addr); + + /* If the protocol needs command code, copy it */ + if (info->cmd_valid) + iproc_i2c_reg_write(&base->mstr_datawr, info->command); + + /* Depending on the SMBus protocol, we need to write additional + * transaction data in to Tx FIFO. Refer to section 5.5 of SMBus + * spec for sequence for a transaction + */ + switch (info->smb_proto) { + case SMBUS_PROT_RECV_BYTE: + /* No additional data to be written */ + num_data_bytes = 0; + break; + + case SMBUS_PROT_SEND_BYTE: + num_data_bytes = info->size; + break; + + case SMBUS_PROT_RD_BYTE: + case SMBUS_PROT_RD_WORD: + case SMBUS_PROT_BLK_RD: + /* Write slave address with R/W~ set (bit #0) */ + iproc_i2c_reg_write(&base->mstr_datawr, + dev_addr | 0x1); + num_data_bytes = 0; + break; +#if defined(CONFIG_CYGNUS) || defined(CONFIG_TARGET_BCMOMEGA) + case SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL: + iproc_i2c_reg_write(&base->mstr_datawr, + dev_addr | 0x1 | + CCB_SMB_MSTRWRSTS_MASK); + num_data_bytes = 0; + break; +#endif + case SMBUS_PROT_WR_BYTE: + case SMBUS_PROT_WR_WORD: + /* No additional bytes to be written. + * Data portion is written in the + * 'for' loop below + */ + num_data_bytes = info->size; + break; + + case SMBUS_PROT_BLK_WR: + /* 3rd byte is byte count */ + iproc_i2c_reg_write(&base->mstr_datawr, info->size); + num_data_bytes = info->size; + break; + + default: + break; + } + + /* Copy actual data from caller, next. In general, for reads, no data is + * copied + */ + for (i = 0; num_data_bytes; --num_data_bytes, i++) { + /* For the last byte, set MASTER_WR_STATUS bit */ + regval = (num_data_bytes == 1) ? + info->data[i] | CCB_SMB_MSTRWRSTS_MASK : + info->data[i]; + + iproc_i2c_reg_write(&base->mstr_datawr, regval); + } +} + +static int iproc_i2c_data_send(struct iproc_i2c *bus_prvdata, + unsigned short addr, + struct iproc_xact_info *info) +{ + struct iproc_i2c_regs *base = bus_prvdata->base; + int rc, retry = 3; unsigned int regval; + + /* Make sure the previous transaction completed */ + rc = iproc_i2c_startbusy_wait(bus_prvdata); + + if (rc < 0) { + pr_err("%s: Send: bus is busy, exiting\n", __func__); + return rc; + } + + /* Write transaction bytes to Tx FIFO */ + iproc_i2c_write_trans_data(bus_prvdata, addr, info); + + /* Program master command register (0x30) with protocol type and set + * start_busy_command bit to initiate the write transaction + */ + regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) | + CCB_SMB_MSTRSTARTBUSYCMD_MASK; + + iproc_i2c_reg_write(&base->mstr_cmd, regval); + + /* Check for Master status */ + regval = iproc_i2c_reg_read(&base->mstr_cmd); + while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) { + mdelay(10); + if (retry-- <= 0) + break; + regval = iproc_i2c_reg_read(&base->mstr_cmd); + } + + /* If start_busy bit cleared, check if there are any errors */ + if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) { + /* start_busy bit cleared, check master_status field now */ + regval &= CCB_SMB_MSTRSTS_MASK; + regval >>= CCB_SMB_MSTRSTS_SHIFT; + + if (regval != MSTR_STS_XACT_SUCCESS) { + /* Error We can flush Tx FIFO here */ + pr_err("%s: ERROR: Error in transaction %u, exiting\n", + __func__, regval); + return -EREMOTEIO; + } + } + + return 0; +} + +static int iproc_i2c_data_recv(struct iproc_i2c *bus_prvdata, + unsigned short addr, + struct iproc_xact_info *info, + unsigned int *num_bytes_read) +{ + struct iproc_i2c_regs *base = bus_prvdata->base; + int rc, retry = 3; + unsigned int regval; + + /* Make sure the previous transaction completed */ + rc = iproc_i2c_startbusy_wait(bus_prvdata); + + if (rc < 0) { + pr_err("%s: Receive: Bus is busy, exiting\n", __func__); + return rc; + } + + /* Program all transaction bytes into master Tx FIFO */ + iproc_i2c_write_trans_data(bus_prvdata, addr, info); + + /* Program master command register (0x30) with protocol type and set + * start_busy_command bit to initiate the write transaction + */ + regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) | + CCB_SMB_MSTRSTARTBUSYCMD_MASK | info->size; + + iproc_i2c_reg_write(&base->mstr_cmd, regval); + + /* Check for Master status */ + regval = iproc_i2c_reg_read(&base->mstr_cmd); + while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) { + udelay(1000); + if (retry-- <= 0) + break; + regval = iproc_i2c_reg_read(&base->mstr_cmd); + } + + /* If start_busy bit cleared, check if there are any errors */ + if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) { + /* start_busy bit cleared, check master_status field now */ + regval &= CCB_SMB_MSTRSTS_MASK; + regval >>= CCB_SMB_MSTRSTS_SHIFT; + + if (regval != MSTR_STS_XACT_SUCCESS) { + /* We can flush Tx FIFO here */ + pr_err("%s: Error in transaction %d, exiting\n", + __func__, regval); + return -EREMOTEIO; + } + } + + /* Read received byte(s), after TX out address etc */ + regval = iproc_i2c_reg_read(&base->mstr_datard); + + /* For block read, protocol (hw) returns byte count, + * as the first byte + */ + if (info->smb_proto == SMBUS_PROT_BLK_RD) { + int i; + + *num_bytes_read = regval & CCB_SMB_MSTRRDDATA_MASK; + + /* Limit to reading a max of 32 bytes only; just a safeguard. + * If # bytes read is a number > 32, check transaction set up, + * and contact hw engg. Assumption: PEC is disabled + */ + for (i = 0; + (i < *num_bytes_read) && (i < I2C_SMBUS_BLOCK_MAX); + i++) { + /* Read Rx FIFO for data bytes */ + regval = iproc_i2c_reg_read(&base->mstr_datard); + info->data[i] = regval & CCB_SMB_MSTRRDDATA_MASK; + } + } else { + /* 1 Byte data */ + *info->data = regval & CCB_SMB_MSTRRDDATA_MASK; + *num_bytes_read = 1; + } + + return 0; +} + +static int i2c_write_byte(struct iproc_i2c *bus_prvdata, + u8 devaddr, + u8 regoffset, + u8 value) +{ + int rc; + struct iproc_xact_info info; + + devaddr <<= 1; + + info.cmd_valid = 1; + info.command = (unsigned char)regoffset; + info.data = &value; + info.size = 1; + info.flags = 0; +#if defined(CONFIG_CYGNUS) || defined(CONFIG_TARGET_BCMOMEGA) + info.smb_proto = SMBUS_PROT_WR_WORD;/*SMBUS_PROT_WR_BYTE;*/ +#else + info.smb_proto = SMBUS_PROT_WR_BYTE; +#endif + /* Refer to i2c_smbus_write_byte params passed. */ + rc = iproc_i2c_data_send(bus_prvdata, devaddr, &info); + + if (rc < 0) { + pr_err("%s: %s error accessing device 0x%X\n", + __func__, "Write", devaddr); + return -EREMOTEIO; + } + + return 0; +} + +int i2c_write(struct iproc_i2c *bus_prvdata, + uchar chip, + uint regaddr, + int alen, + uchar *buffer, + int len) +{ + int i, data_len; + u8 *data; + + if (alen > 1) { + pr_err("I2C write: addr len %d not supported\n", alen); + return 1; + } + + if (regaddr + len > 256) { + pr_err("I2C write: address out of range\n"); + return 1; + } + + if (len < 1) { + pr_err("I2C write: Need offset addr and value\n"); + return 1; + } + + /* buffer contains offset addr followed by value to be written */ + regaddr = buffer[0]; + data = &buffer[1]; + data_len = len - 1; + + for (i = 0; i < data_len; i++) { + if (i2c_write_byte(bus_prvdata, chip, regaddr + i, data[i])) { + pr_err("I2C write (%d): I/O error\n", i); + iproc_i2c_init(bus_prvdata); + return 1; + } + } + + return 0; +} + +static int i2c_read_byte(struct iproc_i2c *bus_prvdata, + u8 devaddr, + u8 regoffset, + u8 *value) +{ + int rc; + struct iproc_xact_info info; + unsigned int num_bytes_read = 0; + + devaddr <<= 1; + + info.cmd_valid = 1; + info.command = (unsigned char)regoffset; + info.data = value; + info.size = 1; + info.flags = 0; +#if defined(CONFIG_CYGNUS) || defined(CONFIG_TARGET_BCMOMEGA) + info.smb_proto = SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL; +#else + info.smb_proto = SMBUS_PROT_RD_BYTE; +#endif + /* Refer to i2c_smbus_read_byte for params passed. */ + rc = iproc_i2c_data_recv(bus_prvdata, devaddr, &info, &num_bytes_read); + + if (rc < 0) { + pr_err("%s: %s error accessing device 0x%X\n", + __func__, "Read", devaddr); + return -EREMOTEIO; + } + + return 0; +} + +int i2c_read(struct iproc_i2c *bus_prvdata, + uchar chip, + uint addr, + int alen, + uchar *buffer, + int len) +{ + int i; + + if (alen > 1) { + pr_err("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + pr_err("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_read_byte(bus_prvdata, chip, addr + i, &buffer[i])) { + pr_err("I2C read: I/O error\n"); + iproc_i2c_init(bus_prvdata); + return 1; + } + } + + return 0; +} + +static int iproc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct iproc_i2c *bus_prvdata = dev_get_priv(bus); + int ret = 0; + +#ifdef IPROC_I2C_DBG + debug("%s: %d messages\n", __func__, nmsgs); +#endif + + for (; nmsgs > 0; nmsgs--, msg++) { + if (msg->flags & I2C_M_RD) + ret = i2c_read(bus_prvdata, + msg->addr, + 0, + 0, + msg->buf, + msg->len); + else + ret = i2c_write(bus_prvdata, + msg->addr, + 0, + 0, + msg->buf, + msg->len); + } + + return ret; +} + +static int iproc_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct iproc_i2c *bus_prvdata = dev_get_priv(bus); + struct iproc_i2c_regs *base = bus_prvdata->base; + u32 regval; + +#ifdef IPROC_I2C_DBG + debug("\n%s: Entering chip probe\n", __func__); +#endif /* IPROC_I2C_DBG */ + + /* Init internal regs, disable intrs (and then clear intrs), set fifo + * thresholds, etc. + */ + if (!i2c_init_done) + iproc_i2c_init(bus_prvdata); + + regval = (chip_addr << 1); + iproc_i2c_reg_write(&base->mstr_datawr, regval); + regval = ((SMBUS_PROT_QUICK_CMD << CCB_SMB_MSTRSMBUSPROTO_SHIFT) | + (1 << CCB_SMB_MSTRSTARTBUSYCMD_SHIFT)); + iproc_i2c_reg_write(&base->mstr_cmd, regval); + + do { + udelay(100); + regval = iproc_i2c_reg_read(&base->mstr_cmd); + regval &= CCB_SMB_MSTRSTARTBUSYCMD_MASK; + } while (regval); + + regval = iproc_i2c_reg_read(&base->mstr_cmd); + + if ((regval & CCB_SMB_MSTRSTS_MASK) != 0) + return -1; + +#ifdef IPROC_I2C_DBG + iproc_dump_i2c_regs(bus_prvdata); + + debug("%s: chip probe successful\n", __func__); +#endif /* IPROC_I2C_DBG */ + + return 0; +} + +static int iproc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct iproc_i2c *bus_prvdata = dev_get_priv(bus); + + bus_prvdata->bus_speed = speed; + if (iproc_i2c_set_clk_freq(bus_prvdata)) + return -EINVAL; + + return 0; +} + +/** + * i2c_get_bus_speed - get i2c bus speed + * + * This function returns the speed of operation in Hz + */ +int iproc_i2c_get_bus_speed(struct udevice *bus) +{ + struct iproc_i2c *bus_prvdata = dev_get_priv(bus); + struct iproc_i2c_regs *base = bus_prvdata->base; + unsigned int regval; + unsigned int val; + + regval = iproc_i2c_reg_read(&base->timg_cfg); + val = GETREGFLDVAL(regval, CCB_SMB_TIMGCFG_MODE400_MASK, + CCB_SMB_TIMGCFG_MODE400_SHIFT); + switch (val) { + case 0: + return I2C_SPEED_100KHZ; + case 1: + return I2C_SPEED_400KHZ; + default: + return -EINVAL; + } + return -EINVAL; +} + +static int iproc_i2c_probe(struct udevice *bus) +{ + struct iproc_i2c *bus_prvdata = dev_get_priv(bus); + + return iproc_i2c_init(bus_prvdata); +} + +static int iproc_i2c_ofdata_to_platdata(struct udevice *bus) +{ + struct iproc_i2c *bus_prvdata = dev_get_priv(bus); + int node = dev_of_offset(bus); + const void *blob = gd->fdt_blob; + + bus_prvdata->base = map_physmem(devfdt_get_addr(bus), + sizeof(void *), + MAP_NOCACHE); + + /* default 100KHz freq */ + bus_prvdata->bus_speed = fdtdec_get_int(blob, node, "bus-frequency", + I2C_SPEED_100KHZ); + + return 0; +} + +static const struct dm_i2c_ops iproc_i2c_ops = { + .xfer = iproc_i2c_xfer, + .probe_chip = iproc_i2c_probe_chip, + .set_bus_speed = iproc_i2c_set_bus_speed, + .get_bus_speed = iproc_i2c_get_bus_speed, +}; + +static const struct udevice_id iproc_i2c_ids[] = { + { .compatible = "brcm,iproc-i2c" }, + { } +}; + +U_BOOT_DRIVER(iproc_i2c) = { + .name = "iproc_i2c", + .id = UCLASS_I2C, + .of_match = iproc_i2c_ids, + .ofdata_to_platdata = iproc_i2c_ofdata_to_platdata, + .probe = iproc_i2c_probe, + .priv_auto_alloc_size = sizeof(struct iproc_i2c), + .ops = &iproc_i2c_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/i2c/iproc_i2c.h b/drivers/i2c/iproc_i2c.h new file mode 100644 index 0000000000..4f8d6ba2b2 --- /dev/null +++ b/drivers/i2c/iproc_i2c.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (C) 2018 Broadcom */ + +#ifndef __IPROC_I2C_H__ +#define __IPROC_I2C_H__ + +#if (defined(CONFIG_NS_PLUS) || defined(CONFIG_HELIX4)) +#define SHADOW_CPY_BUFFER_ADDR1 0x70000000 +#define SHADOW_CPY_BUFFER_ADDR2 0x70100000 +#define IPROC_SMBUS_BASE_ADDR1 0x18038000 +#define IPROC_SMBUS_BASE_ADDR2 0x1803B000 +#elif (defined(CONFIG_CYGNUS)) +#define SHADOW_CPY_BUFFER_ADDR1 0x70000000 +#define SHADOW_CPY_BUFFER_ADDR2 0x70100000 +#define IPROC_SMBUS_BASE_ADDR1 0x18008000 +#define IPROC_SMBUS_BASE_ADDR2 0x1800B000 +#endif + +/* Registers */ +#define CCB_SMB_CFG_REG 0x0 + +#define CCB_SMB_CFG_RST_MASK 0x80000000 +#define CCB_SMB_CFG_RST_SHIFT 31 + +#define CCB_SMB_CFG_SMBEN_MASK 0x40000000 +#define CCB_SMB_CFG_SMBEN_SHIFT 30 + +#define CCB_SMB_CFG_BITBANGEN_MASK 0x20000000 +#define CCB_SMB_CFG_BITBANGEN_SHIFT 29 + +#define CCB_SMB_CFG_EN_NIC_SMBADDR0_MASK 0x10000000 +#define CCB_SMB_CFG_EN_NIC_SMBADDR0_SHIFT 28 + +#define CCB_SMB_CFG_PROMISCMODE_MASK 0x08000000 +#define CCB_SMB_CFG_PROMISCMODE_SHIFT 27 + +#define CCB_SMB_CFG_TSTMPCNTEN_MASK 0x04000000 +#define CCB_SMB_CFG_TSTMPCNTEN_SHIFT 26 + +#define CCB_SMB_CFG_MSTRRTRYCNT_MASK 0x000F0000 +#define CCB_SMB_CFG_MSTRRTRYCNT_SHIFT 16 + +#define CCB_SMB_TIMGCFG_REG 0x4 + +#define CCB_SMB_TIMGCFG_MODE400_MASK 0x80000000 +#define CCB_SMB_TIMGCFG_MODE400_SHIFT 31 + +#define CCB_SMB_TIMGCFG_RNDSLVSTR_MASK 0x7F000000 +#define CCB_SMB_TIMGCFG_RNDSLVSTR_SHIFT 24 + +#define CCB_SMB_TIMGCFG_PERSLVSTR_MASK 0x00FF0000 +#define CCB_SMB_TIMGCFG_PERSLVSTR_SHIFT 16 + +#define CCB_SMB_TIMGCFG_IDLTIME_MASK 0x0000FF00 +#define CCB_SMB_TIMGCFG_IDLTIME_SHIFT 8 + +#define CCB_SMB_ADDR_REG 0x8 + +#define CCB_SMB_EN_NIC_SMBADDR3_MASK 0x80000000 +#define CCB_SMB_EN_NIC_SMBADDR3_SHIFT 31 + +#define CCB_SMB_NIC_SMBADDR3_MASK 0x7F000000 +#define CCB_SMB_NIC_SMBADDR3_SHIFT 24 + +#define CCB_SMB_EN_NIC_SMBADDR2_MASK 0x00800000 +#define CCB_SMB_EN_NIC_SMBADDR2_SHIFT 23 + +#define CCB_SMB_NIC_SMBADDR2_MASK 0x007F0000 +#define CCB_SMB_NIC_SMBADDR2_SHIFT 16 + +#define CCB_SMB_EN_NIC_SMBADDR1_MASK 0x00008000 +#define CCB_SMB_EN_NIC_SMBADDR1_SHIFT 15 + +#define CCB_SMB_NIC_SMBADDR1_MASK 0x00007F00 +#define CCB_SMB_NIC_SMBADDR1_SHIFT 8 + +#define CCB_SMB_EN_NIC_SMBADDR0_MASK 0x00000080 +#define CCB_SMB_EN_NIC_SMBADDR0_SHIFT 7 + +#define CCB_SMB_NIC_SMBADDR0_MASK 0x0000007F +#define CCB_SMB_NIC_SMBADDR0_SHIFT 0 + +#define CCB_SMB_MSTRFIFOCTL_REG 0xC + +#define CCB_SMB_MSTRRXFIFOFLSH_MASK 0x80000000 +#define CCB_SMB_MSTRRXFIFOFLSH_SHIFT 31 + +#define CCB_SMB_MSTRTXFIFOFLSH_MASK 0x40000000 +#define CCB_SMB_MSTRTXFIFOFLSH_SHIFT 30 + +#define CCB_SMB_MSTRRXPKTCNT_MASK 0x007F0000 +#define CCB_SMB_MSTRRXPKTCNT_SHIFT 16 + +#define CCB_SMB_MSTRRXFIFOTHR_MASK 0x00003F00 +#define CCB_SMB_MSTRRXFIFOTHR_SHIFT 8 + +#define CCB_SMB_SLVFIFOCTL_REG 0x10 + +#define CCB_SMB_SLVRXFIFOFLSH_MASK 0x80000000 +#define CCB_SMB_SLVRXFIFOFLSH_SHIFT 31 + +#define CCB_SMB_SLVTXFIFOFLSH_MASK 0x40000000 +#define CCB_SMB_SLVTXFIFOFLSH_SHIFT 30 + +#define CCB_SMB_SLVRXPKTCNT_MASK 0x007F0000 +#define CCB_SMB_SLVRXPKTCNT_SHIFT 16 + +#define CCB_SMB_SLVRXFIFOTHR_MASK 0x00003F00 +#define CCB_SMB_SLVRXFIFOTHR_SHIFT 8 + +#define CCB_SMB_BITBANGCTL_REG 0x14 + +#define CCB_SMB_SMBCLKIN_MASK 0x80000000 +#define CCB_SMB_SMBCLKIN_SHIFT 31 + +#define CCB_SMB_SMBCLKOUTEN_MASK 0x40000000 +#define CCB_SMB_SMBCLKOUTEN_SHIFT 30 + +#define CCB_SMB_SMBDATAIN_MASK 0x20000000 +#define CCB_SMB_SMBDATAIN_SHIFT 29 + +#define CCB_SMB_SMBDATAOUTEN_MASK 0x10000000 +#define CCB_SMB_SMBDATAOUTEN_SHIFT 28 + +#define CCB_SMB_MSTRCMD_REG 0x30 + +#define CCB_SMB_MSTRSTARTBUSYCMD_MASK 0x80000000 +#define CCB_SMB_MSTRSTARTBUSYCMD_SHIFT 31 + +#define CCB_SMB_MSTRABORT_MASK 0x40000000 +#define CCB_SMB_MSTRABORT_SHIFT 30 + +#define CCB_SMB_MSTRSTS_MASK 0x0E000000 +#define CCB_SMB_MSTRSTS_SHIFT 25 + +#define CCB_SMB_MSTRSMBUSPROTO_MASK 0x00001E00 +#define CCB_SMB_MSTRSMBUSPROTO_SHIFT 9 + +#define CCB_SMB_MSTRPEC_MASK 0x00000100 +#define CCB_SMB_MSTRPEC_SHIFT 8 + +#define CCB_SMB_MSTRRDBYTECNT_MASK 0x000000FF +#define CCB_SMB_MSTRRDBYTECNT_SHIFT 0 + +#define CCB_SMB_SLVCMD_REG 0x34 + +#define CCB_SMB_SLVSTARTBUSYCMD_MASK 0x80000000 +#define CCB_SMB_SLVSTARTBUSYCMD_SHIFT 31 + +#define CCB_SMB_SLVABORT_MASK 0x40000000 +#define CCB_SMB_SLVABORT_SHIFT 30 + +#define CCB_SMB_SLVSTS_MASK 0x03800000 +#define CCB_SMB_SLVSTS_SHIFT 23 + +#define CCB_SMB_SLVPEC_MASK 0x00000100 +#define CCB_SMB_SLVPEC_SHIFT 8 + +#define CCB_SMB_EVTEN_REG 0x38 + +#define CCB_SMB_MSTRRXFIFOFULLEN_MASK 0x80000000 +#define CCB_SMB_MSTRRXFIFOFULLEN_SHIFT 31 + +#define CCB_SMB_MSTRRXFIFOTHRHITEN_MASK 0x40000000 +#define CCB_SMB_MSTRRXFIFOTHRHITEN_SHIFT 30 + +#define CCB_SMB_MSTRRXEVTEN_MASK 0x20000000 +#define CCB_SMB_MSTRRXEVTEN_SHIFT 29 + +#define CCB_SMB_MSTRSTARTBUSYEN_MASK 0x10000000 +#define CCB_SMB_MSTRSTARTBUSYEN_SHIFT 28 + +#define CCB_SMB_MSTRTXUNDEN_MASK 0x08000000 +#define CCB_SMB_MSTRTXUNDEN_SHIFT 27 + +#define CCB_SMB_SLVRXFIFOFULLEN_MASK 0x04000000 +#define CCB_SMB_SLVRXFIFOFULLEN_SHIFT 26 + +#define CCB_SMB_SLVRXFIFOTHRHITEN_MASK 0x02000000 +#define CCB_SMB_SLVRXFIFOTHRHITEN_SHIFT 25 + +#define CCB_SMB_SLVRXEVTEN_MASK 0x01000000 +#define CCB_SMB_SLVRXEVTEN_SHIFT 24 + +#define CCB_SMB_SLVSTARTBUSYEN_MASK 0x00800000 +#define CCB_SMB_SLVSTARTBUSYEN_SHIFT 23 + +#define CCB_SMB_SLVTXUNDEN_MASK 0x00400000 +#define CCB_SMB_SLVTXUNDEN_SHIFT 22 + +#define CCB_SMB_SLVRDEVTEN_MASK 0x00200000 +#define CCB_SMB_SLVRDEVTEN_SHIFT 21 + +#define CCB_SMB_EVTSTS_REG 0x3C + +#define CCB_SMB_MSTRRXFIFOFULLSTS_MASK 0x80000000 +#define CCB_SMB_MSTRRXFIFOFULLSTS_SHIFT 31 + +#define CCB_SMB_MSTRRXFIFOTHRHITSTS_MASK 0x40000000 +#define CCB_SMB_MSTRRXFIFOTHRHITSTS_SHIFT 30 + +#define CCB_SMB_MSTRRXEVTSTS_MASK 0x20000000 +#define CCB_SMB_MSTRRXEVTSTS_SHIFT 29 + +#define CCB_SMB_MSTRSTARTBUSYSTS_MASK 0x10000000 +#define CCB_SMB_MSTRSTARTBUSYSTS_SHIFT 28 + +#define CCB_SMB_MSTRTXUNDSTS_MASK 0x08000000 +#define CCB_SMB_MSTRTXUNDSTS_SHIFT 27 + +#define CCB_SMB_SLVRXFIFOFULLSTS_MASK 0x04000000 +#define CCB_SMB_SLVRXFIFOFULLSTS_SHIFT 26 + +#define CCB_SMB_SLVRXFIFOTHRHITSTS_MASK 0x02000000 +#define CCB_SMB_SLVRXFIFOTHRHITSTS_SHIFT 25 + +#define CCB_SMB_SLVRXEVTSTS_MASK 0x01000000 +#define CCB_SMB_SLVRXEVTSTS_SHIFT 24 + +#define CCB_SMB_SLVSTARTBUSYSTS_MASK 0x00800000 +#define CCB_SMB_SLVSTARTBUSYSTS_SHIFT 23 + +#define CCB_SMB_SLVTXUNDSTS_MASK 0x00400000 +#define CCB_SMB_SLVTXUNDSTS_SHIFT 22 + +#define CCB_SMB_SLVRDEVTSTS_MASK 0x00200000 +#define CCB_SMB_SLVRDEVTSTS_SHIFT 21 + +#define CCB_SMB_MSTRDATAWR_REG 0x40 + +#define CCB_SMB_MSTRWRSTS_MASK 0x80000000 +#define CCB_SMB_MSTRWRSTS_SHIFT 31 + +#define CCB_SMB_MSTRWRDATA_MASK 0x000000FF +#define CCB_SMB_MSTRWRDATA_SHIFT 0 + +#define CCB_SMB_MSTRDATARD_REG 0x44 + +#define CCB_SMB_MSTRRDSTS_MASK 0xC0000000 +#define CCB_SMB_MSTRRDSTS_SHIFT 30 + +#define CCB_SMB_MSTRRDPECERR_MASK 0x20000000 +#define CCB_SMB_MSTRRDPECERR_SHIFT 29 + +#define CCB_SMB_MSTRRDDATA_MASK 0x000000FF +#define CCB_SMB_MSTRRDDATA_SHIFT 0 + +#define CCB_SMB_SLVDATAWR_REG 0x48 + +#define CCB_SMB_SLVWRSTS_MASK 0x80000000 +#define CCB_SMB_SLVWRSTS_SHIFT 31 + +#define CCB_SMB_SLVWRDATA_MASK 0x000000FF +#define CCB_SMB_SLVWRDATA_SHIFT 0 + +#define CCB_SMB_SLVDATARD_REG 0x4C + +#define CCB_SMB_SLVRDSTS_MASK 0xC0000000 +#define CCB_SMB_SLVRDSTS_SHIFT 30 + +#define CCB_SMB_SLVRDERRSTS_MASK 0x30000000 +#define CCB_SMB_SLVRDERRSTS_SHIFT 28 + +#define CCB_SMB_SLVRDDATA_MASK 0x000000FF +#define CCB_SMB_SLVRDDATA_SHIFT 0 + +/* --Registers-- */ + +/* Transaction error codes defined in Master command register (0x30) */ +#define MSTR_STS_XACT_SUCCESS 0 +#define MSTR_STS_LOST_ARB 1 +#define MSTR_STS_NACK_FIRST_BYTE 2 + +/* NACK on a byte other than + * the first byte + */ +#define MSTR_STS_NACK_NON_FIRST_BYTE 3 + +#define MSTR_STS_TTIMEOUT_EXCEEDED 4 +#define MSTR_STS_TX_TLOW_MEXT_EXCEEDED 5 +#define MSTR_STS_RX_TLOW_MEXT_EXCEEDED 6 + +/* SMBUS protocol values defined in register 0x30 */ +#define SMBUS_PROT_QUICK_CMD 0 +#define SMBUS_PROT_SEND_BYTE 1 +#define SMBUS_PROT_RECV_BYTE 2 +#define SMBUS_PROT_WR_BYTE 3 +#define SMBUS_PROT_RD_BYTE 4 +#define SMBUS_PROT_WR_WORD 5 +#define SMBUS_PROT_RD_WORD 6 +#define SMBUS_PROT_BLK_WR 7 +#define SMBUS_PROT_BLK_RD 8 +#define SMBUS_PROT_PROC_CALL 9 +#define SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL 10 + +/* SMBUS Block speed mode */ +#define SMBUS_BLOCK_MODE_100 0 +#define SMBUS_BLOCK_MODE_400 1 + +#define BUS_BUSY_COUNT 100000 /* Number can be changed later */ +#define IPROC_I2C_INVALID_ADDR 0xFF +#define IPROC_SMB_MAX_RETRIES 35 +#define I2C_SMBUS_BLOCK_MAX 32 +#define GETREGFLDVAL(regval, mask, startbit) \ + (((regval) & (mask)) >> (startbit)) +#define SETREGFLDVAL(regval, fldval, mask, startbit) (regval) = \ + ((regval) & ~(mask)) | \ + ((fldval) << (startbit)) + +/* Enum to specify clock speed. The user will provide it during initialization + * If needed, it can be changed dynamically + */ +enum iproc_smb_clk_freq { + I2C_SPEED_100KHZ = 100000, + I2C_SPEED_400KHZ = 400000, + I2C_SPEED_INVALID = 255 +}; + +/* This enum will be used to notify the user of status of a data transfer + * request + */ +enum iproc_smb_error_code { + I2C_NO_ERR = 0, + I2C_TIMEOUT_ERR = 1, + + /* Invalid parameter(s) passed to the driver */ + I2C_INVALID_PARAM_ERR = 2, + + /* The driver API was called before the present + * transfer was completed + */ + I2C_OPER_IN_PROGRESS = 3, + + /* Transfer aborted unexpectedly, for example a NACK + * received, before last byte was read/written + */ + I2C_OPER_ABORT_ERR = 4, + + /* Feature or function not supported + * (e.g., 10-bit addresses, or clock speeds + * other than 100KHz, 400KHz) + */ + I2C_FUNC_NOT_SUPPORTED = 5, +}; + +/* Structure used to pass information to read/write functions. */ +struct iproc_xact_info { + unsigned char command; + unsigned char *data; + unsigned int size; + unsigned short flags; /* used for specifying PEC, 10-bit addresses */ + unsigned char smb_proto; /* SMBus protocol */ + unsigned int cmd_valid; /* true if command is valid else false */ +}; + +#endif /* __IPROC_I2C_H__ */ -- 2.17.1

3 3

[U-Boot] [PATCH v4 0/3] env: Add CONFIG_ENV_FULL_SUPPORT
by Patrick Delaunay 18 Mar '20

18 Mar '20

Hi, This patchset follow http://patchwork.ozlabs.org/project/uboot/list/?series=131268&state=* It follow the first proposal http://patchwork.ozlabs.org/project/uboot/list/?series=129339 "env: Add CONFIG_ENV_SUPPORT" The first patch of the serie only solves the regression introduced by commit 7d4776545b0f ("env: solve compilation error in SPL"); change_ok was always NULL in U-Boot. See "U-Boot: Environment flags broken for U-Boot" mail http://u-boot.10912.n7.nabble.com/U-Boot-Environment-flags-broken-for-U-Boo… This first patch can be integrated in master branch for v2019.10 as requested Tom Rimi. The next patches of the serie is a proposal after Wolfgang Denk review on the first proposal: I make the env support coherent between U-Boot, SPL and TPL. I need to change many defconfig (to add CONFIG_(SPL/TPL)_ENV_IS_NOWHERE) because I modify the dependency between the CONFIG used by SPL. Moreover the size of SPL increase this last patch. So to avoid to increase the SPL and TPL size, I also allow to have empty default environment with the new options CONFIG_$(SPL_TPL_)ENV_DEFAULT Today the last buildman result is : 02: env: Add CONFIG_ENV_FULL_SUPPORT arm: + smartweb +/local/home/frq07632/.buildman-toolchains/gcc-7.3.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ld.bfd: u-boot-spl section `.u_boot_list' will not fit in region `.sram' +/local/home/frq07632/.buildman-toolchains/gcc-7.3.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ld.bfd: SPL image too big +/local/home/frq07632/.buildman-toolchains/gcc-7.3.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 56 bytes +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 x86: (for 26/26 boards) all -23.5 bss -7.4 spl/u-boot-spl:all -226.7 spl/u-boot-spl:data +0.9 spl/u-boot-spl:rodata -228.6 spl/u-boot-spl:text +1.0 text -16.1 aarch64: (for 225/225 boards) all +0.1 rodata +0.1 spl/u-boot-spl:all -33.3 spl/u-boot-spl:bss -0.1 spl/u-boot-spl:data +18.0 spl/u-boot-spl:rodata -64.3 spl/u-boot-spl:text +13.2 powerpc: (for 309/309 boards) spl/u-boot-spl:all -338.8 spl/u-boot-spl:data -338.8 sandbox: (for 6/6 boards) all -46.7 rodata +16.0 spl/u-boot-spl:all -496.0 spl/u-boot-spl:rodata -496.0 text -62.7 microblaze: (for 1/1 boards) all +4.0 bss +100.0 data -4.0 rodata -8.0 spl/u-boot-spl:all +1136.0 spl/u-boot-spl:bss -8.0 spl/u-boot-spl:data +24.0 spl/u-boot-spl:rodata +1092.0 spl/u-boot-spl:text +28.0 text -84.0 arm: (for 689/689 boards) all -0.1 bss +0.1 rodata +0.1 spl/u-boot-spl:all -131.3 spl/u-boot-spl:data +12.9 spl/u-boot-spl:rodata -154.7 spl/u-boot-spl:text +10.5 text -0.3 With this patch I gain on the rodata size in spl for many targets. But I need to be sure that have a empty default environment in SPL/TPL by default is normal for all architecture/boards. Do you think I need to reactivate it by default the CONFIG for SPL and deactivated only on some target. Any remarks are welcome. Best regards. Patrick Delaunay. Changes in v4: - Add CONFIG_$(SPL_TPL_)ENV_DEFAULT: empty default environment when not activated Changes in v3: - It is a version 3 of http://patchwork.ozlabs.org/project/uboot/list/?series=129339 "env: Add CONFIG_ENV_SUPPORT" after Tom Rimi and Wolfgang Denk remarks Changes in v2: - Add comment for ENV_IS_IN_SOMEWHERE - Update commit message after Lukasz Majewki review Patrick Delaunay (3): env: correct the check of env_flags_validate presence env: introduce macro ENV_IS_IN_SOMEWHERE env: Add CONFIG_ENV_FULL_SUPPORT arch/arm/mach-omap2/Kconfig | 1 - arch/arm/mach-omap2/am33xx/Kconfig | 2 -- board/birdland/bav335x/board.c | 2 +- board/gateworks/gw_ventana/gw_ventana_spl.c | 2 +- board/liebherr/display5/spl.c | 4 +-- board/tcl/sl50/board.c | 2 +- board/ti/am335x/board.c | 2 +- board/ti/am57xx/board.c | 2 +- board/ti/dra7xx/evm.c | 2 +- cmd/Kconfig | 2 ++ cmd/nvedit.c | 27 +++------------ common/spl/Kconfig | 20 ----------- common/spl/spl_ext.c | 2 +- common/spl/spl_fat.c | 2 +- configs/A10-OLinuXino-Lime_defconfig | 1 + configs/A10s-OLinuXino-M_defconfig | 1 + configs/A13-OLinuXinoM_defconfig | 1 + configs/A13-OLinuXino_defconfig | 1 + configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 + configs/A20-OLinuXino-Lime2_defconfig | 1 + configs/A20-OLinuXino-Lime_defconfig | 1 + configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 + configs/A20-OLinuXino_MICRO_defconfig | 1 + configs/A20-Olimex-SOM-EVB_defconfig | 1 + configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 + configs/A20-Olimex-SOM204-EVB_defconfig | 1 + configs/A33-OLinuXino_defconfig | 1 + configs/Ainol_AW1_defconfig | 1 + configs/Ampe_A76_defconfig | 1 + configs/Auxtek-T003_defconfig | 1 + configs/Auxtek-T004_defconfig | 1 + configs/B4420QDS_NAND_defconfig | 1 - configs/B4860QDS_NAND_defconfig | 1 - configs/BSC9131RDB_NAND_SYSCLK100_defconfig | 1 + configs/BSC9131RDB_NAND_defconfig | 1 + configs/BSC9132QDS_NAND_DDRCLK100_defconfig | 1 + configs/BSC9132QDS_NAND_DDRCLK133_defconfig | 1 + configs/Bananapi_M2_Ultra_defconfig | 1 + configs/Bananapi_defconfig | 1 + configs/Bananapi_m2m_defconfig | 1 + configs/Bananapro_defconfig | 1 + configs/C29XPCIE_NAND_defconfig | 2 +- configs/CHIP_pro_defconfig | 1 + configs/CSQ_CS908_defconfig | 1 + configs/Chuwi_V7_CW0825_defconfig | 1 + configs/Colombus_defconfig | 1 + configs/Cubieboard2_defconfig | 1 + configs/Cubieboard4_defconfig | 1 + configs/Cubieboard_defconfig | 1 + configs/Cubietruck_defconfig | 1 + configs/Cubietruck_plus_defconfig | 1 + configs/Empire_electronix_d709_defconfig | 1 + configs/Empire_electronix_m712_defconfig | 1 + configs/Hummingbird_A31_defconfig | 1 + configs/Hyundai_A7HD_defconfig | 1 + configs/Itead_Ibox_A20_defconfig | 1 + configs/Lamobo_R1_defconfig | 1 + configs/LicheePi_Zero_defconfig | 1 + configs/Linksprite_pcDuino3_Nano_defconfig | 1 + configs/Linksprite_pcDuino3_defconfig | 1 + configs/Linksprite_pcDuino_defconfig | 1 + configs/MK808C_defconfig | 1 + configs/MPC8313ERDB_NAND_33_defconfig | 1 + configs/MPC8313ERDB_NAND_66_defconfig | 1 + configs/MSI_Primo73_defconfig | 1 + configs/MSI_Primo81_defconfig | 1 + configs/Marsboard_A10_defconfig | 1 + configs/Mele_A1000G_quad_defconfig | 1 + configs/Mele_A1000_defconfig | 1 + configs/Mele_I7_defconfig | 1 + configs/Mele_M3_defconfig | 1 + configs/Mele_M5_defconfig | 1 + configs/Mele_M9_defconfig | 1 + configs/Merrii_A80_Optimus_defconfig | 1 + configs/Mini-X_defconfig | 1 + configs/Orangepi_defconfig | 1 + configs/Orangepi_mini_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 - configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 - configs/P1010RDB-PA_NAND_defconfig | 2 +- configs/P1010RDB-PA_SDCARD_defconfig | 1 - configs/P1010RDB-PA_SPIFLASH_defconfig | 1 - configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 - configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 - configs/P1010RDB-PB_NAND_defconfig | 2 +- configs/P1010RDB-PB_SDCARD_defconfig | 1 - configs/P1010RDB-PB_SPIFLASH_defconfig | 1 - configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 1 - configs/P1020MBG-PC_SDCARD_defconfig | 1 - configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 +- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 - configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 - configs/P1020RDB-PC_NAND_defconfig | 2 +- configs/P1020RDB-PC_SDCARD_defconfig | 1 - configs/P1020RDB-PC_SPIFLASH_defconfig | 1 - configs/P1020RDB-PD_NAND_defconfig | 2 +- configs/P1020RDB-PD_SDCARD_defconfig | 1 - configs/P1020RDB-PD_SPIFLASH_defconfig | 1 - configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 1 - configs/P1020UTM-PC_SDCARD_defconfig | 1 - configs/P1021RDB-PC_36BIT_NAND_defconfig | 2 +- configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 1 - configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 1 - configs/P1021RDB-PC_NAND_defconfig | 2 +- configs/P1021RDB-PC_SDCARD_defconfig | 1 - configs/P1021RDB-PC_SPIFLASH_defconfig | 1 - configs/P1022DS_36BIT_NAND_defconfig | 2 +- configs/P1022DS_36BIT_SDCARD_defconfig | 1 - configs/P1022DS_36BIT_SPIFLASH_defconfig | 1 - configs/P1022DS_NAND_defconfig | 2 +- configs/P1022DS_SDCARD_defconfig | 1 - configs/P1022DS_SPIFLASH_defconfig | 1 - configs/P1024RDB_NAND_defconfig | 2 +- configs/P1024RDB_SDCARD_defconfig | 1 - configs/P1024RDB_SPIFLASH_defconfig | 1 - configs/P1025RDB_NAND_defconfig | 2 +- configs/P1025RDB_SDCARD_defconfig | 1 - configs/P1025RDB_SPIFLASH_defconfig | 1 - configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 - configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 - configs/P2020RDB-PC_NAND_defconfig | 2 +- configs/P2020RDB-PC_SDCARD_defconfig | 1 - configs/P2020RDB-PC_SPIFLASH_defconfig | 1 - configs/Sinlinx_SinA31s_defconfig | 1 + configs/Sinlinx_SinA33_defconfig | 1 + configs/Sinovoip_BPI_M2_defconfig | 1 + configs/Sinovoip_BPI_M3_defconfig | 1 + configs/Sunchip_CX-A99_defconfig | 1 + configs/T1023RDB_NAND_defconfig | 1 - configs/T1023RDB_SDCARD_defconfig | 1 - configs/T1023RDB_SPIFLASH_defconfig | 1 - configs/T1024QDS_NAND_defconfig | 1 - configs/T1024QDS_SDCARD_defconfig | 1 - configs/T1024QDS_SPIFLASH_defconfig | 1 - configs/T1024RDB_NAND_defconfig | 1 - configs/T1024RDB_SDCARD_defconfig | 1 - configs/T1024RDB_SPIFLASH_defconfig | 1 - configs/T1040D4RDB_NAND_defconfig | 1 - configs/T1040D4RDB_SDCARD_defconfig | 1 - configs/T1040D4RDB_SPIFLASH_defconfig | 1 - configs/T1040RDB_NAND_defconfig | 1 - configs/T1040RDB_SDCARD_defconfig | 1 - configs/T1040RDB_SPIFLASH_defconfig | 1 - configs/T1042D4RDB_NAND_defconfig | 1 - configs/T1042D4RDB_SDCARD_defconfig | 1 - configs/T1042D4RDB_SPIFLASH_defconfig | 1 - .../T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 1 - configs/T1042RDB_PI_NAND_defconfig | 1 - configs/T1042RDB_PI_SDCARD_defconfig | 1 - configs/T1042RDB_PI_SPIFLASH_defconfig | 1 - configs/T2080QDS_NAND_defconfig | 1 - configs/T2080QDS_SDCARD_defconfig | 1 - configs/T2080QDS_SPIFLASH_defconfig | 1 - configs/T2080RDB_NAND_defconfig | 1 - configs/T2080RDB_SDCARD_defconfig | 1 - configs/T2080RDB_SPIFLASH_defconfig | 1 - configs/T2081QDS_NAND_defconfig | 1 - configs/T2081QDS_SDCARD_defconfig | 1 - configs/T2081QDS_SPIFLASH_defconfig | 1 - configs/T4160QDS_NAND_defconfig | 1 - configs/T4160QDS_SDCARD_defconfig | 1 - configs/T4240QDS_NAND_defconfig | 1 - configs/T4240QDS_SDCARD_defconfig | 1 - configs/T4240RDB_SDCARD_defconfig | 1 - configs/UTOO_P66_defconfig | 1 + configs/Wexler_TAB7200_defconfig | 1 + configs/Wits_Pro_A20_DKT_defconfig | 1 + configs/Wobo_i5_defconfig | 1 + configs/Yones_Toptech_BD1078_defconfig | 1 + configs/Yones_Toptech_BS1078_V2_defconfig | 1 + configs/a64-olinuxino_defconfig | 1 + configs/ae350_rv32_xip_defconfig | 1 + configs/alt_defconfig | 1 + configs/am335x_guardian_defconfig | 1 - configs/am335x_hs_evm_defconfig | 2 +- configs/am335x_hs_evm_uart_defconfig | 2 +- configs/am335x_igep003x_defconfig | 1 + configs/am335x_shc_defconfig | 1 + configs/am335x_shc_ict_defconfig | 1 + configs/am335x_shc_netboot_defconfig | 1 - configs/am335x_shc_sdboot_defconfig | 1 + configs/am335x_sl50_defconfig | 1 - configs/am3517_crane_defconfig | 1 + configs/am3517_evm_defconfig | 1 + configs/am65x_evm_a53_defconfig | 1 + configs/am65x_evm_r5_defconfig | 1 + configs/am65x_hs_evm_a53_defconfig | 1 + configs/am65x_hs_evm_r5_defconfig | 1 + configs/amarula_a64_relic_defconfig | 1 + configs/apalis-tk1_defconfig | 1 + configs/apalis_imx6_defconfig | 1 + configs/apalis_t30_defconfig | 1 + configs/apf27_defconfig | 1 + configs/apx4devkit_defconfig | 1 + configs/arndale_defconfig | 1 + configs/axm_defconfig | 1 + configs/ba10_tv_box_defconfig | 1 + configs/bananapi_m1_plus_defconfig | 1 + configs/bananapi_m2_berry_defconfig | 1 + configs/bananapi_m2_plus_h3_defconfig | 1 + configs/bananapi_m2_plus_h5_defconfig | 1 + configs/bananapi_m2_zero_defconfig | 1 + configs/bananapi_m64_defconfig | 1 + configs/beaver_defconfig | 1 + configs/beelink_gs1_defconfig | 1 + configs/beelink_x2_defconfig | 1 + configs/bitmain_antminer_s9_defconfig | 1 + configs/brppt1_mmc_defconfig | 1 + configs/brppt1_nand_defconfig | 1 + configs/brppt1_spi_defconfig | 1 + configs/brsmarc1_defconfig | 1 + configs/brxre1_defconfig | 1 + configs/cairo_defconfig | 1 + configs/cardhu_defconfig | 1 + configs/cei-tk1-som_defconfig | 1 + configs/cgtqmx6eval_defconfig | 1 + configs/chiliboard_defconfig | 1 + configs/chromebook_bob_defconfig | 1 + configs/chromebook_link64_defconfig | 1 - configs/chromebook_samus_tpl_defconfig | 2 ++ configs/ci20_mmc_defconfig | 1 + configs/cl-som-imx7_defconfig | 1 + configs/clearfog_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/cm_t335_defconfig | 1 + configs/cm_t35_defconfig | 1 + configs/cm_t43_defconfig | 1 + configs/colibri_imx6_defconfig | 1 + configs/colibri_t20_defconfig | 1 + configs/colibri_t30_defconfig | 1 + configs/colorfly_e708_q1_defconfig | 1 + configs/controlcenterdc_defconfig | 1 + configs/corvus_defconfig | 1 + configs/da850evm_defconfig | 1 + configs/da850evm_nand_defconfig | 1 + configs/dalmore_defconfig | 1 + configs/db-88f6720_defconfig | 1 + configs/db-88f6820-amc_defconfig | 1 + configs/db-88f6820-gp_defconfig | 1 + configs/db-mv784mp-gp_defconfig | 1 + configs/devkit3250_defconfig | 1 + configs/devkit8000_defconfig | 1 + configs/dh_imx6_defconfig | 1 + configs/difrnce_dit4350_defconfig | 1 + configs/display5_defconfig | 1 - configs/display5_factory_defconfig | 1 + configs/draco_defconfig | 1 + configs/ds414_defconfig | 1 + configs/dserve_dsrv9703c_defconfig | 1 + configs/edminiv2_defconfig | 1 + configs/emlid_neutis_n5_devboard_defconfig | 1 + configs/etamin_defconfig | 1 + configs/evb-px5_defconfig | 2 ++ configs/evb-rk3229_defconfig | 2 ++ configs/evb-rk3288_defconfig | 2 ++ configs/evb-rk3328_defconfig | 2 ++ configs/evb-rk3399_defconfig | 2 ++ configs/ficus-rk3399_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/firefly-rk3399_defconfig | 2 ++ configs/ga10h_v1_1_defconfig | 1 + .../gardena-smart-gateway-at91sam_defconfig | 1 + configs/gose_defconfig | 1 + configs/gt90h_v4_defconfig | 1 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + configs/h8_homlet_v2_defconfig | 1 + configs/harmony_defconfig | 1 + configs/helios4_defconfig | 1 + configs/i12-tvbox_defconfig | 1 + configs/iNet_3F_defconfig | 1 + configs/iNet_3W_defconfig | 1 + configs/iNet_86VS_defconfig | 1 + configs/iNet_D978_rev2_defconfig | 1 + configs/icnova-a20-swac_defconfig | 1 + configs/igep00x0_defconfig | 1 + configs/imx6dl_icore_nand_defconfig | 1 + configs/imx6dl_mamoj_defconfig | 1 + configs/imx6q_icore_nand_defconfig | 1 + configs/imx6q_logic_defconfig | 1 + configs/imx6qdl_icore_mipi_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + configs/imx6qdl_icore_rqs_defconfig | 1 + configs/imx6ul_geam_mmc_defconfig | 1 + configs/imx6ul_geam_nand_defconfig | 1 + configs/imx6ul_isiot_emmc_defconfig | 1 + configs/imx6ul_isiot_nand_defconfig | 1 + configs/imx8mq_evk_defconfig | 1 + configs/imx8qm_mek_defconfig | 1 + configs/imx8qxp_mek_defconfig | 1 + configs/inet1_defconfig | 1 + configs/inet86dz_defconfig | 1 + configs/inet97fv2_defconfig | 1 + configs/inet98v_rev2_defconfig | 1 + configs/inet9f_rev03_defconfig | 1 + configs/inet_q972_defconfig | 1 + configs/j721e_evm_r5_defconfig | 1 - configs/jesurun_q5_defconfig | 1 + configs/jetson-tk1_defconfig | 1 + configs/k2e_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/khadas-edge-captain-rk3399_defconfig | 2 ++ configs/khadas-edge-rk3399_defconfig | 2 ++ configs/khadas-edge-v-rk3399_defconfig | 2 ++ configs/koelsch_defconfig | 1 + configs/kp_imx6q_tpc_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/lager_defconfig | 1 + configs/libretech_all_h3_cc_h2_plus_defconfig | 1 + configs/libretech_all_h3_cc_h3_defconfig | 1 + configs/libretech_all_h3_cc_h5_defconfig | 1 + configs/lion-rk3368_defconfig | 2 ++ configs/liteboard_defconfig | 1 + configs/ls1021aiot_sdcard_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 - configs/ls1021aqds_sdcard_ifc_defconfig | 1 - configs/ls1021aqds_sdcard_qspi_defconfig | 1 - configs/ls1021atsn_sdcard_defconfig | 1 - ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 - configs/ls1021atwr_sdcard_ifc_defconfig | 1 - configs/ls1021atwr_sdcard_qspi_defconfig | 1 - configs/ls1043aqds_nand_defconfig | 1 - configs/ls1043aqds_sdcard_ifc_defconfig | 1 - configs/ls1043aqds_sdcard_qspi_defconfig | 1 - configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 - configs/ls1043ardb_nand_defconfig | 1 - .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 - configs/ls1043ardb_sdcard_defconfig | 1 - configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 - configs/ls1046aqds_sdcard_qspi_defconfig | 1 - configs/ls1046ardb_emmc_defconfig | 1 - configs/ls1046ardb_qspi_spl_defconfig | 1 - .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 - configs/ls1046ardb_sdcard_defconfig | 1 - configs/ls1088aqds_sdcard_ifc_defconfig | 1 - configs/ls1088aqds_sdcard_qspi_defconfig | 1 - ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 - configs/ls1088ardb_sdcard_qspi_defconfig | 1 - configs/ls2080aqds_nand_defconfig | 1 - configs/ls2080aqds_sdcard_defconfig | 1 - configs/ls2080ardb_nand_defconfig | 1 - configs/m53menlo_defconfig | 1 + configs/maxbcm_defconfig | 1 + configs/mccmon6_nor_defconfig | 1 - configs/mccmon6_sd_defconfig | 1 - configs/medcom-wide_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/mixtile_loftq_defconfig | 1 + configs/mk802_a10s_defconfig | 1 + configs/mk802_defconfig | 1 + configs/mk802ii_defconfig | 1 + configs/mx23_olinuxino_defconfig | 1 + configs/mx23evk_defconfig | 1 + configs/mx28evk_auart_console_defconfig | 1 + configs/mx28evk_defconfig | 1 + configs/mx28evk_nand_defconfig | 1 + configs/mx31pdk_defconfig | 1 + configs/mx6cuboxi_defconfig | 1 + configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6sxsabresd_spl_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/nanopc-t4-rk3399_defconfig | 2 ++ configs/nanopi-m4-rk3399_defconfig | 2 ++ configs/nanopi-neo4-rk3399_defconfig | 2 ++ configs/nanopi_a64_defconfig | 1 + configs/nanopi_m1_defconfig | 1 + configs/nanopi_m1_plus_defconfig | 1 + configs/nanopi_neo2_defconfig | 1 + configs/nanopi_neo_air_defconfig | 1 + configs/nanopi_neo_defconfig | 1 + configs/nanopi_neo_plus2_defconfig | 1 + configs/novena_defconfig | 1 + configs/nyan-big_defconfig | 1 + configs/oceanic_5205_5inmfd_defconfig | 1 + configs/omap35_logic_defconfig | 1 + configs/omap35_logic_somlv_defconfig | 1 + configs/omap3_beagle_defconfig | 1 + configs/omap3_evm_defconfig | 1 + configs/omap3_ha_defconfig | 1 + configs/omap3_logic_defconfig | 1 + configs/omap3_logic_somlv_defconfig | 1 + configs/omap3_overo_defconfig | 1 + configs/omap4_panda_defconfig | 1 + configs/omap4_sdp4430_defconfig | 1 + configs/omapl138_lcdk_defconfig | 1 + configs/opos6uldev_defconfig | 1 - configs/orangepi-rk3399_defconfig | 2 ++ configs/orangepi_2_defconfig | 1 + configs/orangepi_lite2_defconfig | 1 + configs/orangepi_lite_defconfig | 1 + configs/orangepi_one_defconfig | 1 + configs/orangepi_one_plus_defconfig | 1 + configs/orangepi_pc2_defconfig | 1 + configs/orangepi_pc_defconfig | 1 + configs/orangepi_pc_plus_defconfig | 1 + configs/orangepi_plus2e_defconfig | 1 + configs/orangepi_plus_defconfig | 1 + configs/orangepi_prime_defconfig | 1 + configs/orangepi_r1_defconfig | 1 + configs/orangepi_win_defconfig | 1 + configs/orangepi_zero_defconfig | 1 + configs/orangepi_zero_plus2_defconfig | 1 + configs/orangepi_zero_plus_defconfig | 1 + configs/origen_defconfig | 1 + configs/ot1200_spl_defconfig | 1 + configs/parrot_r16_defconfig | 1 + configs/paz00_defconfig | 1 + configs/pcm051_rev1_defconfig | 1 - configs/pcm051_rev3_defconfig | 1 - configs/pcm058_defconfig | 1 + configs/peach-pi_defconfig | 1 + configs/peach-pit_defconfig | 1 + configs/pengwyn_defconfig | 1 - configs/phycore-am335x-r2-wega_defconfig | 1 + configs/phycore-rk3288_defconfig | 1 + configs/pico-hobbit-imx6ul_defconfig | 1 + configs/pico-hobbit-imx7d_defconfig | 1 + configs/pico-imx6ul_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + configs/pico-pi-imx6ul_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 1 + configs/picosam9g45_defconfig | 1 + configs/pine64-lts_defconfig | 1 + configs/pine64_plus_defconfig | 1 + configs/pine_h64_defconfig | 1 + configs/pinebook_defconfig | 1 + configs/platinum_picon_defconfig | 1 + configs/platinum_titanium_defconfig | 1 + configs/plutux_defconfig | 1 + configs/polaroid_mid2407pxe03_defconfig | 1 + configs/polaroid_mid2809pxe04_defconfig | 1 + configs/popmetal-rk3288_defconfig | 1 + configs/porter_defconfig | 1 + configs/pov_protab2_ips9_defconfig | 1 + configs/puma-rk3399_defconfig | 1 + configs/pxm2_defconfig | 1 + configs/q8_a13_tablet_defconfig | 1 + configs/q8_a23_tablet_800x480_defconfig | 1 + configs/q8_a33_tablet_1024x600_defconfig | 1 + configs/q8_a33_tablet_800x480_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 - configs/r7-tv-dongle_defconfig | 1 + configs/r8a7795_salvator-x_defconfig | 1 + configs/r8a7795_ulcb_defconfig | 1 + configs/r8a77965_salvator-x_defconfig | 1 + configs/r8a77965_ulcb_defconfig | 1 + configs/r8a7796_salvator-x_defconfig | 1 + configs/r8a7796_ulcb_defconfig | 1 + configs/r8a77970_eagle_defconfig | 1 + configs/r8a77980_condor_defconfig | 1 + configs/r8a77990_ebisu_defconfig | 1 + configs/r8a77995_draak_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/riotboard_spl_defconfig | 1 + configs/roc-rk3399-pc_defconfig | 2 ++ configs/rock-pi-4-rk3399_defconfig | 2 ++ configs/rock2_defconfig | 1 + configs/rock64-rk3328_defconfig | 2 ++ configs/rock960-rk3399_defconfig | 1 + configs/rock_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 2 ++ configs/rut_defconfig | 1 + configs/sama5d27_som1_ek_mmc1_defconfig | 1 + configs/sama5d27_som1_ek_mmc_defconfig | 1 + configs/sama5d27_som1_ek_qspiflash_defconfig | 1 + configs/sama5d2_icp_mmc_defconfig | 1 + configs/sama5d2_xplained_emmc_defconfig | 1 + configs/sama5d2_xplained_mmc_defconfig | 1 + configs/sama5d2_xplained_qspiflash_defconfig | 1 + configs/sama5d2_xplained_spiflash_defconfig | 1 + configs/sama5d3_xplained_mmc_defconfig | 1 + configs/sama5d3_xplained_nandflash_defconfig | 1 + configs/sama5d3xek_mmc_defconfig | 1 + configs/sama5d3xek_nandflash_defconfig | 1 + configs/sama5d3xek_spiflash_defconfig | 1 + configs/sama5d4_xplained_mmc_defconfig | 1 + configs/sama5d4_xplained_nandflash_defconfig | 1 + configs/sama5d4_xplained_spiflash_defconfig | 1 + configs/sama5d4ek_mmc_defconfig | 1 + configs/sama5d4ek_nandflash_defconfig | 1 + configs/sama5d4ek_spiflash_defconfig | 1 + configs/sandbox_spl_defconfig | 1 - configs/sc_sps_1_defconfig | 1 + configs/seaboard_defconfig | 1 + configs/sh7752evb_defconfig | 1 + configs/silk_defconfig | 1 + configs/sksimx6_defconfig | 1 + configs/smartweb_defconfig | 1 + configs/smdk5250_defconfig | 1 + configs/smdk5420_defconfig | 1 + configs/smdkv310_defconfig | 1 + configs/snow_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 - configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/sopine_baseboard_defconfig | 1 + configs/spring_defconfig | 1 + configs/stout_defconfig | 1 + configs/sun8i_a23_evb_defconfig | 1 + configs/sunxi_Gemei_G9_defconfig | 1 + configs/tao3530_defconfig | 1 + configs/taurus_defconfig | 1 + configs/tbs_a711_defconfig | 1 + configs/tec-ng_defconfig | 1 + configs/tec_defconfig | 1 + configs/teres_i_defconfig | 1 + configs/theadorable_debug_defconfig | 1 + configs/thuban_defconfig | 1 + configs/ti816x_evm_defconfig | 1 + configs/tinker-rk3288_defconfig | 2 ++ configs/tricorder_defconfig | 1 + configs/trimslice_defconfig | 1 + configs/ts4600_defconfig | 1 + configs/turris_omnia_defconfig | 1 + configs/udoo_defconfig | 1 + configs/udoo_neo_defconfig | 1 - configs/venice2_defconfig | 1 + configs/ventana_defconfig | 1 + configs/vyasa-rk3288_defconfig | 2 ++ configs/wandboard_defconfig | 1 + configs/wb45n_defconfig | 1 + configs/wb50n_defconfig | 1 + configs/woodburn_sd_defconfig | 1 + configs/work_92105_defconfig | 1 + configs/x530_defconfig | 1 + configs/x600_defconfig | 1 + .../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + .../xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 + .../xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 + configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 + configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 + configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 + configs/xpress_spl_defconfig | 1 + configs/zc5202_defconfig | 1 + configs/zc5601_defconfig | 1 + configs/zynq_dlc20_rev1_0_defconfig | 1 + configs/zynq_microzed_defconfig | 1 + configs/zynq_minized_defconfig | 1 + configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + configs/zynq_zybo_z7_defconfig | 1 + drivers/input/input.c | 2 +- drivers/mtd/nand/raw/Makefile | 4 +-- drivers/reset/reset-socfpga.c | 2 +- env/Kconfig | 33 +++++++++++++++++-- env/Makefile | 11 +++---- env/common.c | 4 +-- include/configs/ls1021aiot.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/xilinx_zynqmp.h | 1 - include/env.h | 23 +++++++++++++ include/env_callback.h | 4 +++ include/env_default.h | 4 +++ include/env_flags.h | 4 +++ 586 files changed, 557 insertions(+), 207 deletions(-) -- 2.17.1

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[U-Boot] `uclass_find_device_by_name` fails to find the device
by Nandor Han 14 Mar '20

14 Mar '20

Hi everybody, I've noticed that commit 4213609cc7fb78f84b2ea63f4a5691b60d01c248 changes how `uclass.c:uclass_find_device_by_name` function compares the names for finding devices. Because of this I have an issue when having a DTS and trying to find a device by name. The `lists.c:lists_bind_fdt` function will bind a device to a device node tree and use the node name as device name. ``` lists.c: int lists_bind_fdt(..) ... name = ofnode_get_name(node); ... ``` Because of this devices will end up having names like: i2c@021a0000, pfuze100@8... When using `uclass.c:uclass_find_device_by_name` to get a device, before the change, this was not an issue since `strncmp` was used with the length of the name making a call like `uclass_find_device_by_name(pfuze100)` successfully even if the device name was `pfuze100@8`. ``` if (!strncmp(dev->name, name, strlen(name))) { ``` However after the change (which I think is correct), the check fails, resulting in not finding the expected device, since the device name has also the suffix `@...` included. What's the proper fix here: 1. Changing the `lists.c:lists_bind_fdt` to drop the `@` suffix? Note: Could this be a problem when having the same node names but different addressees in DTS {e.g.foo@1, foo@2} 2. When using `uclass.c:uclass_find_device_by_name` the user should take in consideration that `@..` suffix needs to be added. Note: This could be a problem when same code is used with different DTSs. 3. Changing the comparation in `uclass.c:uclass_find_device_by_name` to ignore the part after `@` for device names. 4. What else? Regads, Nandor

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