January 2019 - U-Boot

[U-Boot] [PATCH] MSCC: Jaguar2 enable debug uart
by Horatiu Vultur 01 Feb '19

01 Feb '19

Enable debug uart for Jaguar2 SoC family. Signed-off-by: Horatiu Vultur <horatiu.vultur(a)microchip.com> --- board/mscc/jr2/jr2.c | 7 +++++++ configs/mscc_jr2_defconfig | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index eac4dca..226181f 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -64,6 +64,13 @@ static void vcoreiii_gpio_set_alternate(int gpio, int mode) } } +void board_debug_uart_init(void) +{ + /* too early for the pinctrl driver, so configure the UART pins here */ + vcoreiii_gpio_set_alternate(10, 1); + vcoreiii_gpio_set_alternate(11, 1); +} + static void do_board_detect(void) { int i; diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 040e1e1..d80ca41 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -56,3 +56,9 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_LZMA=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x70100000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y -- 2.7.4

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[U-Boot] [PATCH 1/3] fsl_sec: fix register layout on Layerscape architectures
by laurentiu.tudor＠nxp.com 01 Feb '19

01 Feb '19

From: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> On Layerscape architectures the SEC memory map is 1MB and the register blocks contained in it are 64KB aligned, not 4KB as the ccsr_sec structure currently assumes. Fix the layout of the structure for these architectures. Signed-off-by: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> --- include/fsl_sec.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 16e3fcb5a1..be08a2b88b 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -121,10 +121,18 @@ typedef struct ccsr_sec { u32 chanum_ls; /* CHA Number Register, LS */ u32 secvid_ms; /* SEC Version ID Register, MS */ u32 secvid_ls; /* SEC Version ID Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res9[0x6f020]; +#else u8 res9[0x6020]; +#endif u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res10[0x8ffd8]; +#else u8 res10[0x8fd8]; +#endif } ccsr_sec_t; #define SEC_CTPR_MS_AXI_LIODN 0x08000000 -- 2.17.1

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[U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
by Marty E. Plummer 31 Jan '19

31 Jan '19

This adds support for the ASUS C201, a RK3288-based clamshell device. The device tree comes from linus's linux tree at 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters are for 4GB Samsung LPDDR3, decoded from coreboot's src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++ arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +- arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++ board/google/veyron/Kconfig | 16 ++ configs/chromebook_speedy_defconfig | 98 ++++++++++++ 7 files changed, 302 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts create mode 100644 configs/chromebook_speedy_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 44ebc50bfa..eab90216f0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ + rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi new file mode 100644 index 0000000000..22ba3490f2 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2015 Google, Inc + */ + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts new file mode 100644 index 0000000000..20100bbdee --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-speedy.dts @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Veyron Speedy Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "cros-ec-sbs.dtsi" +#include "rk3288-veyron-speedy-u-boot.dtsi" + +/ { + model = "Google Speedy"; + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", + "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", + "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", + "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", + "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + startup-delay-us = <100000>; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; +}; + +&backlight { + power-supply = <&backlight_regulator>; +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_alert1 { + temperature = <70000>; +}; + +&edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + +&panel { + power-supply= <&panel_regulator>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index abd62e520f..236cb932ba 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -71,7 +71,8 @@ u32 spl_boot_device(void) fallback: #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ + defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_MMC1; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index b5447e5b65..bce8023881 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of internal MMC. The product name is ASUS Chromebook Flip. +config TARGET_CHROMEBOOK_SPEEDY + bool "Google/Rockchip Veyron-Speedy Chromebook" + select BOARD_LATE_INIT + help + Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports, + micro HDMI, an 11.6 inch display, micro-SD card, + HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS + EC (Cortex-M3) to provide access to the keyboard and battery + functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC. + The product name is Asus Chromebook C201PA. + config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig index 770e9aad28..7f55d78dac 100644 --- a/board/google/veyron/Kconfig +++ b/board/google/veyron/Kconfig @@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y endif + +if TARGET_CHROMEBOOK_SPEEDY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig new file mode 100644 index 0000000000..77b25eafab --- /dev/null +++ b/configs/chromebook_speedy_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00100000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_TARGET_CHROMEBOOK_SPEEDY=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_SILENT_CONSOLE=y +CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_ROCKCHIP_RK3288=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK8XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x320a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y +# CONFIG_SPL_OF_LIBFDT is not set -- 2.18.0

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[U-Boot] [PATCH] rockchip: dts: rk3399-firely: add 'same-as-spl'
by Mark Kettenis 31 Jan '19

31 Jan '19

Like on rk3399-puma we want to continue booting the fill U-Boot from the same device as the SPL stage. Signed-off-by: Mark Kettenis <kettenis(a)openbsd.org> --- arch/arm/dts/rk3399-firefly.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index be350866a7..f90e7e88db 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -15,7 +15,7 @@ chosen { stdout-path = &uart2; - u-boot,spl-boot-order = &sdhci, &sdmmc; + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; backlight: backlight { -- 2.19.2

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[U-Boot] [PULL u-boot] Please pull u-boot-amlogic-20190131
by Neil Armstrong 31 Jan '19

31 Jan '19

[Oops, wrong subject, now fixed] Hi Tom, This PR adds support for HDMI & CVBS video output support for Amlogic GX SoCs. For simplicity, Anatolij acked to include the video patches along the platform changes in this PR. Video has been enabled only on libretech-cc, but will be enabled on the other boards after broader testing. Thanks, Neil The following changes since commit 535d74a8ae8d194269cefdf59ae17a92cd6e75dc: MAINTAINERS: Add Amlogic entry (2019-01-30 21:22:53 -0500) are available in the Git repository at: git://git.denx.de/u-boot-amlogic.git tags/u-boot-amlogic-20190131 for you to fetch changes up to fce1069bfb9b0b12fb760c408833c33243492257: arm: libretech-cc: enable video by default (2019-01-31 09:35:01 +0100) ---------------------------------------------------------------- - Add features and fixups to support video on Amlogic GX SoCs - Add video support for Amlogic GX SoC - Add DT fixups - Enable Video and USB Console for libretech-cc board ---------------------------------------------------------------- Jorge Ramirez-Ortiz (2): video: dw_hdmi: support SoC specific read/write ops video: dw_hdmi: add support for color conversion Maxime Jourdan (6): power: domain: meson-gx-pwrc-vpu: add missing depends arm64: dts: meson-gx: vpu should be probed before relocation arm64: dts: meson-gx: add hhi reg entry to hdmi_tx arm: meson: board-gx: Setup VPU in fdt arm: meson64: enable console mux and console env by default arm: libretech-cc: enable video by default Neil Armstrong (3): video: Add Meson Video Processing Unit Driver arm64: dts: meson-gx: Add hdmi_5v regulator as hdmi tx supply configs: meson64: use vidconsole and usbkbd if enabled arch/arm/dts/meson-gx-u-boot.dtsi | 21 + arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi | 7 + arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 7 + .../arm/dts/meson-gxl-s905x-khadas-vim-u-boot.dtsi | 7 + arch/arm/dts/meson-gxl-s905x-khadas-vim.dts | 1 + .../dts/meson-gxl-s905x-libretech-cc-u-boot.dtsi | 7 + arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 1 + arch/arm/dts/meson-gxl-s905x-p212-u-boot.dtsi | 7 + arch/arm/dts/meson-gxl-s905x-p212.dts | 1 + arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi | 7 + arch/arm/dts/meson-gxm-khadas-vim2.dts | 1 + arch/arm/include/asm/arch-meson/meson-vpu.h | 13 + arch/arm/mach-meson/board-gx.c | 5 + configs/khadas-vim2_defconfig | 2 + configs/khadas-vim_defconfig | 2 + configs/libretech-cc_defconfig | 8 + configs/odroid-c2_defconfig | 2 + configs/p212_defconfig | 2 + drivers/power/domain/Kconfig | 2 +- drivers/video/Kconfig | 2 + drivers/video/Makefile | 1 + drivers/video/dw_hdmi.c | 267 +++- drivers/video/meson/Kconfig | 12 + drivers/video/meson/Makefile | 9 + drivers/video/meson/meson_canvas.c | 45 + drivers/video/meson/meson_dw_hdmi.c | 445 ++++++ drivers/video/meson/meson_dw_hdmi.h | 134 ++ drivers/video/meson/meson_plane.c | 177 +++ drivers/video/meson/meson_registers.h | 1393 +++++++++++++++++++ drivers/video/meson/meson_vclk.c | 893 ++++++++++++ drivers/video/meson/meson_venc.c | 1464 ++++++++++++++++++++ drivers/video/meson/meson_vpu.c | 211 +++ drivers/video/meson/meson_vpu.h | 97 ++ drivers/video/meson/meson_vpu_init.c | 440 ++++++ drivers/video/meson/simplefb_common.c | 29 + drivers/video/meson/simplefb_common.h | 21 + include/configs/meson64.h | 23 + include/dw_hdmi.h | 74 + include/media_bus_format.h | 156 +++ 39 files changed, 5992 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/meson-gx-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x-khadas-vim-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x-p212-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi create mode 100644 arch/arm/include/asm/arch-meson/meson-vpu.h create mode 100644 drivers/video/meson/Kconfig create mode 100644 drivers/video/meson/Makefile create mode 100644 drivers/video/meson/meson_canvas.c create mode 100644 drivers/video/meson/meson_dw_hdmi.c create mode 100644 drivers/video/meson/meson_dw_hdmi.h create mode 100644 drivers/video/meson/meson_plane.c create mode 100644 drivers/video/meson/meson_registers.h create mode 100644 drivers/video/meson/meson_vclk.c create mode 100644 drivers/video/meson/meson_venc.c create mode 100644 drivers/video/meson/meson_vpu.c create mode 100644 drivers/video/meson/meson_vpu.h create mode 100644 drivers/video/meson/meson_vpu_init.c create mode 100644 drivers/video/meson/simplefb_common.c create mode 100644 drivers/video/meson/simplefb_common.h create mode 100644 include/media_bus_format.h

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[U-Boot] RISC-V Open source Supervisor Binary Interface (OpenSBI) Version 0.1 Released
by Atish Patra 31 Jan '19

31 Jan '19

OpenSBI version 0.1 is now publicly available in GitHub at https://github.com/riscv/opensbi. OpenSBI is an open source implementation of the RISC-V Supervisor Binary Interface (SBI). RISC-V SBI specifications are maintained as an independent project by the RISC-V Foundation in [Github]. This initial release of OpenSBI provides an implementation of the RISC-V SBI specifications version 0.1. These specifications define the legacy SBI interface currently in use by various products as well as by RISC-V QEMU virtual machines. OpenSBI also implements SBI compliant early boot firmwares capable of handling various boot flows and payloads on various environments. OpenSBI firmwares have been tested with payloads such as U-Boot and Linux kernel, showing that these open firmwares can fully replace the legacy non-standard BBL intermediate boot loader. The platforms supported with this first release are as follows. * Sifive HiFive Unleashed board * RISC-V QEMU *virt* and *sifive_u* virtual machines * Kendryte K210 SoC based boards. OpenSBI implementation can be easily extended by RISC-V platform vendors and System-on-Chip vendors to fit new hardware configurations. As SBI specifications evolve and extend beyond the current base legacy features, OpenSBI will be modified to provide a reference implementation for new SBI specifications. More information on OpenSBI capabilities as well as a contribution guideline are available in OpenSBI documentation included with the source code in GitHub. [Github]: https://github.com/riscv/riscv-sbi-doc

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[U-Boot] [PATCH] dfu: mmc: call fs functions instead of run_command
by Simon Goldschmidt 31 Jan '19

31 Jan '19

This unbreaks dfu mmc_file_op which is currently broken since using the load cmd on a buffer from heap is not allowed - added with commit aa3c609e2be5 ("fs: prevent overwriting reserved memory") Fixes: commit aa3c609e2be5 ("fs: prevent overwriting reserved memory") Reported-by: Stephen Warren <swarren(a)wwwdotorg.org> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Tested-by: Stephen Warren <swarren(a)nvidia.com> --- Changes since RFC: - decreased size of 'dev_part_str' to hold 'xxx:yyy' string - removed now unused define 'DFU_CMD_BUF_SIZE' --- drivers/dfu/dfu_mmc.c | 67 ++++++++++++++++++++----------------------- include/dfu.h | 1 - 2 files changed, 31 insertions(+), 37 deletions(-) diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index b45e6dc54c..403fd5351d 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -108,17 +108,17 @@ static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len) static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, void *buf, u64 *len) { - const char *fsname, *opname; - char cmd_buf[DFU_CMD_BUF_SIZE]; - char *str_env; + char dev_part_str[8]; int ret; + int fstype; + loff_t size = 0; switch (dfu->layout) { case DFU_FS_FAT: - fsname = "fat"; + fstype = FS_TYPE_FAT; break; case DFU_FS_EXT4: - fsname = "ext4"; + fstype = FS_TYPE_EXT; break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -126,48 +126,43 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, return -1; } + snprintf(dev_part_str, sizeof(dev_part_str), "%d:%d", + dfu->data.mmc.dev, dfu->data.mmc.part); + + ret = fs_set_blk_dev("mmc", dev_part_str, fstype); + if (ret) { + puts("dfu: fs_set_blk_dev error!\n"); + return ret; + } + switch (op) { case DFU_OP_READ: - opname = "load"; + ret = fs_read(dfu->name, (size_t)buf, 0, 0, &size); + if (ret) { + puts("dfu: fs_read error!\n"); + return ret; + } + *len = size; break; case DFU_OP_WRITE: - opname = "write"; + ret = fs_write(dfu->name, (size_t)buf, 0, *len, &size); + if (ret) { + puts("dfu: fs_write error!\n"); + return ret; + } break; case DFU_OP_SIZE: - opname = "size"; + ret = fs_size(dfu->name, &size); + if (ret) { + puts("dfu: fs_size error!\n"); + return ret; + } + *len = size; break; default: return -1; } - sprintf(cmd_buf, "%s%s mmc %d:%d", fsname, opname, - dfu->data.mmc.dev, dfu->data.mmc.part); - - if (op != DFU_OP_SIZE) - sprintf(cmd_buf + strlen(cmd_buf), " %p", buf); - - sprintf(cmd_buf + strlen(cmd_buf), " %s", dfu->name); - - if (op == DFU_OP_WRITE) - sprintf(cmd_buf + strlen(cmd_buf), " %llx", *len); - - debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); - - ret = run_command(cmd_buf, 0); - if (ret) { - puts("dfu: Read error!\n"); - return ret; - } - - if (op != DFU_OP_WRITE) { - str_env = env_get("filesize"); - if (str_env == NULL) { - puts("dfu: Wrong file size!\n"); - return -1; - } - *len = simple_strtoul(str_env, NULL, 16); - } - return ret; } diff --git a/include/dfu.h b/include/dfu.h index fbe978abdc..c671d8b04d 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -80,7 +80,6 @@ struct sf_internal_data { }; #define DFU_NAME_SIZE 32 -#define DFU_CMD_BUF_SIZE 128 #ifndef CONFIG_SYS_DFU_DATA_BUF_SIZE #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024*1024*8) /* 8 MiB */ #endif -- 2.17.1

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[U-Boot] Help: CONFIG_ENV_IS_IN_SPI_FLASH on AllWinner H5?
by g4＠novadsp.com 31 Jan '19

31 Jan '19

Greetings. Please let me know if there is a better place to ask this question. Any clues here? I've got an AllWinner H5 with Winbond SPI flash attached on SPI0. The flash is programmed using the sunxi FEL tools and boots perfectly. Now I'd like to save the environment there too. Loading Environment from SPI Flash... Invalid bus 0 (err=-19) *** Warning - spi_flash_probe_bus_cs() failed, using default environment TAIA Jerry. ------------------------------------------------------- CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=504 CONFIG_DRAM_ZQ=3881977 CONFIG_DRAM_ODT_EN=y CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_CMD_SF=y CONFIG_CMD_SF_TEST=y CONFIG_DEFAULT_DEVICE_TREE="anemos-sc5" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MTD=y CONFIG_MTD_DEVICE=y CONFIG_DM_SPI_FLASH=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SUN4I_SPI=y CONFIG_SOFT_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_USB_HOST_ETHER=y ... ------------------------------------------------ Device tree looks sane but I am no judge. ------------------------------------------------------- => fdt list /soc/spi@1c68000 spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x00001000>; interrupts = <0x00000000 0x00000041 0x00000004>; clocks = <0x00000003 0x0000001e 0x00000003 0x00000052>; clock-names = "ahb", "mod"; dmas = <0x00000014 0x00000017 0x00000014 0x00000017>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <0x00000015>; resets = <0x00000003 0x0000000f>; status = "okay"; #address-cells = <0x00000001>; #size-cells = <0x00000000>; spi_flash@0 { }; ------------------------------------------------------- => fdt list /soc/spi@1c68000/spi_flash@0 spi_flash@0 { compatible = "spi-flash"; reg = <0x00000000>; spi-max-frequency = <0x02faf080>; u-boot,dm-pre-reloc; };

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[U-Boot] [PATCH v3 00/22] mx6sabre: Add DM and SPL FIT support
by Abel Vesa 31 Jan '19

31 Jan '19

The second version is here: https://lists.denx.de/pipermail/u-boot/2019-January/356557.html Changes since v2: * Removed the unecessary SYS_MALLOC_F_LEN from both defocnfig * Fixed the copyright for all the *u-boot.dtsi files Abel Vesa (22): usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGE usb: ehci-mx6: Make regulator DM_REGULATOR dependent configs: imx6sabreauto: Add DM_MMC support configs: imx6sabreauto: Add DM_USB support mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds board: mx6sabresd: Add board_fit_config_name_match to support FIT in SPL board: mx6sabreauto: Add board_fit_config_name_match to support FIT in SPL arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] files arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] arm: imx: Add FIT SPL its configs: mx6sabreauto: Add SPL FIT and DM support configs: mx6sabresd: Add SPL FIT and DM support mx6sabreauto: Add DM_GPIO support mx6sabresd: Add DM_GPIO support configs: mx6sabreauto: Add DM_SPI_FLASH necessary configs configs: mx6sabresd: Add DM_SPI_FLASH necessary configs board: mx6sabreauto: Remove the non-DM code board: mx6sabresd: Remove non-DM code board: mx6sabresd: Remove the enet reset gpio handling configs: mx6sabresd: Reduce size for SPL by disabling SPL_DOS and SPL_EFI board: mx6sabreauto: Update README with the SPL DM FIT info board: mx6sabresd: Update README with the SPL DM FIT info arch/arm/dts/Makefile | 8 +- arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi | 6 + arch/arm/dts/imx6dl-sabreauto.dts | 13 + arch/arm/dts/imx6dl-sabresd-u-boot.dtsi | 6 + arch/arm/dts/imx6dl-sabresd.dts | 18 + arch/arm/dts/imx6dl.dtsi | 306 ++++++++++- arch/arm/dts/imx6q-sabreauto-u-boot.dtsi | 6 + arch/arm/dts/imx6q-sabreauto.dts | 18 + arch/arm/dts/imx6q-sabresd-u-boot.dtsi | 6 + arch/arm/dts/imx6q-sabresd.dts | 23 + arch/arm/dts/imx6q.dtsi | 310 +++++++++-- arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi | 21 + arch/arm/dts/imx6qdl-sabreauto.dtsi | 810 ++++++++++++++++++++++++++++ arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi | 14 + arch/arm/dts/imx6qdl-sabresd.dtsi | 741 +++++++++++++++++++++++++ arch/arm/dts/imx6qdl-u-boot.dtsi | 4 +- arch/arm/dts/imx6qdl.dtsi | 455 +++++++++------- arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi | 6 + arch/arm/dts/imx6qp-sabreauto.dts | 55 ++ arch/arm/dts/imx6qp-sabresd-u-boot.dtsi | 6 + arch/arm/dts/imx6qp-sabresd.dts | 55 ++ arch/arm/dts/imx6qp.dtsi | 115 ++++ arch/arm/include/asm/arch-am33xx/spl.h | 2 +- arch/arm/mach-imx/mx6/fit_spl.its | 41 ++ arch/arm/mach-omap2/boot-common.c | 2 +- board/freescale/mx6sabreauto/README | 6 +- board/freescale/mx6sabreauto/mx6sabreauto.c | 91 +--- board/freescale/mx6sabresd/README | 9 +- board/freescale/mx6sabresd/mx6sabresd.c | 78 +-- common/Makefile | 5 +- common/spl/Kconfig | 4 +- common/spl/Makefile | 2 +- common/spl/spl_usb.c | 4 - configs/am43xx_evm_usbhost_boot_defconfig | 2 +- configs/am43xx_hs_evm_defconfig | 2 +- configs/mx6sabreauto_defconfig | 21 +- configs/mx6sabresd_defconfig | 26 +- drivers/mmc/fsl_esdhc.c | 8 +- drivers/usb/host/ehci-mx6.c | 7 +- 39 files changed, 2900 insertions(+), 412 deletions(-) create mode 100644 arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-sabreauto.dts create mode 100644 arch/arm/dts/imx6dl-sabresd-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-sabresd.dts create mode 100644 arch/arm/dts/imx6q-sabreauto-u-boot.dtsi create mode 100644 arch/arm/dts/imx6q-sabreauto.dts create mode 100644 arch/arm/dts/imx6q-sabresd-u-boot.dtsi create mode 100644 arch/arm/dts/imx6q-sabresd.dts create mode 100644 arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-sabreauto.dtsi create mode 100644 arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi create mode 100644 arch/arm/dts/imx6qp-sabreauto-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qp-sabreauto.dts create mode 100644 arch/arm/dts/imx6qp-sabresd-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qp-sabresd.dts create mode 100644 arch/arm/dts/imx6qp.dtsi create mode 100644 arch/arm/mach-imx/mx6/fit_spl.its -- 2.7.4

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[U-Boot] [PATCH 0/9] sunxi: enable DM_MMC
by Andre Przywara 31 Jan '19

31 Jan '19

This series enables the Allwinner MMC driver to drive all SoCs with its DM_MMC variant. We use the gates clock and reset support from the new clock driver, but keep the actual mod clock in its somewhat hackish state. Properly supporting this via the clock driver is a bit more work. The per-compatible variant struct for now only holds the mod clock address (which will go away), but we will need the struct later again for the various timing modes. This allows us to eventually enable DM_MMC for all SoCs, and get rid of the nasty deprecation warning. The first patch adds the MMC clock gates and resets to the clock driver. Patch 2/9 adds support for the A80 MMC config clock, which is a bit special. I can't test this, so please give this a try if you have a board. Patch 3 uses the new clocks in the MMC driver, the following three patches add the remaining compatible strings along with their required mod clock addresses. Patch 7 fixes the Pine64-LTS board, while patch 8 eventually enables everything. Patch 9 is some comment fix to make it easier to reason about what part of the driver is for DM_MMC and which is not. I successfully compiled the HEAD for all 142 Allwinner boards, also compiled all patches for selected boards. This was briefly tested on Pine-H64 (H6), Pine64-LTS (A64), OrangePi PC 2 (H5), OrangePi Zero (H2+) and BananaPi-M1 (A20). Please run it on every board that you can get hold of to give this series a good shake. This goes on top of current sunxi/master (543049ab5906) and is available on https://github.com/apritzel/u-boot/commits/sunxi-dm. This replaces Jagan's v2 series "mmc: sunxi: Enable DM_MMC" in a more driver model compliant way, borrowing two patches from him. Cheers, Andre. Andre Przywara (7): sunxi: clk: add MMC gates/resets sunxi: clk: A80: add MMC clock support mmc: sunxi: Add DM clk and reset support mmc: sunxi: Add H6 support mmc: sunxi: Add A80 support mmc: sunxi: Honour non-removable property in DT mmc: sunxi: Mark end of DM_MMC #ifdefs Jagan Teki (2): mmc: sunxi: Add missing compatible strings arm: sunxi: Enable DM_MMC arch/arm/Kconfig | 1 + arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - drivers/clk/sunxi/clk_a10.c | 4 +++ drivers/clk/sunxi/clk_a10s.c | 3 ++ drivers/clk/sunxi/clk_a23.c | 6 ++++ drivers/clk/sunxi/clk_a31.c | 8 +++++ drivers/clk/sunxi/clk_a64.c | 6 ++++ drivers/clk/sunxi/clk_a80.c | 28 ++++++++++++++++- drivers/clk/sunxi/clk_a83t.c | 6 ++++ drivers/clk/sunxi/clk_h3.c | 6 ++++ drivers/clk/sunxi/clk_h6.c | 6 ++++ drivers/clk/sunxi/clk_r40.c | 8 +++++ drivers/mmc/sunxi_mmc.c | 59 +++++++++++++++++++++++++++++------ 14 files changed, 131 insertions(+), 12 deletions(-) -- 2.14.5

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