January 2019 - U-Boot

[U-Boot] [PATCH 0/3] Add Ethernet support for Poplar board
by Shawn Guo 13 Feb '19

13 Feb '19

The series adds Ethernet support for Poplar board. It firstly creates a reset driver for HiSilicon platform, then introduces higmacv300 Ethernet driver, and finally enables Ethernet support for Poplar board. Shawn Guo (3): reset: add reset driver for HiSilicon platform net: add higmacv300 Ethernet driver for HiSilicon platform poplar: enable Ethernet driver support arch/arm/dts/hi3798cv200-u-boot.dtsi | 6 + configs/poplar_defconfig | 3 + drivers/net/Kconfig | 9 + drivers/net/Makefile | 1 + drivers/net/higmacv300.c | 592 +++++++++++++++++++++++++++ drivers/reset/Kconfig | 6 + drivers/reset/Makefile | 1 + drivers/reset/reset-hisilicon.c | 95 +++++ 8 files changed, 713 insertions(+) create mode 100644 drivers/net/higmacv300.c create mode 100644 drivers/reset/reset-hisilicon.c -- 2.18.0

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[U-Boot] [PATCH 1/1] test/py: use default load address for tftp
by Heinrich Schuchardt 13 Feb '19

13 Feb '19

On x86_64 the size of the file u-boot loaded by the tftp test has grown in size such that when loading the file to 0x200000 it overwrites a memory area reserved for PCI. If no load address is specified for tftp do not use the ram base address (or if zero 0x200000) but the default address. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- Currently there is a bug in net/tftp.c introduced by commit a156c47e39ad ("tftp: prevent overwriting reserved memory") which does not allow loading to the second DRAM bank. Simon Goldschmidt is working to fix it. Due to this bug with the proposed patch we see a Travis CI error for vexpress_ca15_tc2_defconfig and vexpress_ca9x4_defconfig. --- test/py/tests/test_net.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py index 9c395e69fa..9ca6743afd 100644 --- a/test/py/tests/test_net.py +++ b/test/py/tests/test_net.py @@ -145,11 +145,12 @@ def test_net_tftpboot(u_boot_console): pytest.skip('No TFTP readable file to read') addr = f.get('addr', None) - if not addr: - addr = u_boot_utils.find_ram_base(u_boot_console) fn = f['fn'] - output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn)) + if not addr: + output = u_boot_console.run_command('tftpboot %s' % (fn)) + else: + output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn)) expected_text = 'Bytes transferred = ' sz = f.get('size', None) if sz: @@ -163,7 +164,7 @@ def test_net_tftpboot(u_boot_console): if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y': return - output = u_boot_console.run_command('crc32 %x $filesize' % addr) + output = u_boot_console.run_command('crc32 $fileaddr $filesize') assert expected_crc in output @pytest.mark.buildconfigspec('cmd_nfs') -- 2.20.1

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[U-Boot] [RFC] ARM: omap3_logic_somlv: Enable OF_CONTROL in SPL
by Adam Ford 12 Feb '19

12 Feb '19

By removing EXT support from SPL, it makes room for the extra overhead of enabling OF_CONTROL in SPL. With SPL_OF_CONTROL enabled, extra options need to be added to the device tree to tell it which portions of the tree are needed early in boot time Unfortunately, with these options as-is, the system doesn't boot nor does it display anything on the UART. I don't have a debugger readily available, but I have seen others with AM33x boards which are similar to OMAP3 boards. This is posted as an RFC just in case anyone has any suggestions on what might be missing. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi index 6445048fe0..e53c7065cb 100644 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi @@ -8,6 +8,18 @@ chosen { stdout-path = &uart1; }; + + ocp { + u-boot,dm-pre-reloc; + }; +}; + +&l4_core { + u-boot,dm-pre-reloc; +}; + +&scm { + u-boot,dm-pre-reloc; }; &i2c1 { @@ -19,9 +31,14 @@ }; &mmc1 { + u-boot,dm-pre-reloc; cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */ }; +&mmc1_pins { + u-boot,dm-pre-reloc; +}; + &mmc2 { status = "disabled"; }; @@ -30,3 +47,23 @@ status = "disabled"; }; +&omap3_pmx_wkup { + u-boot,dm-pre-reloc; +}; + +&omap3_pmx_core { + u-boot,dm-pre-reloc; +}; + +&omap3_pmx_core2 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +&uart1_pins { + u-boot,dm-pre-reloc; +}; + diff --git a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi index 4990ed90dc..fcb35834e2 100644 --- a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi +++ b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi @@ -222,6 +222,13 @@ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ >; }; + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + >; + }; + }; &omap3_pmx_wkup { @@ -240,6 +247,8 @@ &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; }; diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 144e6f68a4..ee77ce077c 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -56,36 +56,6 @@ DECLARE_GLOBAL_DATA_PTR; #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50 -/* This is only needed until SPL gets OF support */ -#ifdef CONFIG_SPL_BUILD -static const struct ns16550_platdata omap3logic_serial = { - .base = OMAP34XX_UART1, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(omap3logic_uart) = { - "omap_serial", - &omap3logic_serial -}; - -static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = { - .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, - .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, - .cfg.f_min = 400000, - .cfg.f_max = 52000000, - .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, - .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, -}; - -U_BOOT_DEVICE(omap3_logic_mmc0) = { - .name = "omap_hsmmc", - .platdata = &omap3_logic_mmc0_platdata, -}; - -#endif - #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 6602af6abe..31a3909098 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -14,6 +14,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_EXT_SUPPORT is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="OMAP Logic # " @@ -29,6 +30,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit" # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y @@ -52,6 +54,7 @@ CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x08000000 CONFIG_SMC911X_32_BIT=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set -- 2.17.1

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[U-Boot] [PATCH 1/2] xilinx: Move zynq_board_read_rom_ethaddr to shared location
by Michal Simek 12 Feb '19

12 Feb '19

Zynq and ZynqMP are sharing similar code and there is no reason to do code duplication. Move zynq_board_read_rom_ethaddr() to common file for easier conversion to DM. Use ZynqMP version that's why also add CONFIG_ZYNQ_EEPROM_BUS to Syzygy which is only one Zynq board which is using this feature. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/opalkelly/zynq/board.c | 2 ++ board/xilinx/common/board.c | 25 +++++++++++++++++++++++++ board/xilinx/zynq/Makefile | 1 + board/xilinx/zynq/board.c | 13 ------------- board/xilinx/zynqmp/Makefile | 1 + board/xilinx/zynqmp/zynqmp.c | 17 ----------------- include/configs/syzygy_hub.h | 1 + 7 files changed, 30 insertions(+), 30 deletions(-) create mode 100644 board/xilinx/common/board.c diff --git a/board/opalkelly/zynq/board.c b/board/opalkelly/zynq/board.c index a95c9d1eff0f..ee666185ec09 100644 --- a/board/opalkelly/zynq/board.c +++ b/board/opalkelly/zynq/board.c @@ -1 +1,3 @@ +#include "../../xilinx/common/board.c" + #include "../../xilinx/zynq/board.c" diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c new file mode 100644 index 000000000000..7e813d856404 --- /dev/null +++ b/board/xilinx/common/board.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2019 Xilinx, Inc. + * Michal Simek <michal.simek(a)xilinx.com> + */ + +#include <common.h> +#include <dm/uclass.h> +#include <i2c.h> + +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ +#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ + defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ + defined(CONFIG_ZYNQ_EEPROM_BUS) + i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); + + if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, + ethaddr, 6)) + printf("I2C EEPROM MAC address read failed\n"); +#endif + + return 0; +} diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index e7645be189c3..8d3301543959 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -4,6 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. obj-y := board.o +obj-y += ../common/board.o ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"") PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE)) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 614d93c082a6..f9973840bf20 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -77,19 +77,6 @@ int board_late_init(void) return 0; } -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) -{ -#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ - defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) - if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, - CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, - ethaddr, 6)) - printf("I2C EEPROM MAC address read failed\n"); -#endif - - return 0; -} - #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) int dram_init_banksize(void) { diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 960b81fc5853..80f8ca7e1e4b 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -4,6 +4,7 @@ # Michal Simek <michal.simek(a)xilinx.com> obj-y := zynqmp.o +obj-y += ../common/board.o ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"") PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE)) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 41e88b03f9d1..e7dfd49a3ccf 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -20,7 +20,6 @@ #include <usb.h> #include <dwc3-uboot.h> #include <zynqmppl.h> -#include <i2c.h> #include <g_dnl.h> DECLARE_GLOBAL_DATA_PTR; @@ -409,22 +408,6 @@ int board_early_init_r(void) return 0; } -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) -{ -#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ - defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ - defined(CONFIG_ZYNQ_EEPROM_BUS) - i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); - - if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, - CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, - ethaddr, 6)) - printf("I2C EEPROM MAC address read failed\n"); -#endif - - return 0; -} - unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, char * const argv[]) { diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h index 88ee77284890..75036977d486 100644 --- a/include/configs/syzygy_hub.h +++ b/include/configs/syzygy_hub.h @@ -12,6 +12,7 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x57 +#define CONFIG_ZYNQ_EEPROM_BUS 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "fit_image=fit.itb\0" \ -- 1.9.1

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[U-Boot] [PATCH 1/3] x86: Change 4-level page table base address to low memory
by Bin Meng 12 Feb '19

12 Feb '19

At present the 4-level page table base address for 64-bit U-Boot proper is assigned an address that conflicts with CONFIG_LOADADDR. Change it to an address within the low memory range instead. Fixes crashes seen when 'dhcp' on QEMU x86_64 with "-net nic -net user,tftp=.,bootfile=u-boot". Reported-by: Alexander Graf <agraf(a)suse.de> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/i386/cpu.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 208ef08..af42431 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -462,6 +462,7 @@ int cpu_has_64bit(void) has_long_mode(); } +#define PAGETABLE_BASE 0x80000 #define PAGETABLE_SIZE (6 * 4096) /** @@ -523,10 +524,7 @@ int cpu_jump_to_64bit_uboot(ulong target) uint32_t *pgtable; func_t func; - /* TODO(sjg(a)chromium.org): Find a better place for this */ - pgtable = (uint32_t *)0x1000000; - if (!pgtable) - return -ENOMEM; + pgtable = (uint32_t *)PAGETABLE_BASE; build_pagetable(pgtable); -- 2.7.4

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[U-Boot] [PATCH v2 0/7] Align U-Boot I2C DM bus ID handling with Linux
by Michal Simek 11 Feb '19

11 Feb '19

U-Boot with I2C_DM enabled is not capable to list i2c busses connected to i2c mux. For getting this work there is a need to find out highest alias ID and use this uniq number for new buses connected to I2C mux. This series is making this happen. There is only one missing piece which is that also i2c controllers which are not listed in DT are not using this feature. Removing setting up aliases from i2c mux code and unifying it in the same code ensures that numbering schema is proper if no alias is specified. ZynqMP> i2c bus Bus 0: i2c@ff020000 20: gpio@20, offset len 1, flags 0 21: gpio@21, offset len 1, flags 0 75: i2c-mux@75, offset len 1, flags 0 Bus 1: i2c@ff020000->i2c-mux@75->i2c@0 Bus 2: i2c@ff020000->i2c-mux@75->i2c@1 Bus 3: i2c@ff020000->i2c-mux@75->i2c@2 Bus 4: i2c@ff030000 (active 4) 74: i2c-mux@74, offset len 1, flags 0 75: i2c-mux@75, offset len 1, flags 0 Bus 5: i2c@ff030000->i2c-mux@74->i2c@0 (active 5) 54: eeprom@54, offset len 1, flags 0 Bus 6: i2c@ff030000->i2c-mux@74->i2c@1 Bus 7: i2c@ff030000->i2c-mux@74->i2c@2 Bus 8: i2c@ff030000->i2c-mux@74->i2c@3 Bus 9: i2c@ff030000->i2c-mux@74->i2c@4 Bus 10: i2c@ff030000->i2c-mux@75->i2c@0 Bus 11: i2c@ff030000->i2c-mux@75->i2c@1 Bus 12: i2c@ff030000->i2c-mux@75->i2c@2 Bus 13: i2c@ff030000->i2c-mux@75->i2c@3 Bus 14: i2c@ff030000->i2c-mux@75->i2c@4 Bus 15: i2c@ff030000->i2c-mux@75->i2c@5 Bus 16: i2c@ff030000->i2c-mux@75->i2c@6 Bus 17: i2c@ff030000->i2c-mux@75->i2c@7 Thanks, Michal Changes in v2: - Update kernel-doc binding - Return -1 in case of error. -1 means that the next free alias is 0. - New patch - New patch - Use dev_read_alias_highest_id() - Use uclass private data - Use private uclass data - Fix headers - Change patch description to focus only on bus name Michal Simek (7): dm: core: Add of_alias_get_highest_id() fdt: Introduce fdtdec_get_alias_highest_id() dm: core: Introduce dev_read_alias_highest_id() dm: core: Add tests for dev_read_alias_highest_id() i2c: dm: Record maximum id of devices before probing devices i2c: Fill req_seq in i2c_post_bind() i2c: mux: Generate longer i2c mux name drivers/core/of_access.c | 18 ++++++++++++++ drivers/core/read.c | 8 ++++++ drivers/i2c/i2c-uclass.c | 50 +++++++++++++++++++++++++++++++++++--- drivers/i2c/muxes/i2c-mux-uclass.c | 29 +++++++++++++++++++--- include/dm/of_access.h | 10 ++++++++ include/dm/read.h | 16 ++++++++++++ include/fdtdec.h | 13 ++++++++++ lib/fdtdec.c | 33 +++++++++++++++++++++++++ test/dm/test-fdt.c | 23 ++++++++++++++++++ 9 files changed, 194 insertions(+), 6 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] sun50i: h5: Orange Pi Zero Plus: Fix SdCard detection
by Hauke Mehrtens 11 Feb '19

11 Feb '19

The Detection pin is at PF6 and not at PH13 like defined before. I checked the schematics and now I am am not seeing this error message any more: Loading Environment from FAT... Card did not respond to voltage select! CONFIG_MMC_SUNXI_SLOT_EXTRA is also not needed because the second MCC slot is for the Wifi card. Fixes: 76d69eb01de ("sun50i: h5: Add initial Orange Pi Zero Plus support") Signed-off-by: Hauke Mehrtens <hauke(a)hauke-m.de> --- configs/orangepi_zero_plus_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index 5d783c5981..2b9691a1aa 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -4,8 +4,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 -CONFIG_MMC0_CD_PIN="PH13" -CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_MMC0_CD_PIN="PF6" CONFIG_NR_DRAM_BANKS=1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set -- 2.20.1

2 1

[U-Boot] [PATCH 1/4 v3] pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr
by Stefan Roese 11 Feb '19

11 Feb '19

This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> --- v3: - New patch, replaces "[PATCH] core: ofnode: Add ofnode_pci_get_devfn()" drivers/pci/pci-uclass.c | 28 +++++++++++++++++++--------- include/pci.h | 10 ++++++++++ 2 files changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 2cf55cb743..47f3cc9107 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1007,10 +1007,25 @@ static int pci_uclass_post_probe(struct udevice *bus) return 0; } +int pci_get_devfn(struct udevice *dev) +{ + struct fdt_pci_addr addr; + int ret; + + /* Extract the devfn from fdt_pci_addr */ + ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, + "reg", &addr); + if (ret) { + if (ret != -ENOENT) + return -EINVAL; + } + + return addr.phys_hi & 0xff00; +} + static int pci_uclass_child_post_bind(struct udevice *dev) { struct pci_child_platdata *pplat; - struct fdt_pci_addr addr; int ret; if (!dev_of_valid(dev)) @@ -1022,14 +1037,9 @@ static int pci_uclass_child_post_bind(struct udevice *dev) ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device); /* Extract the devfn from fdt_pci_addr */ - ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg", - &addr); - if (ret) { - if (ret != -ENOENT) - return -EINVAL; - } else { - pplat->devfn = addr.phys_hi & 0xff00; - } + pplat->devfn = pci_get_devfn(dev); + if (ret < 0) + return ret; return 0; } diff --git a/include/pci.h b/include/pci.h index 785d7d28b7..041f8e3747 100644 --- a/include/pci.h +++ b/include/pci.h @@ -1560,6 +1560,16 @@ struct dm_pci_emul_ops { int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, struct udevice **containerp, struct udevice **emulp); +/** + * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device + * + * Get devfn from fdt_pci_addr of the specifified device + * + * @dev: PCI device + * @return devfn in bits 15...8 if found, -ENODEV if not found + */ +int pci_get_devfn(struct udevice *dev); + #endif /* CONFIG_DM_PCI */ /** -- 2.20.1

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[U-Boot] [PATCH v2 1/2] Kconfig: Migrate CONFIG_BUILD_TARGET
by Jagan Teki 11 Feb '19

11 Feb '19

Migrate CONFIG_BUILD_TARGET into Kconfig. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v2: - build target type 'u-boot.itb' when SPL_LOAD_FIT being used Kconfig | 13 +++++++++++++ README | 7 ------- arch/arm/mach-mvebu/include/mach/config.h | 5 ----- configs/SBx81LIFKW_defconfig | 1 + configs/SBx81LIFXCAT_defconfig | 1 + configs/dreamplug_defconfig | 1 + configs/ds109_defconfig | 1 + configs/guruplug_defconfig | 1 + configs/ib62x0_defconfig | 1 + configs/nsa310s_defconfig | 1 + configs/sheevaplug_defconfig | 1 + include/configs/SBx81LIFKW.h | 1 - include/configs/SBx81LIFXCAT.h | 1 - include/configs/ib62x0.h | 3 --- include/configs/mv-plug-common.h | 3 --- include/configs/nsa310s.h | 3 --- include/configs/rcar-gen3-common.h | 1 - include/configs/socfpga_common.h | 3 --- include/configs/sunxi-common.h | 1 - scripts/config_whitelist.txt | 1 - 20 files changed, 21 insertions(+), 29 deletions(-) diff --git a/Kconfig b/Kconfig index aff7b2e00a..15b79259a8 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,19 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details. +config BUILD_TARGET + string "Build target special images" + default "u-boot-with-spl.sfp" if ARCH_SOCFPGA + default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD + default "u-boot-elf.srec" if RCAR_GEN3 + default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI + help + Some SoCs need special image types (e.g. U-Boot binary + with a special header) as build targets. By defining + CONFIG_BUILD_TARGET in the SoC / board header, this + special image will be automatically built upon calling + make / buildman. + endmenu # General setup menu "Boot images" diff --git a/README b/README index 17d56b8034..01ad69e926 100644 --- a/README +++ b/README @@ -1998,13 +1998,6 @@ The following options need to be configured: 200 ms. - Configuration Management: - CONFIG_BUILD_TARGET - - Some SoCs need special image types (e.g. U-Boot binary - with a special header) as build targets. By defining - CONFIG_BUILD_TARGET in the SoC / board header, this - special image will be automatically built upon calling - make / buildman. CONFIG_IDENT_STRING diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index f165d10018..e3235fc67e 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -40,11 +40,6 @@ #define CONFIG_SYS_KWD_CONFIG arch/arm/mach-mvebu/kwbimage.cfg #endif /* CONFIG_SYS_KWD_CONFIG */ -/* Add target to build it automatically upon "make" */ -#ifdef CONFIG_SPL -#define CONFIG_BUILD_TARGET "u-boot-spl.kwb" -#endif - /* end of 16M scrubbed by training in bootrom */ #define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index e0ce1595c5..52bb70ae8c 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_SBx81LIFKW=y CONFIG_IDENT_STRING="\nSBx81LIFKW" # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_BUILD_TARGET="u-boot.kwb" CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y CONFIG_MISC_INIT_R=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 4a6e05844f..b322ab0959 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_SBx81LIFXCAT=y CONFIG_IDENT_STRING="\nSBx81LIFXCAT" # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_BUILD_TARGET="u-boot.kwb" CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y CONFIG_MISC_INIT_R=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index d3263cf9cd..762521f97d 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -6,6 +6,7 @@ CONFIG_IDENT_STRING="\nMarvell-DreamPlug" CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_BUILD_TARGET="u-boot.kwb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 352403e573..b72174eada 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_DS109=y CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_F is not set CONFIG_HUSH_PARSER=y +CONFIG_BUILD_TARGET="u-boot.kwb" # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 9998e48ab9..7726f9a769 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -6,6 +6,7 @@ CONFIG_IDENT_STRING="\nMarvell-GuruPlug" CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_BUILD_TARGET="u-boot.kwb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 985d85e027..03987a4ff1 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_IB62X0=y CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" CONFIG_NR_DRAM_BANKS=2 CONFIG_BOOTDELAY=3 +CONFIG_BUILD_TARGET="u-boot.kwb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ib62x0 => " diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index eb29a70157..971d33b33d 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NSA310S=y CONFIG_NR_DRAM_BANKS=2 CONFIG_BOOTDELAY=3 +CONFIG_BUILD_TARGET="u-boot.kwb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nsa310s => " diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 04b00cdea9..33cced9c48 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -7,6 +7,7 @@ CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_BUILD_TARGET="u-boot.kwb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 07b65f89f9..d62fd35e81 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -13,7 +13,6 @@ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#define CONFIG_BUILD_TARGET "u-boot.kwb" /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index d73752c7f9..3c8c216d89 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -13,7 +13,6 @@ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#define CONFIG_BUILD_TARGET "u-boot.kwb" /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index f8d3c3b63f..5e54441c73 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -15,9 +15,6 @@ #define CONFIG_KW88F6281 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -/* Add target to build it automatically upon "make" */ -#define CONFIG_BUILD_TARGET "u-boot.kwb" - /* * Compression configuration */ diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h index f424e2cc6c..486650f183 100644 --- a/include/configs/mv-plug-common.h +++ b/include/configs/mv-plug-common.h @@ -13,9 +13,6 @@ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -/* Add target to build it automatically upon "make" */ -#define CONFIG_BUILD_TARGET "u-boot.kwb" - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 1ca9a01754..eb465e0690 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -15,9 +15,6 @@ #define CONFIG_KW88F6702 1 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -/* add target to build it automatically upon "make" */ -#define CONFIG_BUILD_TARGET "u-boot.kwb" - /* compression configuration */ #define CONFIG_BZIP2 diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 6c2fa6a63c..06d5d3219c 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -12,7 +12,6 @@ #include <asm/arch/rmobile.h> #define CONFIG_REMAKE_ELF -#define CONFIG_BUILD_TARGET "u-boot-elf.srec" /* boot option */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index bd8f5c8c41..d3dd2eabac 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -14,9 +14,6 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -/* add target to build it automatically upon "make" */ -#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" - /* * Memory configurations */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 9819d9980c..f0c8daad72 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -32,7 +32,6 @@ #endif #ifdef CONFIG_ARM64 -#define CONFIG_BUILD_TARGET "u-boot.itb" #define CONFIG_SYS_BOOTM_LEN (32 << 20) #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 527050de97..17c4b482c7 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -181,7 +181,6 @@ CONFIG_BS_SIZE CONFIG_BTB CONFIG_BUFNO_AUTO_INCR_BIT CONFIG_BUILD_ENVCRC -CONFIG_BUILD_TARGET CONFIG_BUS_WIDTH CONFIG_BZIP2 CONFIG_CADDY2 -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH] mtd: qspi: support read the flag status in fspi driver
by Ye Li 11 Feb '19

11 Feb '19

From: Han Xu <han.xu(a)nxp.com> Support to read the flag status in driver to avoid the spi-nor framework wait_for_ready hang issue. Signed-off-by: Han Xu <han.xu(a)nxp.com> --- drivers/spi/fsl_qspi.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 1987a72..ed0e649 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -47,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif #define SEQID_WRAR 13 #define SEQID_RDAR 14 +#define SEQID_RDFSR 15 /* QSPI CMD */ #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ @@ -57,6 +58,7 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ +#define QSPI_CMD_FLAG_SR 0x70 /* Read FLAG STATUS*/ /* Used for Micron, winbond and Macronix flashes */ #define QSPI_CMD_WREAR 0xc5 /* EAR register write */ @@ -230,6 +232,15 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); + /* Read Flag Status */ + lut_base = SEQID_RDFSR * 4; + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_FLAG_SR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); + /* Erase a sector */ lut_base = SEQID_SE * 4; #ifdef CONFIG_SPI_FLASH_BAR @@ -740,6 +751,40 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) qspi_write32(priv->flags, &regs->mcr, mcr_reg); } +static void qspi_op_rdfsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) +{ + struct fsl_qspi_regs *regs = priv->regs; + u32 mcr_reg, reg, data; + + mcr_reg = qspi_read32(priv->flags, &regs->mcr); + qspi_write32(priv->flags, &regs->mcr, + QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + mcr_reg); + qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + + qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base); + + qspi_write32(priv->flags, &regs->ipcr, + (SEQID_RDFSR << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) + ; + + while (1) { + reg = qspi_read32(priv->flags, &regs->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + data = qspi_read32(priv->flags, &regs->rbdr[0]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, len); + qspi_write32(priv->flags, &regs->mcr, + qspi_read32(priv->flags, &regs->mcr) | + QSPI_MCR_CLR_RXF_MASK); + break; + } + } + + qspi_write32(priv->flags, &regs->mcr, mcr_reg); +} + static void qspi_op_erase(struct fsl_qspi_priv *priv) { struct fsl_qspi_regs *regs = priv->regs; @@ -825,6 +870,8 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, qspi_op_rdid(priv, din, bytes); else if (priv->cur_seqid == QSPI_CMD_RDSR) qspi_op_rdsr(priv, din, bytes); + else if (priv->cur_seqid == QSPI_CMD_FLAG_SR) + qspi_op_rdfsr(priv, din, bytes); #ifdef CONFIG_SPI_FLASH_BAR else if ((priv->cur_seqid == QSPI_CMD_BRRD) || (priv->cur_seqid == QSPI_CMD_RDEAR)) { -- 2.7.4

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