January 2019 - U-Boot

[U-Boot] [PATCH 1/3] videomodes: Allow EDID timings where hsync/vsync pulse is 0
by Priit Laes 15 Feb '19

15 Feb '19

From: Priit Laes <priit.laes(a)paf.com> Current EDID detailed timing parser errors out when either horizontal or vertical pulse sync width is 0, thus not allowing a display with EDID listed below work properly. Of-course, this is somewhat quirky HDMI display with following anti-features: - HPD pin is not usable - although resolution is 640x480, only top 240 pixels are visible $ xxd -p display.edid 00ffffffffffff0005a1e00301000000150f0103800f05780a0f6ea05748 9a2610474f200000010101010101010101010101010101012a08804520e0 0b1020004000953600000018000000fd0034441a2403000a202020202020 0000001000310a20202020202020202020200000001000002a4030701300 782d1100001e006b $ edid-decode display.edid EDID version: 1.3 Manufacturer: AMA Model 3e0 Serial Number 1 Digital display Maximum image size: 15 cm x 5 cm Gamma: 2.20 RGB color display First detailed timing is preferred timing Display x,y Chromaticity: Red: 0.6250, 0.3398 Green: 0.2841, 0.6044 Blue: 0.1494, 0.0644 White: 0.2802, 0.3105 Established timings supported: 640x480@60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz Standard timings supported: Detailed mode: Clock 20.900 MHz, 149 mm x 54 mm 640 672 672 709 hborder 0 480 484 484 491 vborder 0 -hsync -vsync VertFreq: 60 Hz, HorFreq: 29478 Hz Monitor ranges (GTF): 52-68Hz V, 26-36kHz H, max dotclock 30MHz Dummy block Dummy block Checksum: 0x6b (valid) Signed-off-by: Priit Laes <priit.laes(a)paf.com> --- drivers/video/videomodes.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c index 74bafff011..1cfeaa980f 100644 --- a/drivers/video/videomodes.c +++ b/drivers/video/videomodes.c @@ -396,9 +396,7 @@ int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t, EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*t) == 0 || EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 || EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 || - EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*t) == 0 || EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 || - EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*t) == 0 || /* 3d formats are not supported*/ EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0) return -EINVAL; -- 2.11.0

3 7

[U-Boot] [PATCH] sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters array
by Ye Li 15 Feb '19

15 Feb '19

On i.MX7ULP EVK board, we use MX25R6435F NOR flash, add its parameters and IDs to flash parameter array. Otherwise, the flash probe will fails. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/mtd/spi/spi_flash_ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index ad0a0c8..17f9893 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -94,6 +94,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"mx25u25635f", INFO(0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, + {"mx25r6435f", INFO(0xc22817, 0x0, 64 * 1024, 128, RD_FULL | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, -- 2.7.4

3 2

[U-Boot] [RFC 0/9] Convert Pico-Pi i.MX7D to DM
by Joris Offouga 15 Feb '19

15 Feb '19

Hi all, Pinctrl, GPIO, I2C, MMC, ETH are converted. Convert PMIC is the same of warp7 but i have a some erros, si this log : U-Boot SPL 2019.01-00197-ga524e5d-dirty (Jan 20 2019 - 21:09:49 +0100) Trying to boot from USB SDP SDP: initialize... SDP: handle requests... Downloading file of size 556397 to 0x877fffc0... done Jumping to header at 0x877fffc0 Header Tag is not an IMX image U-Boot 2019.01-00197-ga524e5d-dirty (Jan 20 2019 - 21:09:49 +0100) CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: TechNexion PICO-IMX7D Board and PI baseboard Board: i.MX7D PICOSOM DRAM: 512 MiB read error from device: 9df65458 register: 0x3! PMIC: PFUZE3000 DEV_ID=0x0 REV_ID=0xfffffffb read error from device: 9df65458 register: 0x69! write error to device: 9df65458 register: 0x23! write error to device: 9df65458 register: 0x31! write error to device: 9df65458 register: 0x21! write error to device: 9df65458 register: 0x2f! read error from device: 9df65458 register: 0x2e! write error to device: 9df65458 register: 0x2e! MMC: FSL_SDHC: 2, FSL_SDHC: 1, FSL_SDHC: 0 Loading Environment from MMC... OK In: serial@30a70000 Out: serial@30a70000 Err: serial@30a70000 Net: Warning: ethernet@30be0000 using MAC address from ROM eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 USB is convert but update u-boot with dfu log a error : => dfu 0 mmc 0 Request would exceed designated area! #Deferred dfu_flush() failed!=> Thanks a advance for your help. Best Regards, Joris Offouga Joris Offouga (9): Arm: dts: imx7d-pico: Import Linux pico-pi dts Arm: imx7d-pico: Add DT file hooks pico-pi-imx7d: defconfig Enable DM gpio pinctrl and pinctrl_imx7 arm: imx7d-pico-pi: Convert to DM MMC initialization pico-pi-imx7d: defconfig: Switch to DM for I2C pico-imx7d-pico: defconfig: Switch to DM for UART pico-imx7d: Convert to DM PMIC arm: pico-pi-imx7d: Convert to DM USB pico-imx7d: Convert to DM Ethernet arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx7d-pico-pi.dts | 102 ++++++ arch/arm/dts/imx7d-pico.dtsi | 588 +++++++++++++++++++++++++++++++ board/technexion/pico-imx7d/pico-imx7d.c | 105 +----- configs/pico-pi-imx7d_defconfig | 17 +- include/configs/pico-imx7d.h | 11 - 6 files changed, 726 insertions(+), 100 deletions(-) create mode 100644 arch/arm/dts/imx7d-pico-pi.dts create mode 100644 arch/arm/dts/imx7d-pico.dtsi -- 2.7.4

6 33

[U-Boot] [PATCH 0/2] Make nyan-big working..
by Tristan Bastian 14 Feb '19

14 Feb '19

Another problem is, that the internal keyboard is not working on the current master. A change of the SPI deactive delay solves that. A workaround for the current master was to press [reload/refresh]+[power] button. With the second patch this is no longer needed.

2 6

[U-Boot] [PATCH v4 1/1] avb: add support for named persistent values
by Igor Opaniuk 14 Feb '19

14 Feb '19

AVB version 1.1 introduces support for named persistent values that must be tamper evident and allows AVB to store arbitrary key-value pairs [1]. Introduce implementation of two additional AVB operations read_persistent_value()/write_persistent_value() for retrieving/storing named persistent values. Correspondent pull request in the OP-TEE OS project repo [2]. [1]: https://android.googlesource.com/platform/external/avb/+/android-9.0.0_r22 [2]: https://github.com/OP-TEE/optee_os/pull/2699 Signed-off-by: Igor Opaniuk <igor.opaniuk(a)linaro.org> --- v4: - extend tee sandbox tee driver to support persistent values - fix/re-test avb_persistent test on sandbox configuration: $ ./test/py/test.py --bd sandbox --build -s -i avb_per U-Boot 2019.01-06051-gd01806a-dirty (Jan 27 2019 - 11:56:41 +0200) Model: sandbox DRAM: 128 MiB MMC: MMC probed MMC probed MMC probed mmc2: 2 (SD), mmc1: 1 (SD), mmc0: 0 (SD) In: serial Out: vidconsole Err: vidconsole Model: sandbox SCSI: Net: eth0: eth@10002000, eth5: eth@10003000, eth3: sbe5, eth1: eth@10004000 Hit any key to stop autoboot: 0 => => avb init 1 => => avb write_pvalue test value_value Wrote 12 bytes => => avb read_pvalue test 12 Read 12 bytes, value = value_value => test/py/tests/test_avb.py . ===== 464 tests deselected by '-kavb_per' ====== === 1 passed, 464 deselected in 0.16 seconds === v3: - fix possible mem lick in avb_read_persistent/avb_write_persistent - add additional sanity checks - cover avb read_pvalue/write_pvalue commands with python tests v2: - fix output format for avb read_pvalue/write_pvalue commands - fix issue with named value buffer size cmd/avb.c | 78 ++++++++++++++++++++++++++++ common/avb_verify.c | 125 +++++++++++++++++++++++++++++++++++++++++++++ drivers/tee/sandbox.c | 80 +++++++++++++++++++++++++++++ include/tee.h | 2 + include/tee/optee_ta_avb.h | 16 ++++++ test/py/tests/test_avb.py | 16 ++++++ 6 files changed, 317 insertions(+) diff --git a/cmd/avb.c b/cmd/avb.c index ff00be4..c5af4a2 100644 --- a/cmd/avb.c +++ b/cmd/avb.c @@ -340,6 +340,76 @@ int do_avb_is_unlocked(cmd_tbl_t *cmdtp, int flag, return CMD_RET_FAILURE; } +int do_avb_read_pvalue(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + const char *name; + size_t bytes; + size_t bytes_read; + void *buffer; + char *endp; + + if (!avb_ops) { + printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + return CMD_RET_FAILURE; + } + + if (argc != 3) + return CMD_RET_USAGE; + + name = argv[1]; + bytes = simple_strtoul(argv[2], &endp, 10); + if (*endp && *endp != '\n') + return CMD_RET_USAGE; + + buffer = malloc(bytes); + if (!buffer) + return CMD_RET_FAILURE; + + if (avb_ops->read_persistent_value(avb_ops, name, bytes, buffer, + &bytes_read) == AVB_IO_RESULT_OK) { + printf("Read %ld bytes, value = %s\n", bytes_read, + (char *)buffer); + free(buffer); + return CMD_RET_SUCCESS; + } + + printf("Failed to read persistent value\n"); + + free(buffer); + + return CMD_RET_FAILURE; +} + +int do_avb_write_pvalue(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + const char *name; + const char *value; + + if (!avb_ops) { + printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + return CMD_RET_FAILURE; + } + + if (argc != 3) + return CMD_RET_USAGE; + + name = argv[1]; + value = argv[2]; + + if (avb_ops->write_persistent_value(avb_ops, name, strlen(value) + 1, + (const uint8_t *)value) == + AVB_IO_RESULT_OK) { + printf("Wrote %ld bytes\n", strlen(value) + 1); + return CMD_RET_SUCCESS; + } + + printf("Failed to write persistent value\n"); + + return CMD_RET_FAILURE; +} + static cmd_tbl_t cmd_avb[] = { U_BOOT_CMD_MKENT(init, 2, 0, do_avb_init, "", ""), U_BOOT_CMD_MKENT(read_rb, 2, 0, do_avb_read_rb, "", ""), @@ -350,6 +420,10 @@ static cmd_tbl_t cmd_avb[] = { U_BOOT_CMD_MKENT(read_part_hex, 4, 0, do_avb_read_part_hex, "", ""), U_BOOT_CMD_MKENT(write_part, 5, 0, do_avb_write_part, "", ""), U_BOOT_CMD_MKENT(verify, 1, 0, do_avb_verify_part, "", ""), +#ifdef CONFIG_OPTEE_TA_AVB + U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_avb_read_pvalue, "", ""), + U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_avb_write_pvalue, "", ""), +#endif }; static int do_avb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -384,6 +458,10 @@ U_BOOT_CMD( " partition <partname> and print to stdout\n" "avb write_part <partname> <offset> <num> <addr> - write <num> bytes to\n" " <partname> by <offset> using data from <addr>\n" +#ifdef CONFIG_OPTEE_TA_AVB + "avb read_pvalue <name> <bytes> - read a persistent value <name>\n" + "avb write_pvalue <name> <value> - write a persistent value <name>\n" +#endif "avb verify - run verification process using hash data\n" " from vbmeta structure\n" ); diff --git a/common/avb_verify.c b/common/avb_verify.c index a8c5a3e..32034d9 100644 --- a/common/avb_verify.c +++ b/common/avb_verify.c @@ -647,6 +647,10 @@ static AvbIOResult invoke_func(struct AvbOpsData *ops_data, u32 func, return AVB_IO_RESULT_OK; case TEE_ERROR_OUT_OF_MEMORY: return AVB_IO_RESULT_ERROR_OOM; + case TEE_ERROR_STORAGE_NO_SPACE: + return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE; + case TEE_ERROR_ITEM_NOT_FOUND: + return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE; case TEE_ERROR_TARGET_DEAD: /* * The TA has paniced, close the session to reload the TA @@ -847,6 +851,123 @@ static AvbIOResult get_size_of_partition(AvbOps *ops, return AVB_IO_RESULT_OK; } +static AvbIOResult read_persistent_value(AvbOps *ops, + const char *name, + size_t buffer_size, + u8 *out_buffer, + size_t *out_num_bytes_read) +{ + AvbIOResult rc; + struct tee_shm *shm_name; + struct tee_shm *shm_buf; + struct tee_param param[2]; + struct udevice *tee; + size_t name_size = strlen(name) + 1; + + if (get_open_session(ops->user_data)) + return AVB_IO_RESULT_ERROR_IO; + + tee = ((struct AvbOpsData *)ops->user_data)->tee; + + rc = tee_shm_alloc(tee, name_size, + TEE_SHM_ALLOC, &shm_name); + if (rc) + return AVB_IO_RESULT_ERROR_OOM; + + rc = tee_shm_alloc(tee, buffer_size, + TEE_SHM_ALLOC, &shm_buf); + if (rc) { + rc = AVB_IO_RESULT_ERROR_OOM; + goto free_name; + } + + memcpy(shm_name->addr, name, name_size); + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[0].u.memref.shm = shm_name; + param[0].u.memref.size = name_size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT; + param[1].u.memref.shm = shm_buf; + param[1].u.memref.size = buffer_size; + + rc = invoke_func(ops->user_data, TA_AVB_CMD_READ_PERSIST_VALUE, + 2, param); + if (rc) + goto out; + + if (param[1].u.memref.size > buffer_size) { + rc = AVB_IO_RESULT_ERROR_NO_SUCH_VALUE; + goto out; + } + + *out_num_bytes_read = param[1].u.memref.size; + + memcpy(out_buffer, shm_buf->addr, *out_num_bytes_read); + +out: + tee_shm_free(shm_buf); +free_name: + tee_shm_free(shm_name); + + return rc; +} + +static AvbIOResult write_persistent_value(AvbOps *ops, + const char *name, + size_t value_size, + const u8 *value) +{ + AvbIOResult rc; + struct tee_shm *shm_name; + struct tee_shm *shm_buf; + struct tee_param param[2]; + struct udevice *tee; + size_t name_size = strlen(name) + 1; + + if (get_open_session(ops->user_data)) + return AVB_IO_RESULT_ERROR_IO; + + tee = ((struct AvbOpsData *)ops->user_data)->tee; + + if (!value_size) + return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE; + + rc = tee_shm_alloc(tee, name_size, + TEE_SHM_ALLOC, &shm_name); + if (rc) + return AVB_IO_RESULT_ERROR_OOM; + + rc = tee_shm_alloc(tee, value_size, + TEE_SHM_ALLOC, &shm_buf); + if (rc) { + rc = AVB_IO_RESULT_ERROR_OOM; + goto free_name; + } + + memcpy(shm_name->addr, name, name_size); + memcpy(shm_buf->addr, value, value_size); + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[0].u.memref.shm = shm_name; + param[0].u.memref.size = name_size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[1].u.memref.shm = shm_buf; + param[1].u.memref.size = value_size; + + rc = invoke_func(ops->user_data, TA_AVB_CMD_WRITE_PERSIST_VALUE, + 2, param); + if (rc) + goto out; + +out: + tee_shm_free(shm_buf); +free_name: + tee_shm_free(shm_name); + + return rc; +} /** * ============================================================================ * AVB2.0 AvbOps alloc/initialisation/free @@ -870,6 +991,10 @@ AvbOps *avb_ops_alloc(int boot_device) ops_data->ops.read_is_device_unlocked = read_is_device_unlocked; ops_data->ops.get_unique_guid_for_partition = get_unique_guid_for_partition; +#ifdef CONFIG_OPTEE_TA_AVB + ops_data->ops.write_persistent_value = write_persistent_value; + ops_data->ops.read_persistent_value = read_persistent_value; +#endif ops_data->ops.get_size_of_partition = get_size_of_partition; ops_data->mmc_dev = boot_device; diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c index ccddb03..5fecce0 100644 --- a/drivers/tee/sandbox.c +++ b/drivers/tee/sandbox.c @@ -5,6 +5,7 @@ #include <common.h> #include <dm.h> #include <sandboxtee.h> +#include <search.h> #include <tee.h> #include <tee/optee_ta_avb.h> @@ -61,6 +62,8 @@ bad_params: static u64 ta_avb_rollback_indexes[TA_AVB_MAX_ROLLBACK_LOCATIONS]; static u32 ta_avb_lock_state; +static struct hsearch_data pstorage_htab; +static const u32 pstorage_max = 16; static u32 ta_avb_open_session(uint num_params, struct tee_param *params) { @@ -76,9 +79,13 @@ static u32 ta_avb_open_session(uint num_params, struct tee_param *params) static u32 ta_avb_invoke_func(u32 func, uint num_params, struct tee_param *params) { + ENTRY e, *ep; + char *name; u32 res; uint slot; u64 val; + char *value; + u32 value_sz; switch (func) { case TA_AVB_CMD_READ_ROLLBACK_INDEX: @@ -151,6 +158,57 @@ static u32 ta_avb_invoke_func(u32 func, uint num_params, } return TEE_SUCCESS; + case TA_AVB_CMD_READ_PERSIST_VALUE: + res = check_params(TEE_PARAM_ATTR_TYPE_MEMREF_INPUT, + TEE_PARAM_ATTR_TYPE_MEMREF_INOUT, + TEE_PARAM_ATTR_TYPE_NONE, + TEE_PARAM_ATTR_TYPE_NONE, + num_params, params); + if (res) + return res; + + name = params[0].u.memref.shm->addr; + + value = params[1].u.memref.shm->addr; + value_sz = params[1].u.memref.size; + + e.key = name; + e.data = NULL; + hsearch_r(e, FIND, &ep, &pstorage_htab, 0); + if (!ep) + return TEE_ERROR_ITEM_NOT_FOUND; + + value_sz = strlen(ep->data); + memcpy(value, ep->data, value_sz); + + return TEE_SUCCESS; + case TA_AVB_CMD_WRITE_PERSIST_VALUE: + res = check_params(TEE_PARAM_ATTR_TYPE_MEMREF_INPUT, + TEE_PARAM_ATTR_TYPE_MEMREF_INPUT, + TEE_PARAM_ATTR_TYPE_NONE, + TEE_PARAM_ATTR_TYPE_NONE, + num_params, params); + if (res) + return res; + + name = params[0].u.memref.shm->addr; + + value = params[1].u.memref.shm->addr; + value_sz = params[1].u.memref.size; + + e.key = name; + e.data = NULL; + hsearch_r(e, FIND, &ep, &pstorage_htab, 0); + if (ep) + hdelete_r(e.key, &pstorage_htab, 0); + + e.key = name; + e.data = value; + hsearch_r(e, ENTER, &ep, &pstorage_htab, 0); + if (!ep) + return TEE_ERROR_OUT_OF_MEMORY; + + return TEE_SUCCESS; default: return TEE_ERROR_NOT_SUPPORTED; @@ -285,6 +343,26 @@ static int sandbox_tee_shm_unregister(struct udevice *dev, struct tee_shm *shm) return 0; } +static int sandbox_tee_remove(struct udevice *dev) +{ + hdestroy_r(&pstorage_htab); + + return 0; +} + +static int sandbox_tee_probe(struct udevice *dev) +{ + /* + * With this hastable we emulate persistent storage, + * which should contain persistent values + * between different sessions/command invocations. + */ + if (!hcreate_r(pstorage_max, &pstorage_htab)) + return TEE_ERROR_OUT_OF_MEMORY; + + return 0; +} + static const struct tee_driver_ops sandbox_tee_ops = { .get_version = sandbox_tee_get_version, .open_session = sandbox_tee_open_session, @@ -305,4 +383,6 @@ U_BOOT_DRIVER(sandbox_tee) = { .of_match = sandbox_tee_match, .ops = &sandbox_tee_ops, .priv_auto_alloc_size = sizeof(struct sandbox_tee_state), + .probe = sandbox_tee_probe, + .remove = sandbox_tee_remove, }; diff --git a/include/tee.h b/include/tee.h index edd9f9b..02bcd9e 100644 --- a/include/tee.h +++ b/include/tee.h @@ -43,7 +43,9 @@ #define TEE_ERROR_COMMUNICATION 0xffff000e #define TEE_ERROR_SECURITY 0xffff000f #define TEE_ERROR_OUT_OF_MEMORY 0xffff000c +#define TEE_ERROR_OVERFLOW 0xffff300f #define TEE_ERROR_TARGET_DEAD 0xffff3024 +#define TEE_ERROR_STORAGE_NO_SPACE 0xffff3041 #define TEE_ORIGIN_COMMS 0x00000002 #define TEE_ORIGIN_TEE 0x00000003 diff --git a/include/tee/optee_ta_avb.h b/include/tee/optee_ta_avb.h index 074386a..949875a 100644 --- a/include/tee/optee_ta_avb.h +++ b/include/tee/optee_ta_avb.h @@ -45,4 +45,20 @@ */ #define TA_AVB_CMD_WRITE_LOCK_STATE 3 +/* + * Reads a persistent value corresponding to the given name. + * + * in params[0].u.memref: persistent value name + * out params[1].u.memref: read persistent value buffer + */ +#define TA_AVB_CMD_READ_PERSIST_VALUE 4 + +/* + * Writes a persistent value corresponding to the given name. + * + * in params[0].u.memref: persistent value name + * in params[1].u.memref: persistent value buffer to write + */ +#define TA_AVB_CMD_WRITE_PERSIST_VALUE 5 + #endif /* __TA_AVB_H */ diff --git a/test/py/tests/test_avb.py b/test/py/tests/test_avb.py index e70a010..2bb75ed 100644 --- a/test/py/tests/test_avb.py +++ b/test/py/tests/test_avb.py @@ -116,3 +116,19 @@ def test_avb_mmc_read(u_boot_console): response = u_boot_console.run_command('cmp 0x%x 0x%x 40' % (temp_addr, temp_addr2)) assert response.find('64 word') + + +(a)pytest.mark.buildconfigspec('cmd_avb') +(a)pytest.mark.buildconfigspec('optee_ta_avb') +def test_avb_persistent_values(u_boot_console): + """Test reading/writing persistent storage to avb + """ + + response = u_boot_console.run_command('avb init %s' % str(mmc_dev)) + assert response == '' + + response = u_boot_console.run_command('avb write_pvalue test value_value') + assert response == 'Wrote 12 bytes' + + response = u_boot_console.run_command('avb read_pvalue test 12') + assert response == 'Read 12 bytes, value = value_value' -- 2.7.4

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[U-Boot] [PATCH v2] rpi: add Compute Module 3+
by Jonathan Gray 14 Feb '19

14 Feb '19

Add Raspberry Pi Compute Module 3+ to list of models, the revision code is 0x10 according to the list on raspberrypi.org. v2: Use the same dtb name as CM3 as CM3+ is a drop in replacement for CM3. Signed-off-by: Jonathan Gray <jsg(a)jsg.id.au> --- board/raspberrypi/rpi/rpi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 153a1fdcb7..617c892dde 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -143,6 +143,11 @@ static const struct rpi_model rpi_models_new_scheme[] = { DTB_DIR "bcm2837-rpi-3-a-plus.dtb", false, }, + [0x10] = { + "Compute Module 3+", + DTB_DIR "bcm2837-rpi-cm3.dtb", + false, + }, }; static const struct rpi_model rpi_models_old_scheme[] = { -- 2.20.1

2 1

[U-Boot] [PATCH v3] net: phy: add TSE PCS support to dwmac-socfpga
by Ooi, Joyce 14 Feb '19

14 Feb '19

This adds support for TSE PCS (Triple Speed Ethernet Physical Coding Sublayer) that uses SGMII adapter when the phy-mode in device tree is set to sgmii. Signed-off-by: Ooi, Joyce <joyce.ooi(a)intel.com> --- arch/arm/mach-socfpga/include/mach/misc.h | 3 + arch/arm/mach-socfpga/misc_s10.c | 6 + drivers/net/Makefile | 3 +- drivers/net/designware.c | 5 + drivers/net/designware.h | 1 + drivers/net/dwmac_socfpga.c | 122 +++++++++++++++++++ drivers/net/phy/altr_tse_pcs.c | 184 +++++++++++++++++++++++++++++ drivers/net/phy/altr_tse_pcs.h | 56 +++++++++ 8 files changed, 379 insertions(+), 1 deletions(-) create mode 100644 drivers/net/phy/altr_tse_pcs.c create mode 100644 drivers/net/phy/altr_tse_pcs.h --- v2: add a __weak function to make it compatible for all socfpga platforms v3: remove __weak function and use board-specific implementation instead diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 4fc9570..751705e 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -30,6 +30,9 @@ void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +int socfpga_test_fpga_ready(void); +#endif void do_bridge_reset(int enable); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index e599362..3cd9c30 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -11,6 +11,7 @@ #include <miiphy.h> #include <netdev.h> #include <asm/io.h> +#include <asm/arch/mailbox_s10.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> #include <asm/arch/misc.h> @@ -91,6 +92,11 @@ static int socfpga_set_phymode(void) return 0; } + +int socfpga_test_fpga_ready(void) +{ + return mbox_get_fpga_config_status(MBOX_CONFIG_STATUS); +} #else static int socfpga_set_phymode(void) { diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 48a2878..c2333b5 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o -obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o +obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac-socfpga.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DNET) += dnet.o obj-$(CONFIG_E1000) += e1000.o @@ -73,3 +73,4 @@ obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +dwmac-socfpga-objs := phy/altr_tse_pcs.o dwmac_socfpga.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 19db0a8..666cf41 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -235,6 +235,8 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, struct phy_device *phydev) { u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; + struct udevice *dev = priv->phydev->dev; + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); if (!phydev->link) { printf("%s: No link.\n", phydev->dev->name); @@ -254,6 +256,9 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, writel(conf, &mac_p->conf); + if (dw_pdata->pcs_adjust_link) + dw_pdata->pcs_adjust_link(dev, phydev); + printf("Speed: %d, %s duplex%s\n", phydev->speed, (phydev->duplex) ? "full" : "half", (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index dea12b7..3a5a93f 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -255,6 +255,7 @@ extern const struct eth_ops designware_eth_ops; struct dw_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; + void (*pcs_adjust_link)(struct udevice *dev, struct phy_device *phydev); }; int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr); diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 08fc967..7d13f3c 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -9,12 +9,16 @@ #include <asm/io.h> #include <dm.h> #include <clk.h> +#include <fdt_support.h> #include <phy.h> #include <regmap.h> #include <reset.h> #include <syscon.h> #include "designware.h" +#include "phy/altr_tse_pcs.h" +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> enum dwmac_type { @@ -27,8 +31,123 @@ struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; enum dwmac_type type; void *phy_intf; + struct tse_pcs pcs; }; +static void socfpga_tse_pcs_adjust_link(struct udevice *dev, + struct phy_device *phydev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + phys_addr_t tse_pcs_base = pdata->pcs.tse_pcs_base; + phys_addr_t sgmii_adapter_base = pdata->pcs.sgmii_adapter_base; + + if ((tse_pcs_base) && (sgmii_adapter_base)) + writew(SGMII_ADAPTER_DISABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + + if ((tse_pcs_base) && (sgmii_adapter_base)) + tse_pcs_fix_mac_speed(&pdata->pcs, phydev, phydev->speed); +} + +static int socfpga_dw_tse_pcs_init(struct udevice *dev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + struct dw_eth_pdata *dw_pdata = &pdata->dw_eth_pdata; + struct eth_pdata *eth_pdata = &pdata->dw_eth_pdata.eth_pdata; + phys_addr_t tse_pcs_base = pdata->pcs.tse_pcs_base; + phys_addr_t sgmii_adapter_base = pdata->pcs.sgmii_adapter_base; + const fdt32_t *reg; + int ret = 0; + int parent, index, na, ns, offset, len; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), + "altr,gmii-to-sgmii-converter"); + if (offset > 0) { +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 + /* check FPGA status */ + ret = socfpga_test_fpga_ready(); + if (ret) { + debug("%s: FPGA not ready (%d)\n", __func__, ret); + return -EPERM; + } +#endif + /* enable HPS bridge */ + do_bridge_reset(1); + + parent = fdt_parent_offset(gd->fdt_blob, offset); + if (parent < 0) { + debug("s10-hps-bridge DT not found\n"); + return -ENODEV; + } + + na = fdt_address_cells(gd->fdt_blob, parent); + if (na < 1) { + debug("bad #address-cells\n"); + return -EINVAL; + } + + ns = fdt_size_cells(gd->fdt_blob, parent); + if (ns < 1) { + debug("bad #size-cells\n"); + return -EINVAL; + } + + index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", + "eth_tse_control_port"); + if (index < 0) { + debug("fail to find eth_tse_control_port: %s\n", + fdt_strerror(index)); + return -ENOENT; + } + + reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) + return -EINVAL; + + reg += index * (na + ns); + tse_pcs_base = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (tse_pcs_base == FDT_ADDR_T_NONE) { + debug("tse pcs address not found\n"); + return -EINVAL; + } + + index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", + "gmii_to_sgmii_adapter_avalon_slave"); + if (index < 0) { + debug("fail to find gmii_to_sgmii_adapter_avalon_slave: %s\n", + fdt_strerror(index)); + return -EINVAL; + } + + reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) + return -EINVAL; + + reg += index * (na + ns); + sgmii_adapter_base = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (sgmii_adapter_base == FDT_ADDR_T_NONE) { + debug("gmii-to-sgmii adapter address not found\n"); + return -EINVAL; + } + + if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_SGMII) { + if (tse_pcs_init(tse_pcs_base, &pdata->pcs) != 0) { + debug("Unable to intiialize TSE PCS\n"); + return -EINVAL; + } + } + /* Clear sgmii_adapter_base first */ + writel(0, sgmii_adapter_base); + + pdata->pcs.tse_pcs_base = tse_pcs_base; + pdata->pcs.sgmii_adapter_base = sgmii_adapter_base; + dw_pdata->pcs_adjust_link = socfpga_tse_pcs_adjust_link; + } + return ret; +} + static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) { struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); @@ -94,6 +213,7 @@ static int dwmac_socfpga_probe(struct udevice *dev) switch (edata->phy_interface) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_SGMII: modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; break; case PHY_INTERFACE_MODE_RMII: @@ -122,6 +242,8 @@ static int dwmac_socfpga_probe(struct udevice *dev) reset_release_bulk(&reset_bulk); } + socfpga_dw_tse_pcs_init(dev); + return designware_eth_probe(dev); } diff --git a/drivers/net/phy/altr_tse_pcs.c b/drivers/net/phy/altr_tse_pcs.c new file mode 100644 index 0000000..4423538 --- /dev/null +++ b/drivers/net/phy/altr_tse_pcs.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Intel Corporation <www.intel.com> + */ + +#include <asm/io.h> +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <net.h> +#include <linux/compat.h> +#include <phy.h> +#include <timer.h> +#include <wait_bit.h> +#include <linux/ethtool.h> + +#include <asm/omap_common.h> +#include <asm/omap_musb.h> + +#include "altr_tse_pcs.h" + +static int tse_pcs_reset(phys_addr_t base, struct tse_pcs *pcs) +{ + int ret; + u16 val; + phys_addr_t reg = base + TSE_PCS_CONTROL_REG; + + val = readw(reg); + val |= TSE_PCS_SW_RST_MASK; + + writew(val, reg); + + ret = wait_for_bit_le16(&reg, TSE_PCS_SW_RST_MASK, false, + TSE_PCS_SW_RESET_TIMEOUT, false); + + if (ret) { + debug("%s: PCS could not get out of sw reset\n", __func__); + return -ETIMEDOUT; + } + + return 0; +} + +int tse_pcs_init(phys_addr_t base, struct tse_pcs *pcs) +{ + int ret = 0; + + writew(TSE_PCS_USE_SGMII_ENA, base + TSE_PCS_IF_MODE_REG); + writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG); + writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG); + + ret = tse_pcs_reset(base, pcs); + if (ret == 0) + writew(SGMII_ADAPTER_ENABLE, + pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + + return ret; +} + +static void pcs_link_timer_callback(struct tse_pcs *pcs) +{ + u16 val = 0; + phys_addr_t tse_pcs_base = pcs->tse_pcs_base; + phys_addr_t sgmii_adapter_base = pcs->sgmii_adapter_base; + + val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); + val &= TSE_PCS_STATUS_LINK_MASK; + + if (val != 0) { + printf("Adapter: Link is established\n"); + writew(SGMII_ADAPTER_ENABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + } else { + printf("Adapter: Link fail to establish\n"); + } +} + +static void auto_nego_timer_callback(struct tse_pcs *pcs) +{ + u16 val = 0; + u16 speed = 0; + u16 duplex = 0; + phys_addr_t tse_pcs_base = pcs->tse_pcs_base; + phys_addr_t sgmii_adapter_base = pcs->sgmii_adapter_base; + + val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); + val &= TSE_PCS_STATUS_AN_COMPLETED_MASK; + + if (val != 0) { + printf("Adapter: Auto Negotiation is completed\n"); + val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG); + speed = val & TSE_PCS_PARTNER_SPEED_MASK; + duplex = val & TSE_PCS_PARTNER_DUPLEX_MASK; + + if (duplex == TSE_PCS_PARTNER_DUPLEX_FULL) { + if (speed == TSE_PCS_PARTNER_SPEED_10) + printf("Adapter: Link Partner is Up - 10/Full\n"); + else if (speed == TSE_PCS_PARTNER_SPEED_100) + printf("Adapter: Link Partner is Up - 100/Full\n"); + else if (speed == TSE_PCS_PARTNER_SPEED_1000) + printf("Adapter: Link Partner is Up - 1000/Full\n"); + } else if (duplex == TSE_PCS_PARTNER_DUPLEX_HALF) + printf("Adapter does not support Half Duplex\n"); + else + printf("Adapter: Invalid Partner Speed and Duplex\n"); + + if (duplex == TSE_PCS_PARTNER_DUPLEX_FULL && + (speed == TSE_PCS_PARTNER_SPEED_10 || + speed == TSE_PCS_PARTNER_SPEED_100 || + speed == TSE_PCS_PARTNER_SPEED_1000)) + writew(SGMII_ADAPTER_ENABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + } else { + printf("Auto-negotioation failed\n"); + } +} + +void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev, + unsigned int speed) +{ + phys_addr_t tse_pcs_base = pcs->tse_pcs_base; + phys_addr_t sgmii_adapter_base = pcs->sgmii_adapter_base; + u32 val, start; + + writew(SGMII_ADAPTER_ENABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + pcs->autoneg = phy_dev->autoneg; + + if (pcs->autoneg == AUTONEG_ENABLE) { + val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); + val |= TSE_PCS_CONTROL_AN_EN_MASK; + writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG); + + val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); + val |= TSE_PCS_USE_SGMII_AN_MASK; + writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); + + val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); + val |= TSE_PCS_CONTROL_RESTART_AN_MASK; + + tse_pcs_reset(tse_pcs_base, pcs); + + } else if (pcs->autoneg == AUTONEG_DISABLE) { + val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); + val &= ~TSE_PCS_CONTROL_AN_EN_MASK; + writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG); + + val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); + val &= ~TSE_PCS_USE_SGMII_AN_MASK; + writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); + + val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); + val &= ~TSE_PCS_SGMII_SPEED_MASK; + + switch (speed) { + case 1000: + val |= TSE_PCS_SGMII_SPEED_1000; + break; + case 100: + val |= TSE_PCS_SGMII_SPEED_100; + break; + case 10: + val |= TSE_PCS_SGMII_SPEED_10; + break; + default: + return; + } + writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); + + tse_pcs_reset(tse_pcs_base, pcs); + } + + start = get_timer(0); + while (1) { + if (get_timer(start) >= AUTONEGO_LINK_TIMER) { + if (pcs->autoneg == AUTONEG_ENABLE) + auto_nego_timer_callback(pcs); + else if (pcs->autoneg == AUTONEG_DISABLE) + pcs_link_timer_callback(pcs); + return; + } + udelay(100); + } +} diff --git a/drivers/net/phy/altr_tse_pcs.h b/drivers/net/phy/altr_tse_pcs.h new file mode 100644 index 0000000..0e8d4f4 --- /dev/null +++ b/drivers/net/phy/altr_tse_pcs.h @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Intel Corporation <www.intel.com> + */ + +#ifndef __TSE_PCS_H__ +#define __TSE_PCS_H__ + +#define TSE_PCS_CONTROL_AN_EN_MASK BIT(12) +#define TSE_PCS_CONTROL_REG 0x00 +#define TSE_PCS_CONTROL_RESTART_AN_MASK BIT(9) +#define TSE_PCS_IF_MODE_REG 0x28 +#define TSE_PCS_LINK_TIMER_0_REG 0x24 +#define TSE_PCS_LINK_TIMER_1_REG 0x26 +#define TSE_PCS_SIZE 0x40 +#define TSE_PCS_STATUS_AN_COMPLETED_MASK BIT(5) +#define TSE_PCS_STATUS_LINK_MASK BIT(2) +#define TSE_PCS_STATUS_REG 0x02 +#define TSE_PCS_SGMII_SPEED_1000 BIT(3) +#define TSE_PCS_SGMII_SPEED_100 BIT(2) +#define TSE_PCS_SGMII_SPEED_10 0x0 +#define TSE_PCS_SGMII_SPEED_MASK GENMASK(3, 2) +#define TSE_PCS_SW_RST_MASK BIT(15) +#define TSE_PCS_PARTNER_ABILITY_REG 0x0A +#define TSE_PCS_PARTNER_DUPLEX_FULL BIT(12) +#define TSE_PCS_PARTNER_DUPLEX_HALF 0x0000 +#define TSE_PCS_PARTNER_DUPLEX_MASK BIT(12) +#define TSE_PCS_PARTNER_SPEED_MASK GENMASK(11, 10) +#define TSE_PCS_PARTNER_SPEED_1000 BIT(11) +#define TSE_PCS_PARTNER_SPEED_100 BIT(10) +#define TSE_PCS_PARTNER_SPEED_10 0x0000 +#define TSE_PCS_SGMII_LINK_TIMER_0 0x0D40 +#define TSE_PCS_SGMII_LINK_TIMER_1 0x0003 +#define TSE_PCS_SW_RESET_TIMEOUT 100 +#define TSE_PCS_USE_SGMII_AN_MASK BIT(1) +#define TSE_PCS_USE_SGMII_ENA BIT(0) + +#define SGMII_ADAPTER_CTRL_REG 0x00 +#define SGMII_ADAPTER_DISABLE 0x0001 +#define SGMII_ADAPTER_ENABLE 0x0000 + +#define AUTONEGO_LINK_TIMER 20 + +struct tse_pcs { + struct device *dev; + phys_addr_t tse_pcs_base; + phys_addr_t sgmii_adapter_base; + struct timer_list aneg_link_timer; + int autoneg; +}; + +int tse_pcs_init(phys_addr_t base, struct tse_pcs *pcs); +void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev, + unsigned int speed); + +#endif /* __TSE_PCS_H__ */ -- 1.7.1

2 19

[U-Boot] [PATCH 0/3] sunxi: Sync Bananapi M2+ dts files and add H5 variant
by Chen-Yu Tsai 14 Feb '19

14 Feb '19

This series adds support for the H5 variant of the Bananapi M2+, and also renames the MAINTAINERS entry and defconfig for the Bananapi M2+ from its current name, Sinovoip BPI M2+. Sinovoip is the brand name used for their own VOIP-related products, while the brand name "Bananapi" should be used for single board computers bearing the Bananapi logo. This was confirmed by Bananapi. Patch 1 syncs up the BPI-M2+ device tree file from Linux v5.0-rc1. Patch 2 renames the defconfig and maintainer entries to fix the brand name. Patch 3 adds support for the H5 variant of the Bananapi M2+. Please have a look. Regards ChenYu Chen-Yu Tsai (3): sunxi: Sync Bananapi M2+ device tree from Linux v5.0-rc1 sunxi: Rename Sinovoip BPI M2 Plus to Bananapi M2 Plus H3 sunxi: Add Bananapi M2+ H5 board arch/arm/dts/sun50i-h5-bananapi-m2-plus.dts | 11 + arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 190 +----------------- ...2-plus.dts => sunxi-bananapi-m2-plus.dtsi} | 23 ++- board/sunxi/MAINTAINERS | 13 +- configs/Sinovoip_BPI_M2_Plus_defconfig | 21 +- ...efconfig => bananapi_m2_plus_h3_defconfig} | 0 ...efconfig => bananapi_m2_plus_h5_defconfig} | 4 +- 7 files changed, 40 insertions(+), 222 deletions(-) create mode 100644 arch/arm/dts/sun50i-h5-bananapi-m2-plus.dts copy arch/arm/dts/{sun8i-h3-bananapi-m2-plus.dts => sunxi-bananapi-m2-plus.dtsi} (92%) mode change 100644 => 120000 configs/Sinovoip_BPI_M2_Plus_defconfig copy configs/{Sinovoip_BPI_M2_Plus_defconfig => bananapi_m2_plus_h3_defconfig} (100%) copy configs/{Sinovoip_BPI_M2_Plus_defconfig => bananapi_m2_plus_h5_defconfig} (85%) -- 2.20.1

4 17

[U-Boot] [PATCH 0/8] pci: Add pcie controller driver for NXP LX SoCs
by Z.q. Hou 14 Feb '19

14 Feb '19

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Add PCIe driver for the NXP LX series SoCs. Hou Zhiqiang (8): armv8: fsl-layerscpae: correct the PCIe controllers' region size armv8: lx2160a: add MMU table entries for PCIe pci: Add pcie controller driver for NXP LX SoCs kconfig: add dependency PCIE_LX for FSL_PCIE_COMPAT pci: pcie_lx: add device tree fixups for PCI Stream IDs armv8: lx2160a: add pcie DT nodes armv8: lx2160a: enable pcie support on RDB defconfig armv8: lx2160a: enable the pci command Depends on the following patches: https://patchwork.ozlabs.org/patch/990088/ https://patchwork.ozlabs.org/patch/990093/ https://patchwork.ozlabs.org/patch/990097/ https://patchwork.ozlabs.org/patch/990098/ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12 + arch/arm/dts/fsl-lx2160a.dtsi | 85 +++ .../arm/include/asm/arch-fsl-layerscape/cpu.h | 9 + .../asm/arch-fsl-layerscape/immap_lsch3.h | 14 +- configs/lx2160ardb_tfa_defconfig | 5 + drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_lx.c | 607 ++++++++++++++++++ drivers/pci/pcie_lx.h | 258 ++++++++ drivers/pci/pcie_lx_fixup.c | 234 +++++++ include/configs/lx2160a_common.h | 1 + 12 files changed, 1234 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/pcie_lx.c create mode 100644 drivers/pci/pcie_lx.h create mode 100644 drivers/pci/pcie_lx_fixup.c -- 2.17.1

2 10

[U-Boot] [PATCH v7 0/7] Add support for loading FPGA bitstream
by tien.fong.chee＠intel.com 13 Feb '19

13 Feb '19

From: Tien Fong Chee <tien.fong.chee(a)intel.com> These series of patches enable peripheral bitstream being programmed into FPGA to get the DDR up running. This's also called early IO release, because the peripheral bitstream is only initializing FPGA IOs, PLL, IO48 and DDR. Once DDR is up running, core bitstream from MMC which contains user FPGA design would be loaded into DDR location. socfpga loadfs would be called to program core bitstream into FPGA and entering user mode. Lastly, u-boot-dtb.img from MMC FAT partition would be loaded to DDR, and up running from there. For this whole mechanism to work, the SDMMC flash layout would be designed as shown in below: RAW partition: 1. spl_w_dtb-mkpimage.bin mkpimage -hv 1 -o spl/spl_w_dtb-mkpimage.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin FAT partition contains: FPGA FIT image(fit_spl_fpga.itb) -------------------------------- Early IO release method is recommended for the sake of performance, improve up to 86% compare to full bitstream. To generate FPGA FIT image for Early IO release, runs this command: tools/mkimage -E -p 400 -f board/altera/arria10-socdk/fit_spl_fpga.its fit_spl_fpga.itb Before running above command, ensure U-Boot source directory contains both peripheral bitstream(ghrd_10as066n2.periph.rbf) and core bitstream(ghrd_10as066n2.core.rbf_. For details of describing structure and contents of the FIT image, please refer board/altera/arria10-socdk/fit_spl_fpga.its Additonal note: --------------- There is performance penalty if the memory used for loading the bitstream is unalligned to ARCH_DMA_MINALIGN inside function "static int get_cluster()" in fs/fat/fat.c. Sometimes child functions would alter the memory location and causing unalligned to ARCH_DMA_MINALIGN. This only happend when reading a FAT file by offset. To avoid performance penalty, core bitstream(fpga-2) contains large size should be at 1st then following by peripheral bitstream(fpga-1) as shown in fit_spl_fpga.its. After that, enable the DEBUG in fs/fat/fat.c and ensure no print out "FAT: Misaligned buffer address (%p)" when loading core bitstream on SPL console. Print out when loading peripheral bitstream can be ignored because the size is too small. If there is print out, please set an allign data position by running mkimage with optional -p xxx when generating FIT image. U-Boot image ------------ 3. u-boot-dtb.img For the testing purpose, these 3 series of patches are required to apply 1st before applying this series of patches. 1. [U-Boot] [PATCH v4] misc: fs_loader: Add support for initializing block device https://www.mail-archive.com/u-boot@lists.denx.de/msg314453.html Version 4 under review 2. [U-Boot] [PATCH v2 1/4] spl: Kconfig: Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FAT https://www.mail-archive.com/u-boot@lists.denx.de/msg313259.html All series Reviewed-by: Tom Rini <trini(a)konsulko.com> Some patches of the series Reviewed-by: Simon Goldschmidt 3. [U-Boot] [PATCH v2 1/2] fs: fat: dynamically allocate memory for temporary buffer https://www.mail-archive.com/u-boot@lists.denx.de/msg314470.html Version 2 under review This series is working on top of u-boot.git - http://git.denx.de/u-boot.git . Tien Fong Chee (7): ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK spl : socfpga: Implement fpga bitstream loading with socfpga loadfs ARM: socfpga: Synchronize the configuration for A10 SoCDK ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 18 + .../include/mach/fpga_manager_arria10.h | 39 +- arch/arm/mach-socfpga/spl_a10.c | 46 ++- board/altera/arria10-socdk/fit_spl_fpga.its | 31 ++ configs/socfpga_arria10_defconfig | 21 +- .../fpga/altera-socfpga-a10-fpga-mgr.txt | 34 +- drivers/fpga/socfpga_arria10.c | 417 ++++++++++++++++++++- include/configs/socfpga_common.h | 4 +- 8 files changed, 584 insertions(+), 26 deletions(-) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its -- 2.2.0

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