September 2018 - U-Boot

Re: [U-Boot] [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id
by Rick Chen 20 Sep '18

20 Sep '18

> From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Tuesday, September 11, 2018 12:55 PM > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > Cc: Lukas Auer > Subject: [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument > to hart id > > The first argument of Linux kernel is the risc-v core hart id, from which the kernel > is booted from. It is not the mach_id, which seems to be copied from arm. > > While we are here, this also changes the Linux kernel entry parameters' type to > support both 32-bit and 64-bit. > > Note the hart id is hardcoded to zero for now, and we should change to fill in it > with the value read from mhartid CSR of the hart which this routine is currently > running on. > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > > --- > > Changes in v2: > - Change Linux kernel entry parameters' type to support 32/64 bit > > arch/riscv/lib/bootm.c | 18 +++++------------- > 1 file changed, 5 insertions(+), 13 deletions(-) > > diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index > 6662aff..6893108 100644 > --- a/arch/riscv/lib/bootm.c > +++ b/arch/riscv/lib/bootm.c > @@ -25,10 +25,7 @@ int arch_fixup_fdt(void *blob) > > int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) > { > - bd_t *bd = gd->bd; > - char *s; > - int machid = bd->bi_arch_number; > - void (*theKernel)(int arch, uint params); > + void (*kernel)(ulong hart, void *dtb); > > /* > * allow the PREP bootm subcommand, it is required for bootm to work > @@ -39,18 +36,12 @@ int do_bootm_linux(int flag, int argc, char *argv[], > bootm_headers_t *images) > if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) > return 1; > > - theKernel = (void (*)(int, uint))images->ep; > - > - s = env_get("machid"); > - if (s) { > - machid = simple_strtoul(s, NULL, 16); > - printf("Using machid 0x%x from environment\n", machid); > - } > + kernel = (void (*)(ulong, void *))images->ep; > > bootstage_mark(BOOTSTAGE_ID_RUN_OS); > > debug("## Transferring control to Linux (at address %08lx) ...\n", > - (ulong)theKernel); > + (ulong)kernel); > > if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { #ifdef > CONFIG_OF_LIBFDT @@ -66,8 +57,9 @@ int do_bootm_linux(int flag, int argc, > char *argv[], bootm_headers_t *images) > printf("\nStarting kernel ...\n\n"); > > cleanup_before_linux(); > + /* TODO: hardcode the hart id to zero for now */ > if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) > - theKernel(machid, (unsigned long)images->ft_addr); > + kernel(0, images->ft_addr); > > /* does not return */ > Reviewed-by: Rick Chen <rick(a)andestech.com> > -- > 2.7.4

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Re: [U-Boot] [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling
by Rick Chen 20 Sep '18

20 Sep '18

> From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Tuesday, September 11, 2018 12:55 PM > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > Cc: Lukas Auer > Subject: [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name > spelling > > It's RISC-V that is the official name, not RISCV. > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > --- > > Changes in v2: None > > arch/Kconfig | 2 +- > arch/riscv/Kconfig | 6 +++--- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/Kconfig b/arch/Kconfig index bf1b4a9..42c23b5 100644 > --- a/arch/Kconfig > +++ b/arch/Kconfig > @@ -60,7 +60,7 @@ config PPC > select SYS_BOOT_GET_KBD > > config RISCV > - bool "riscv architecture" > + bool "RISC-V architecture" > select SUPPORT_OF_CONTROL > > config SANDBOX > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 20a43d8..49f87de > 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -1,4 +1,4 @@ > -menu "RISCV architecture" > +menu "RISC-V architecture" > depends on RISCV > > config SYS_ARCH > @@ -20,13 +20,13 @@ choice > default CPU_RISCV_32 > > config CPU_RISCV_32 > - bool "RISCV 32 bit" > + bool "RISC-V 32-bit" > select 32BIT > help > Choose this option to build an U-Boot for RISCV32 architecture. > > config CPU_RISCV_64 > - bool "RISCV 64 bit" > + bool "RISC-V 64-bit" > select 64BIT > help > Choose this option to build an U-Boot for RISCV64 architecture. > -- > 2.7.4 Reviewed-by: Rick Chen <rick(a)andestech.com>

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[U-Boot] Please pull u-boot-dm
by Simon Glass 20 Sep '18

20 Sep '18

Hi Tom, I was unable to get signed tags working, but here is a list of changes: - MPC83xx device tree additions (CPU and RAM) - Fix sandbox build error - Sync bitrev with Linux - Various ofnode/DT improvements The following changes since commit 40e44c8bf516e7071c9b80113473be5757e8c3f3: Merge branch 'master' of git://git.denx.de/u-boot-coldfire (2018-09-16 10:32:33 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to 75629a25087cd9897305375421abe2248bc40e72: dm: uclass: Adding missing child_pre_probe description (2018-09-18 13:27:10 -0600) ---------------------------------------------------------------- Andy Shevchenko (1): sandbox: Build with -fPIC Bin Meng (3): lib: bitrev: Sync with Linux kernel v4.17 sandbox: Enable bitrev library build dm: uclass: Adding missing child_pre_probe description Cédric Le Goater (1): dm: core: fix devfdt_remap_addr_index() Jens Wiklander (2): ofnode: add ofnode_by_prop_value() test: ofnode: test ofnode_by_prop_value() Mario Six (17): ram: Add driver for MPC83xx powerpc: Add read*_*/write*_* macros sysreset: Add get_status method test: Add tests for sysreset_get_status board_f: Add reset status printing mpc83xx: Add sysreset driver clk: Add MPC83xx clock driver timer: Sort Makefile entries timer: Add MPC83xx timer driver common: board_f: Sort includes init: Fix documentation board_f: Use static print_cpuinfo if CONFIG_CPU is active cpu: Fix cpu.h documentation cpu: Add cpu_probe_all method test: Add tests for CPU uclass cpu: Add MPC83xx CPU driver misc: Add MPC83xx serdes driver Masahiro Yamada (1): dm: fix alignment of help message of "dm" command Michael Heimpold (1): binman: fix a few typos in documentation Rajan Vaja (2): dm: core: Move "/clock" node scan into function dm: core: Scan "/firmware" node by default Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt | 23 + Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt | 34 + .../devicetree/bindings/misc/fsl,mpc83xx-serdes.txt | 24 + .../bindings/ram/fsl,mpc83xx-mem-controller.txt | 314 +++++++ .../devicetree/bindings/timer/fsl,mpc83xx-timer.txt | 21 + MAINTAINERS | 11 + arch/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu.c | 9 +- arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 + arch/powerpc/cpu/mpc83xx/serdes.c | 4 + arch/powerpc/cpu/mpc83xx/spd_sdram.c | 4 + arch/powerpc/cpu/mpc83xx/speed.c | 4 + arch/powerpc/include/asm/arch-mpc83xx/soc.h | 74 ++ arch/powerpc/include/asm/config.h | 2 +- arch/powerpc/include/asm/fsl_mpc83xx_serdes.h | 4 + arch/powerpc/include/asm/global_data.h | 4 + arch/powerpc/include/asm/io.h | 18 + arch/powerpc/include/asm/processor.h | 2 + arch/powerpc/lib/Makefile | 4 + arch/powerpc/lib/interrupts.c | 5 +- arch/sandbox/config.mk | 1 + arch/sandbox/dts/test.dts | 12 + common/board_f.c | 58 +- drivers/clk/Kconfig | 6 + drivers/clk/Makefile | 1 + drivers/clk/mpc83xx_clk.c | 410 +++++++++ drivers/clk/mpc83xx_clk.h | 379 ++++++++ drivers/core/fdtaddr.c | 2 +- drivers/core/of_access.c | 27 + drivers/core/ofnode.c | 14 + drivers/core/root.c | 35 +- drivers/cpu/Kconfig | 7 + drivers/cpu/Makefile | 2 + drivers/cpu/cpu-uclass.c | 23 + drivers/cpu/cpu_sandbox.c | 61 ++ drivers/cpu/mpc83xx_cpu.c | 349 ++++++++ drivers/cpu/mpc83xx_cpu.h | 126 +++ drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/mpc83xx_serdes.c | 185 ++++ drivers/misc/mpc83xx_serdes.h | 232 +++++ drivers/ram/Kconfig | 9 + drivers/ram/Makefile | 1 + drivers/ram/mpc83xx_sdram.c | 1096 +++++++++++++++++++++++ drivers/sysreset/Kconfig | 5 + drivers/sysreset/Makefile | 9 +- drivers/sysreset/sysreset-uclass.c | 10 + drivers/sysreset/sysreset_mpc83xx.c | 212 +++++ drivers/sysreset/sysreset_mpc83xx.h | 103 +++ drivers/sysreset/sysreset_sandbox.c | 16 + drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 17 +- drivers/timer/mpc83xx_timer.c | 249 +++++ include/cpu.h | 35 +- include/dm/of_access.h | 16 + include/dm/ofnode.h | 14 + include/dm/uclass.h | 1 + include/dt-bindings/clk/mpc83xx-clk.h | 33 + include/dt-bindings/memory/mpc83xx-sdram.h | 161 ++++ include/init.h | 34 +- include/linux/bitrev.h | 102 ++- include/mpc83xx.h | 6 + include/sysreset.h | 17 + lib/bitrev.c | 28 +- test/dm/Makefile | 1 + test/dm/cmd_dm.c | 2 +- test/dm/cpu.c | 45 + test/dm/ofnode.c | 27 + test/dm/sysreset.c | 20 + tools/binman/README | 8 +- 70 files changed, 4695 insertions(+), 91 deletions(-) create mode 100644 Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt create mode 100644 Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt create mode 100644 Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt create mode 100644 Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt create mode 100644 Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt create mode 100644 arch/powerpc/include/asm/arch-mpc83xx/soc.h create mode 100644 drivers/clk/mpc83xx_clk.c create mode 100644 drivers/clk/mpc83xx_clk.h create mode 100644 drivers/cpu/cpu_sandbox.c create mode 100644 drivers/cpu/mpc83xx_cpu.c create mode 100644 drivers/cpu/mpc83xx_cpu.h create mode 100644 drivers/misc/mpc83xx_serdes.c create mode 100644 drivers/misc/mpc83xx_serdes.h create mode 100644 drivers/ram/mpc83xx_sdram.c create mode 100644 drivers/sysreset/sysreset_mpc83xx.c create mode 100644 drivers/sysreset/sysreset_mpc83xx.h create mode 100644 drivers/timer/mpc83xx_timer.c create mode 100644 include/dt-bindings/clk/mpc83xx-clk.h create mode 100644 include/dt-bindings/memory/mpc83xx-sdram.h create mode 100644 test/dm/cpu.c Regards, Simon

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[U-Boot] [PATCH] nios2: 10m50: Add CPU pre-relocation in device tree
by Gan, Yau Wai 20 Sep '18

20 Sep '18

Tag CPU with dm-pre-reloc to enable driver before relocation. Signed-off-by: Gan, Yau Wai <yau.wai.gan(a)intel.com> Cc: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/dts/10m50_devboard.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/nios2/dts/10m50_devboard.dts b/arch/nios2/dts/10m50_devboard.dts index 05eac30..461ae68 100644 --- a/arch/nios2/dts/10m50_devboard.dts +++ b/arch/nios2/dts/10m50_devboard.dts @@ -19,6 +19,7 @@ #size-cells = <0>; cpu: cpu@0 { + u-boot,dm-pre-reloc; device_type = "cpu"; compatible = "altr,nios2-1.1"; reg = <0x00000000>; -- 2.7.4

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[U-Boot] [PATCH 1/2] imx: mx7: fix potential overflow in imx_ddr_size()
by Marcel Ziswiler 19 Sep '18

19 Sep '18

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> The imx_ddr_size() function may overflow as it is possible to kind of over provision the DDR controller. Fix this by capping it to 2 GB which is the maximum allowed size as per reference manual. Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> -- arch/arm/mach-imx/mx7/ddr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index f19aeb8042..9713835bf2 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -196,5 +196,9 @@ unsigned int imx_ddr_size(void) if (field_val <= 29) bits++; + /* cap to max 2 GB */ + if (bits > 31) + bits = 31; + return 1 << bits; } -- 2.14.4

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[U-Boot] [PATCH 1/3] net: designware: socfpga: Add Arria10 extras
by Marek Vasut 19 Sep '18

19 Sep '18

Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- NOTE: This driver is not enabled on Gen5 or Stratix10 as the implementation for its specifics is missing thus far. The driver can be safely enabled though, as the behavior of the plain designware mac driver will be retained. --- drivers/net/Kconfig | 8 +++ drivers/net/Makefile | 1 + drivers/net/dwmac_socfpga.c | 143 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 drivers/net/dwmac_socfpga.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f762b0898d..d86da7760e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -150,6 +150,14 @@ config ETH_DESIGNWARE 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to provide the PHY (physical media interface). +config ETH_DESIGNWARE_SOCFPGA + bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC" + depends on DM_ETH && ETH_DESIGNWARE + help + The Altera SoCFPGA requires additional configuration of the + Altera system manager to correctly interface with the PHY. + This code handles those SoC specifics. + config ETHOC bool "OpenCores 10/100 Mbps Ethernet MAC" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index c1ed44e21f..48a2878071 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o +obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DNET) += dnet.o obj-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c new file mode 100644 index 0000000000..08fc9677c4 --- /dev/null +++ b/drivers/net/dwmac_socfpga.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Marek Vasut <marex(a)denx.de> + * + * Altera SoCFPGA EMAC extras + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <clk.h> +#include <phy.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include "designware.h" + +#include <asm/arch/system_manager.h> + +enum dwmac_type { + DWMAC_SOCFPGA_GEN5 = 0, + DWMAC_SOCFPGA_ARRIA10, + DWMAC_SOCFPGA_STRATIX10, +}; + +struct dwmac_socfpga_platdata { + struct dw_eth_pdata dw_eth_pdata; + enum dwmac_type type; + void *phy_intf; +}; + +static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + struct regmap *regmap; + struct ofnode_phandle_args args; + void *range; + int ret; + + ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL, + 2, 0, &args); + if (ret) { + dev_err(dev, "Failed to get syscon: %d\n", ret); + return ret; + } + + if (args.args_count != 2) { + dev_err(dev, "Invalid number of syscon args\n"); + return -EINVAL; + } + + regmap = syscon_node_to_regmap(args.node); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(dev, "Failed to get regmap: %d\n", ret); + return ret; + } + + range = regmap_get_range(regmap, 0); + if (!range) { + dev_err(dev, "Failed to get regmap range\n"); + return -ENOMEM; + } + + pdata->phy_intf = range + args.args[0]; + + /* + * Sadly, the Altera DT bindings don't have SoC-specific compatibles, + * so we have to guesstimate which SoC we are running on from the + * DWMAC version. Luckily, Altera at least updated the DWMAC with + * each SoC. + */ + if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.70a")) + pdata->type = DWMAC_SOCFPGA_GEN5; + + if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.72a")) + pdata->type = DWMAC_SOCFPGA_ARRIA10; + + if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.74a")) + pdata->type = DWMAC_SOCFPGA_STRATIX10; + + return designware_eth_ofdata_to_platdata(dev); +} + +static int dwmac_socfpga_probe(struct udevice *dev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; + struct reset_ctl_bulk reset_bulk; + int ret; + u8 modereg; + + if (pdata->type == DWMAC_SOCFPGA_ARRIA10) { + switch (edata->phy_interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + break; + case PHY_INTERFACE_MODE_RMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + break; + default: + dev_err(dev, "Unsupported PHY mode\n"); + return -EINVAL; + } + + ret = reset_get_bulk(dev, &reset_bulk); + if (ret) { + dev_err(dev, "Failed to get reset: %d\n", ret); + return ret; + } + + reset_assert_bulk(&reset_bulk); + + clrsetbits_le32(pdata->phy_intf, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + modereg); + + reset_release_bulk(&reset_bulk); + } + + return designware_eth_probe(dev); +} + +static const struct udevice_id dwmac_socfpga_ids[] = { + { .compatible = "altr,socfpga-stmmac" }, + { } +}; + +U_BOOT_DRIVER(dwmac_socfpga) = { + .name = "dwmac_socfpga", + .id = UCLASS_ETH, + .of_match = dwmac_socfpga_ids, + .ofdata_to_platdata = dwmac_socfpga_ofdata_to_platdata, + .probe = dwmac_socfpga_probe, + .ops = &designware_eth_ops, + .priv_auto_alloc_size = sizeof(struct dw_eth_dev), + .platdata_auto_alloc_size = sizeof(struct dwmac_socfpga_platdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; -- 2.16.2

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[U-Boot] [PATCH v1 00/13] Introduce fastboot support for dragonboard410c
by Ramon Fried 19 Sep '18

19 Sep '18

This set of patches introduce fastboot support for Qualcomm db410c. As part of the patch, a small quirk is added to ci_udc through a weaklly linked function. Ramon Fried (13): ehci: Replace board_prepare_usb with board_usb_init ehci: msm: Add missing platdata dts: db410c: add alias for USB db410c: serial# env using msm board serial phy: db410c: Add MSM USB PHY driver dts: db410c: Add bindings for MSM USB phy configs: db410c: Enable USB PHY ehci: msm: switch to generic PHY uclass ehci: msm: use init_type in probe usb:ci_udc: Introduce init_after_reset phy function usb: ehci-msm: Add init_after_reset for CI_UDC DB410c: Enable fastboot support db410c: automatically launch fastboot MAINTAINERS | 1 + arch/arm/dts/dragonboard410c.dts | 11 ++ arch/arm/mach-snapdragon/Kconfig | 1 + .../dragonboard410c/dragonboard410c.c | 17 ++- configs/dragonboard410c_defconfig | 11 ++ drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile | 1 + drivers/phy/msm8916-usbh-phy.c | 109 ++++++++++++++++++ drivers/usb/gadget/ci_udc.c | 6 + drivers/usb/host/Kconfig | 3 +- drivers/usb/host/ehci-msm.c | 78 +++++-------- 11 files changed, 190 insertions(+), 56 deletions(-) create mode 100644 drivers/phy/msm8916-usbh-phy.c -- 2.18.0

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Re: [U-Boot] [PATCH v12 1/3] Consolidating UDP header functions.
by Duncan Hare 19 Sep '18

19 Sep '18

>On Sun, Jun 24, 2018 at 5:40 PM, <DH(a)synoia.com> wrote:. >From: Duncan Hare <DH(a)Synoia.com >> >> To make it possible to add TCP versions of the same, while reusing >> IP portions. This patch should not change any behavior. >> >> All references to TCP removed >> Used most recent version of u-boot June 22 13, 2918 >> Series to fix patman errors over Licensing declaration >> END >> >> Series-notes >See how it didn't work? It's still in this patch log instead of below >"---". Missing colon. Why so opposed to a dry run? You are having such >trouble using the patman tool properly, it seems so much time is spent >saying the same things over and over. > >I have tested this patch and it breaks UDP functionality. I have fixed >the regression. I have also fixed formatting issues that I've asked >you to fix and you have not. >With your permission I will pull in the fixed version of this patch. >Or if you prefer, I can send it to the list. >-Joe >> TCP with Selective Acknowledgment (SACK) is currently the protocol >> with highest speed transfers, for fast multi-hop networks. >> END >> >Joe With your permission I will pull in the fixed version of this patch.Or if you prefer, I can send it to the list. You have my permission. I have the disadvantage that in Patman I do not know what is correct behavior,so when I run a dry run, I do not know if what I'm seeing is right or wrong. Thanks Duncan Hare 714 931 7952

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[U-Boot] [PATCH] i2c: rcar_iic: Scale delays
by Marek Vasut 19 Sep '18

19 Sep '18

The delays in this driver used to depend on an incorrect timer frequency. This was corrected in 7984ac8d1635, which caused this driver to function incorrectly. Scale the delays accordingly to repair the malfunction. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/i2c/rcar_iic.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c index e91fc86c1a..86a74430ec 100644 --- a/drivers/i2c/rcar_iic.c +++ b/drivers/i2c/rcar_iic.c @@ -51,7 +51,7 @@ static void sh_irq_dte(struct udevice *dev) for (i = 0; i < IRQ_WAIT; i++) { if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) break; - udelay(10); + udelay(3); } } @@ -65,7 +65,7 @@ static int sh_irq_dte_with_tack(struct udevice *dev) break; if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR)) return -ETIMEDOUT; - udelay(10); + udelay(3); } return 0; } @@ -78,7 +78,7 @@ static void sh_irq_busy(struct udevice *dev) for (i = 0; i < IRQ_WAIT; i++) { if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR))) break; - udelay(10); + udelay(3); } } @@ -118,7 +118,7 @@ static int rcar_iic_read_common(struct udevice *dev, struct i2c_msg *msg) if (rcar_iic_set_addr(dev, msg->addr, 1) != 0) goto err; - udelay(10); + udelay(3); writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP, priv->base + RCAR_IIC_ICCR); @@ -151,7 +151,7 @@ static int rcar_iic_write_common(struct udevice *dev, struct i2c_msg *msg) if (rcar_iic_set_addr(dev, msg->addr, 0) != 0) goto err; - udelay(10); + udelay(3); for (i = 0; i < msg->len; i++) { writeb(msg->buf[i], priv->base + RCAR_IIC_ICDR); -- 2.18.0

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[U-Boot] [PATCH] ARM: rmobile: Repair TMU clock on Gen2
by Marek Vasut 19 Sep '18

19 Sep '18

The CPfi/4 is derived from XTAL clock and is not fixed. Undo the previous commit 7984ac8d1635aebd11175c96b07f937a39f0384d. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- include/configs/rcar-gen2-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index df13d864bd..a79e877fd3 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -60,6 +60,6 @@ #define CONFIG_TMU_TIMER #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (32500000 / 4) /* CP/4 */ +#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 8) #endif /* __RCAR_GEN2_COMMON_H */ -- 2.18.0

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