August 2018 - U-Boot

[U-Boot] [PATCH] gpio: xilinx: Add support for using label property
by Michal Simek 06 Aug '18

06 Aug '18

Add support for reading label property from DT and set up bank name based on that. If label property is not present full device node name is used. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/gpio/xilinx_gpio.c | 14 ++++++++++++-- drivers/gpio/zynq_gpio.c | 14 ++++++++++++-- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c index cccfa7561739..da50d1634570 100644 --- a/drivers/gpio/xilinx_gpio.c +++ b/drivers/gpio/xilinx_gpio.c @@ -224,8 +224,18 @@ static int xilinx_gpio_probe(struct udevice *dev) { struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - - uc_priv->bank_name = dev->name; + const void *label_ptr; + void *label_c; + int size; + + label_ptr = dev_read_prop(dev, "label", &size); + if (label_ptr) { + label_c = calloc(1, size); + memcpy(label_c, label_ptr, size); + uc_priv->bank_name = label_c; + } else { + uc_priv->bank_name = dev->name; + } uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1]; diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 6fbaafb3fa3c..aa8d51e2f709 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -336,8 +336,18 @@ static int zynq_gpio_probe(struct udevice *dev) { struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - - uc_priv->bank_name = dev->name; + const void *label_ptr; + void *label_c; + int size; + + label_ptr = dev_read_prop(dev, "label", &size); + if (label_ptr) { + label_c = calloc(1, size); + memcpy(label_c, label_ptr, size); + uc_priv->bank_name = label_c; + } else { + uc_priv->bank_name = dev->name; + } if (platdata->p_data) uc_priv->gpio_count = platdata->p_data->ngpio; -- 1.9.1

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[U-Boot] boot partition access at HS200 speed in eMMC
by Faiz Abbas 06 Aug '18

06 Aug '18

Hi Everyone, After the following patch from JJ, U-boot shifts to a lower speed mode from HS200 when accessing a boot partition. 01298da31d mmc: Change mode when switching to a boot partition I have looked through the JESD84-B51 spec for eMMC card and don't see it say anywhere that boot0 partition cannot be accessed in HS200 modes. In practice, I have seen timeouts sometimes when I try to write to the boot partition in HS200 mode on a dra7xx-evm in U-boot but not consistently (one would expect if such a thing was forbidden by the spec then it wouldn't work at all). Can anyone point to a documentation that says that boot partition cannot be accessed in HS200 mode? Has anyone else observed failures before this patch? I was able to access the boot0 partition in kernel in HS200 mode (log below). Unless there is code to fallback to a lower speed in kernel also (which doesn't seem to be the case from a simple searching of the code), this should prove that boot partitions can be accessed in HS200 speed mode. Here is the log: https://pastebin.ubuntu.com/p/W3SB4N3rfn/ Thanks, Faiz

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[U-Boot] Pull request: u-boot-spi/master
by Jagan Teki 05 Aug '18

05 Aug '18

Hi Tom, Please pull this PR. thanks, Jagan. The following changes since commit a839c3641e4de98981695056eeeb2ec17ba1a4ab: ARM: tegra: align carveout size (2018-08-01 20:06:10 -0400) are available in the Git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 7f25d8179776226a8ecfbaad3d3a88e9acd89f28: arm: sunxi: Allwinner A10 SPI driver (2018-08-03 11:14:08 +0530) ---------------------------------------------------------------- Chris Packham (1): spi: kirkwood: add orion-spi compatible string Clément Laigle (1): mtd: add spi flash id s25fl128l Jagan Teki (1): spi: kirkwood: Get drvdata in .ofdata_to_platdata Stefan Mavrodiev (1): arm: sunxi: Allwinner A10 SPI driver drivers/mtd/spi/spi_flash_ids.c | 1 + drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/kirkwood_spi.c | 16 +- drivers/spi/sun4i_spi.c | 456 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 476 insertions(+), 3 deletions(-) create mode 100644 drivers/spi/sun4i_spi.c

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[U-Boot] Pull request: u-boot-sunxi/master
by Jagan Teki 05 Aug '18

05 Aug '18

Hi Tom, Please pull this PR. thanks, Jagan. The following changes since commit 5a0007d481c0fcd2d422dd48b2a129dd8e8a272a: Prepare v2017.09-rc1 (2018-07-30 21:47:29 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to 89a897fc4d78e31332e5899e977d8bf3c82abafa: board: sun50i: h6: Add OrangePi One Plus initial support (2018-07-31 20:50:01 +0530) ---------------------------------------------------------------- Icenowy Zheng (14): sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS sunxi: add basic memory map definitions of H6 SoC sunxi: change RMR64's RVBAR address for H6 sunxi: change ATF position for H6 sunxi: add config for SPL at 0x20000 on H6 sunxi: change GIC address on H6 sunxi: add clock code for H6 sunxi: use sun6i-style watchdog for H6 sunxi: add UART0 setup for H6 sunxi: add MMC support for H6 sunxi: add DRAM support to H6 sunxi: add support for Allwinner H6 SoC sunxi: add support for Pine H64 board video: sunxi: de2: fix SimpleFB node creation when DE2 not probed Jagan Teki (5): phy: sun4i-usb: Call phy_passby even for PHY#0 phy: sun4i-usb: Remove usb_clk_cfg set in probe phy: sun4i-usb: Update PHY#3 rst_mask only for H3_H5 configs: sunxi: Drop CONFIG_SUNXI_USB_PHYS board: sun50i: h6: Add OrangePi One Plus initial support Mylène Josserand (2): mtd: nand: nand_base: Convert EINVAL into ENOTSUPP mtd: nand: sunxi: Return on set_feature only when not ENOTSUPP Simon Baatz (1): sunxi: enable SATA on Banana Pi M2 Berry arch/arm/dts/Makefile | 3 + arch/arm/dts/sun50i-h6-orangepi-one-plus.dts | 150 +++++ arch/arm/dts/sun50i-h6-pine-h64.dts | 185 ++++++ arch/arm/dts/sun50i-h6.dtsi | 288 +++++++++ arch/arm/include/asm/arch-sunxi/boot0.h | 4 + arch/arm/include/asm/arch-sunxi/clock.h | 2 + arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 320 +++++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 2 + arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 73 +++ arch/arm/include/asm/arch-sunxi/dram.h | 2 + arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h | 297 +++++++++ arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- arch/arm/include/asm/arch-sunxi/spl.h | 6 +- arch/arm/include/asm/arch-sunxi/timer.h | 2 +- arch/arm/mach-sunxi/Kconfig | 37 +- arch/arm/mach-sunxi/Makefile | 2 + arch/arm/mach-sunxi/board.c | 6 +- arch/arm/mach-sunxi/clock_sun50i_h6.c | 94 +++ arch/arm/mach-sunxi/cpu_info.c | 2 + arch/arm/mach-sunxi/dram_sun50i_h6.c | 755 ++++++++++++++++++++++ arch/arm/mach-sunxi/rmr_switch.S | 6 + board/sunxi/MAINTAINERS | 10 + board/sunxi/board.c | 7 + board/sunxi/mksunxi_fit_atf.sh | 10 +- common/spl/Kconfig | 2 +- configs/bananapi_m2_berry_defconfig | 3 + configs/orangepi_one_plus_defconfig | 14 + configs/pine_h64_defconfig | 15 + drivers/mmc/sunxi_mmc.c | 13 +- drivers/mtd/nand/nand_base.c | 4 +- drivers/mtd/nand/sunxi_nand.c | 2 +- drivers/phy/allwinner/phy-sun4i-usb.c | 10 +- drivers/video/sunxi/sunxi_de2.c | 3 + include/configs/sun4i.h | 2 - include/configs/sun50i.h | 7 +- include/configs/sun5i.h | 2 - include/configs/sun6i.h | 2 - include/configs/sun7i.h | 2 - include/configs/sun8i.h | 10 - include/configs/sunxi-common.h | 24 +- include/dt-bindings/clock/sun50i-h6-ccu.h | 125 ++++ include/dt-bindings/clock/sun50i-h6-r-ccu.h | 24 + include/dt-bindings/reset/sun50i-h6-ccu.h | 73 +++ include/dt-bindings/reset/sun50i-h6-r-ccu.h | 17 + scripts/config_whitelist.txt | 1 - 46 files changed, 2560 insertions(+), 61 deletions(-) create mode 100644 arch/arm/dts/sun50i-h6-orangepi-one-plus.dts create mode 100644 arch/arm/dts/sun50i-h6-pine-h64.dts create mode 100644 arch/arm/dts/sun50i-h6.dtsi create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h create mode 100644 arch/arm/mach-sunxi/clock_sun50i_h6.c create mode 100644 arch/arm/mach-sunxi/dram_sun50i_h6.c create mode 100644 configs/orangepi_one_plus_defconfig create mode 100644 configs/pine_h64_defconfig create mode 100644 include/dt-bindings/clock/sun50i-h6-ccu.h create mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h6-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h

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[U-Boot] [PATCH] m68k: ColdFire mcf5441x, add eSDHC support
by Angelo Dureghello 05 Aug '18

05 Aug '18

This patch adds mcf5441x eSDHC support for the mcf5441x family. Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- arch/m68k/cpu/mcf5445x/cpu_init.c | 10 ++++++++++ arch/m68k/cpu/mcf5445x/speed.c | 2 ++ arch/m68k/include/asm/global_data.h | 3 +++ 3 files changed, 15 insertions(+) diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 0b86020204..7632d9262c 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -173,6 +173,15 @@ void cpu_init_f(void) /* Lowest slew rate for UART0,1,2 */ out_8(&gpio->srcr_uart, 0x00); + +#ifdef CONFIG_FSL_ESDHC + /* eSDHC pin as faster speed */ + out_8(&gpio->srcr_sdhc, 0x03); + + /* All esdhc pins as SD */ + out_8(&gpio->par_sdhch, 0xff); + out_8(&gpio->par_sdhcl, 0xff); +#endif #endif /* CONFIG_MCF5441x */ #ifdef CONFIG_MCF5445x @@ -534,4 +543,5 @@ void cfspi_release_bus(uint bus, uint cs) clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); #endif } + #endif diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 5214730a0f..e15e32ebde 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -120,6 +120,8 @@ void setup_5441x_clocks(void) temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1; gd->bus_clk = vco / temp; /* bus clock */ + temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1; + gd->arch.sdhc_clk = vco / temp; } #endif diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index aa0be8191a..188055e9d3 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -18,6 +18,9 @@ struct arch_global_data { unsigned long vco_clk; unsigned long flb_clk; #endif +#ifdef CONFIG_MCF5441x + unsigned long sdhc_clk; +#endif }; #include <asm-generic/global_data.h> -- 2.18.0

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[U-Boot] [PATCH] m68k: fix multiple memory accesses on swap operations
by Angelo Dureghello 05 Aug '18

05 Aug '18

On a u32 val = __sw32(*addr); multiple memory accesses are not welcome, since "addr" may be an IO peripheral register address. This patch changes __sw16/32 to perform a single memory access for the source value. Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- arch/m68k/include/asm/byteorder.h | 34 ++++++++++++++++++------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h index eb03b6a053..9179622250 100644 --- a/arch/m68k/include/asm/byteorder.h +++ b/arch/m68k/include/asm/byteorder.h @@ -10,21 +10,28 @@ #include <asm/types.h> #ifdef __GNUC__ -#define __sw16(x) \ - ((__u16)( \ - (((__u16)(x) & (__u16)0x00ffU) << 8) | \ - (((__u16)(x) & (__u16)0xff00U) >> 8) )) -#define __sw32(x) \ - ((__u32)( \ - (((__u32)(x)) << 24) | \ - (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ - (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ - (((__u32)(x)) >> 24) )) + +static inline __u32 __sw32(__u32 x) +{ + __u32 v = x; + + return v << 24 | + (v & (__u32)0x0000ff00UL) << 8 | + (v & (__u32)0x00ff0000UL) >> 8 | + v >> 24; +} + +static inline __u16 __sw16(__u16 x) +{ + __u16 v = x; + + return (v & (__u16)0x00ffU) << 8 | + (v & (__u16)0xff00U) >> 8; +} static __inline__ unsigned ld_le16(const volatile unsigned short *addr) { - unsigned result = *addr; - return __sw16(result); + return __sw16(*addr); } static __inline__ void st_le16(volatile unsigned short *addr, @@ -35,8 +42,7 @@ static __inline__ void st_le16(volatile unsigned short *addr, static __inline__ unsigned ld_le32(const volatile unsigned *addr) { - unsigned result = *addr; - return __sw32(result); + return __sw32(*addr); } static __inline__ void st_le32(volatile unsigned *addr, const unsigned val) -- 2.18.0

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[U-Boot] 2018.09-rc1 breakage on orangepi pc2
by Mark Kettenis 05 Aug '18

05 Aug '18

I can no longer boot OpenBSD on the orangepi pc2. The kernel faults somewhere in the EFI detection code, almost certainly where it looks through the configuration table entries looking for the ACPI table. I've bisected this resulting in: 4182a129ef735bfd6c54788affe1b649ab85b851 is the first bad commit commit 4182a129ef735bfd6c54788affe1b649ab85b851 Author: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Date: Thu Jun 28 12:45:32 2018 +0200 efi_loader: allocate configuration table array The system table contains a link to the list of configurations tables. These include the device tree, SMBIOS table, and the ACPI table. This array is currently statically linked. With the patch it is allocated as EFI_RUNTIME_SERVICES_DATA. Due to the structure of the system table we cannot work with a linked list here. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> Signed-off-by: Alexander Graf <agraf(a)suse.de>

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[U-Boot] [PATCH v2] gpio: xilinx: Not read output values via regs
by Michal Simek 05 Aug '18

05 Aug '18

Reading registers for finding out output value is not working because input value is read instead in case of tristate. Reported-by: Stefan Herbrechtsmeier <stefan(a)herbrechtsmeier.net> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Rebased on the top of reviewed patches - Change logic in xilinx_gpio_get_value() drivers/gpio/xilinx_gpio.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c index da50d1634570..4b4bf651642c 100644 --- a/drivers/gpio/xilinx_gpio.c +++ b/drivers/gpio/xilinx_gpio.c @@ -25,6 +25,11 @@ struct xilinx_gpio_platdata { int bank_max[XILINX_GPIO_MAX_BANK]; int bank_input[XILINX_GPIO_MAX_BANK]; int bank_output[XILINX_GPIO_MAX_BANK]; + u32 dout_default[XILINX_GPIO_MAX_BANK]; +}; + +struct xilinx_gpio_privdata { + u32 output_val[XILINX_GPIO_MAX_BANK]; }; static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num, @@ -54,6 +59,7 @@ static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset, int value) { struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev); + struct xilinx_gpio_privdata *priv = dev_get_priv(dev); int val, ret; u32 bank, pin; @@ -61,10 +67,10 @@ static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset, if (ret) return ret; - val = readl(&platdata->regs->gpiodata + bank * 2); + val = priv->output_val[bank]; - debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x\n", - __func__, (ulong)platdata->regs, value, offset, bank, pin); + debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n", + __func__, (ulong)platdata->regs, value, offset, bank, pin, val); if (value) val = val | (1 << pin); @@ -73,12 +79,15 @@ static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset, writel(val, &platdata->regs->gpiodata + bank * 2); + priv->output_val[bank] = val; + return val; }; static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset) { struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev); + struct xilinx_gpio_privdata *priv = dev_get_priv(dev); int val, ret; u32 bank, pin; @@ -89,7 +98,14 @@ static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset) debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__, (ulong)platdata->regs, offset, bank, pin); - val = readl(&platdata->regs->gpiodata + bank * 2); + if (platdata->bank_output[bank]) { + debug("%s: Read saved output value\n", __func__); + val = priv->output_val[bank]; + } else { + debug("%s: Read input value from reg\n", __func__); + val = readl(&platdata->regs->gpiodata + bank * 2); + } + val = !!(val & (1 << pin)); return val; @@ -223,6 +239,7 @@ static const struct dm_gpio_ops xilinx_gpio_ops = { static int xilinx_gpio_probe(struct udevice *dev) { struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev); + struct xilinx_gpio_privdata *priv = dev_get_priv(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); const void *label_ptr; void *label_c; @@ -239,6 +256,11 @@ static int xilinx_gpio_probe(struct udevice *dev) uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1]; + priv->output_val[0] = platdata->dout_default[0]; + + if (platdata->bank_max[1]) + priv->output_val[1] = platdata->dout_default[1]; + return 0; } @@ -255,6 +277,9 @@ static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev) "xlnx,all-inputs", 0); platdata->bank_output[0] = dev_read_u32_default(dev, "xlnx,all-outputs", 0); + platdata->dout_default[0] = dev_read_u32_default(dev, + "xlnx,dout-default", + 0); is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0); if (is_dual) { @@ -264,6 +289,8 @@ static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev) "xlnx,all-inputs-2", 0); platdata->bank_output[1] = dev_read_u32_default(dev, "xlnx,all-outputs-2", 0); + platdata->dout_default[1] = dev_read_u32_default(dev, + "xlnx,dout-default-2", 0); } return 0; @@ -282,4 +309,5 @@ U_BOOT_DRIVER(xilinx_gpio) = { .ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata, .probe = xilinx_gpio_probe, .platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata), + .priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata), }; -- 1.9.1

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[U-Boot] [PATCH] clk: clk_set_default: accept no-op skip fields
by Neil Armstrong 05 Aug '18

05 Aug '18

The Assigned Clock parents and rates misses the fact that a "0" entry can be passed to skip setting a parent or rate of an assigned clock as described in the Linux clock bindings at [1]. This patch simply skips the clock reparenting if the DT parsing returns -ENOENT and the clock rate setting if "0" is passed as clock rate. [1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bind… Fixes: f4fcba5c5baa "clk: implement clk_set_defaults()" Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- drivers/clk/clk-uclass.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 419d451..2b15978 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -154,6 +154,10 @@ static int clk_set_default_parents(struct udevice *dev) for (index = 0; index < num_parents; index++) { ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents", index, &parent_clk); + /* If -ENOENT, this is a no-op entry */ + if (ret == -ENOENT) + continue; + if (ret) { debug("%s: could not get parent clock %d for %s\n", __func__, index, dev_read_name(dev)); @@ -210,6 +214,10 @@ static int clk_set_default_rates(struct udevice *dev) goto fail; for (index = 0; index < num_rates; index++) { + /* If 0 is passed, this is a no-op */ + if (!rates[index]) + continue; + ret = clk_get_by_indexed_prop(dev, "assigned-clocks", index, &clk); if (ret) { -- 2.7.4

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[U-Boot] [PATCH] mailmap: Update mail address (lukma)
by Lukasz Majewski 05 Aug '18

05 Aug '18

Update my e-mail address from samsung.com to denx.de Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- .mailmap | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.mailmap b/.mailmap index bd7267241a8e..513b4334c6e2 100644 --- a/.mailmap +++ b/.mailmap @@ -33,4 +33,4 @@ TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Wolfgang Denk <wdenk> York Sun <yorksun(a)freescale.com> York Sun <york.sun(a)nxp.com> -Łukasz Majewski <l.majewski(a)samsung.com> +Lukasz Majewski <lukma(a)denx.de> -- 2.11.0

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