August 2018 - U-Boot

[U-Boot] [PATCH 0/8][RESEND] Device Tree support for PowerPC in u-boot
by Jagdish Gediya 28 Aug '18

28 Aug '18

In current implementation, PowerPC does not support device tree in u-boot. This patch enables device tree support for PowerPC platform . T2080AQDS board used as first platform. Dtb is embedded in the u-boot following below steps using binmam tool. 1. Remove bootpg and resetvec section if required 2. Append dtb using binman 3. Append bootpg and resetvec section back if removed in 1st step. To enable binman tool, 'binman' node has been added in the device tree. Resend with adding missed u-boot mailing list Jagdish Gediya (8): powerpc/dts: setup fdt blob at __init_end powerpc/dts: makefile changes to clean and build dts binman: Add a new "start-pos" property in section class binman: Add support for powerpc 'bootpg + resetvec' entry powerpc: mpc85xx: select BINMAN by default powerpc: dts: add u-boot.dtsi and mpc85xx-u-boot.dtsi powerpc: mpc85xx: Use binman to embed dtb inside u-boot powerpc: dts: Enable device tree support for T2080QDS Makefile | 30 ++++++++++++- arch/powerpc/Kconfig | 1 + arch/powerpc/cpu/mpc8xxx/fdt.c | 12 +++++ arch/powerpc/dts/Makefile | 14 ++++++ arch/powerpc/dts/e6500_power_isa.dtsi | 39 ++++++++++++++++ arch/powerpc/dts/mpc85xx-u-boot.dtsi | 16 +++++++ arch/powerpc/dts/t2080qds.dts | 17 +++++++ arch/powerpc/dts/t2080qds.dtsi | 64 +++++++++++++++++++++++++++ arch/powerpc/dts/u-boot.dtsi | 31 +++++++++++++ board/freescale/t208xqds/README | 17 +++++++ configs/T2080QDS_NAND_defconfig | 3 +- configs/T2080QDS_SDCARD_defconfig | 3 +- configs/T2080QDS_SPIFLASH_defconfig | 3 +- configs/T2080QDS_defconfig | 3 +- dts/Makefile | 2 +- tools/binman/bsection.py | 13 +++++- tools/binman/etype/mpc85xx_bootpg_resetvec.py | 15 +++++++ 17 files changed, 274 insertions(+), 9 deletions(-) create mode 100644 arch/powerpc/dts/Makefile create mode 100644 arch/powerpc/dts/e6500_power_isa.dtsi create mode 100644 arch/powerpc/dts/mpc85xx-u-boot.dtsi create mode 100644 arch/powerpc/dts/t2080qds.dts create mode 100644 arch/powerpc/dts/t2080qds.dtsi create mode 100644 arch/powerpc/dts/u-boot.dtsi create mode 100644 tools/binman/etype/mpc85xx_bootpg_resetvec.py -- 2.7.4

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[U-Boot] [PATCH v2] serial: omap: Introduce DM specific omap serial
by Lokesh Vutla 27 Aug '18

27 Aug '18

Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- Based on the conclusion on the thread[1], added a separate driver for omap uart. [1] https://patchwork.ozlabs.org/patch/944756/ Changes since v1: - Updated ifdefs in NS16550_init() to use OMAP_SERIAL. drivers/serial/Kconfig | 9 +++ drivers/serial/Makefile | 1 + drivers/serial/ns16550.c | 47 +------------ drivers/serial/serial_omap.c | 126 +++++++++++++++++++++++++++++++++++ 4 files changed, 139 insertions(+), 44 deletions(-) create mode 100644 drivers/serial/serial_omap.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 766e5ced03..0aa2338135 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -625,6 +625,15 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200). +config OMAP_SERIAL + bool "Support for OMAP specific UART" + depends on DM_SERIAL + default y if (ARCH_OMAP2PLUS || SOC_DA8XX) + select SYS_NS16550 + help + If you have an TI based SoC and want to use the on-chip serial + port, say Y to this option. If unsure say N. + config OWL_SERIAL bool "Actions Semi OWL UART" depends on DM_SERIAL && ARCH_OWL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 9fa81d855d..03dc29ee2e 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o +obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 9c80090aa7..f9041aa626 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -175,7 +175,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) ; serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); -#if defined(CONFIG_ARCH_OMAP2PLUS) +#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif @@ -183,7 +183,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(ns16550_getfcr(com_port), &com_port->fcr); if (baud_divisor != -1) NS16550_setbrg(com_port, baud_divisor); -#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) +#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \ + defined(CONFIG_OMAP_SERIAL) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif @@ -279,42 +280,6 @@ DEBUG_UART_FUNCS #endif -#ifdef CONFIG_DEBUG_UART_OMAP - -#include <debug_uart.h> - -static inline void _debug_uart_init(void) -{ - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; - int baud_divisor; - - baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, - CONFIG_BAUDRATE); - serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); - serial_dout(&com_port->mdr1, 0x7); - serial_dout(&com_port->mcr, UART_MCRVAL); - serial_dout(&com_port->fcr, UART_FCR_DEFVAL); - - serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); - serial_dout(&com_port->dll, baud_divisor & 0xff); - serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); - serial_dout(&com_port->lcr, UART_LCRVAL); - serial_dout(&com_port->mdr1, 0x0); -} - -static inline void _debug_uart_putc(int ch) -{ - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; - - while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) - ; - serial_dout(&com_port->thr, ch); -} - -DEBUG_UART_FUNCS - -#endif - #ifdef CONFIG_DM_SERIAL static int ns16550_serial_putc(struct udevice *dev, const char ch) { @@ -489,12 +454,6 @@ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, - { .compatible = "ti,omap2-uart", .data = PORT_NS16550 }, - { .compatible = "ti,omap3-uart", .data = PORT_NS16550 }, - { .compatible = "ti,omap4-uart", .data = PORT_NS16550 }, - { .compatible = "ti,am3352-uart", .data = PORT_NS16550 }, - { .compatible = "ti,am4372-uart", .data = PORT_NS16550 }, - { .compatible = "ti,dra742-uart", .data = PORT_NS16550 }, {} }; #endif /* OF_CONTROL && !OF_PLATDATA */ diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c new file mode 100644 index 0000000000..d8a047bb71 --- /dev/null +++ b/drivers/serial/serial_omap.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' OMAP serial driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla(a)ti.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dt-structs.h> +#include <ns16550.h> +#include <serial.h> +#include <clk.h> + +#ifndef CONFIG_SYS_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 0 +#endif + +#ifdef CONFIG_DEBUG_UART_OMAP + +#include <debug_uart.h> + +static inline void _debug_uart_init(void) +{ + struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; + int baud_divisor; + + baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); + serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); + serial_dout(&com_port->mdr1, 0x7); + serial_dout(&com_port->mcr, UART_MCRVAL); + serial_dout(&com_port->fcr, UART_FCR_DEFVAL); + + serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); + serial_dout(&com_port->dll, baud_divisor & 0xff); + serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); + serial_dout(&com_port->lcr, UART_LCRVAL); + serial_dout(&com_port->mdr1, 0x0); +} + +static inline void _debug_uart_putc(int ch) +{ + struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; + + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) + ; + serial_dout(&com_port->thr, ch); +} + +DEBUG_UART_FUNCS + +#endif + +#if CONFIG_IS_ENABLED(DM_SERIAL) + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int omap_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev->platdata; + fdt_addr_t addr; + struct clk clk; + int err; + + /* try Processor Local Bus device first */ + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); + + plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); + plat->reg_shift = 2; + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + plat->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("omap serial failed to get clock\n"); + return err; + } + + if (!plat->clock) + plat->clock = dev_read_u32_default(dev, "clock-frequency", + CONFIG_SYS_NS16550_CLK); + if (!plat->clock) { + debug("omap serial clock not defined\n"); + return -EINVAL; + } + + plat->fcr = UART_FCR_DEFVAL; + + return 0; +} + +static const struct udevice_id omap_serial_ids[] = { + { .compatible = "ti,omap2-uart", }, + { .compatible = "ti,omap3-uart", }, + { .compatible = "ti,omap4-uart", }, + { .compatible = "ti,am3352-uart", }, + { .compatible = "ti,am4372-uart", }, + { .compatible = "ti,dra742-uart", }, + {} +}; +#endif /* OF_CONTROL && !OF_PLATDATA */ + +#if CONFIG_IS_ENABLED(SERIAL_PRESENT) +U_BOOT_DRIVER(omap_serial) = { + .name = "omap_serial", + .id = UCLASS_SERIAL, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = omap_serial_ids, + .ofdata_to_platdata = omap_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), +#endif + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; +#endif +#endif /* DM_SERIAL */ -- 2.18.0

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[U-Boot] [PATCH 0/8] [1/3] Initial support Texas Instrument's AM654 Platform
by Lokesh Vutla 27 Aug '18

27 Aug '18

The AM654 SoC is a lead device of the K3 Multicore SoC architecture platform, targeted for broad market and industrial control with aim to meet the complex processing needs of modern embedded products. The device is partitioned into three functional domains, each containing specific processing cores and peripherals: Some highlights in each domain are: - MAIN Domain: -------------- * Quad ARMv8 A53 cores split over two clusters * GICv3 compliant GIC500 * Configurable L3 Cache and IO-coherent architecture * DDR Subsystem (DDRSS) with Error Correcting Code (ECC) * Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL * eQEP/eCAP, eHRPWM. * Multimedia capability with CAL, DSS7-UL, SGX544, McASP * Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI, GPIO - MCU Domain: ------------- * Dual lock-step capable R5F uC for safety-critical applications * Flash subsystem with OSPI and Hyperbus interfaces * High data throughput capable distributed DMA architecture under MCU NAVSS * Dual ADCSS, Dual CAN-FD. - WKUP Domain: -------------- * Centralized System Controller for Security, Power, and Resource management. For further deails see AM65x Technical Reference Manual (SPRUID7, April 2018): http://www.ti.com/lit/pdf/spruid7 This is a complex SoC and the support to add this SoC is very huge. So I tried to split into 3 separate series: [1/3] Adding base SoC support [2/3] Base drivers that allow minimal boot. [3/3] EVM support with dts and defconfig changes. This series adds base SoC support. The rest of the two series will be a follow up of this series. On AM65x family devices, ROM supports boot only via MCU(R5). This means that bootloader has to run on R5 core. In order to meet this constraint, keeping safety in picture and to have faster boot time, the software boot architecture is designed as: https://pastebin.ubuntu.com/p/NxSvDbMtSk/ Any feedback is highly appreciated. Andreas Dannenberg (1): arm: K3: am654: Unlock control module registers during init Lokesh Vutla (7): arm: K3: Add initial support for TI's K3 generation of SoCs arm: K3: Add support for AM654 SoC definition arm: K3: Update _start instruction arm: K3: am654: Add support for boot device detection armv8: K3: am654: Add custom MMU support armv8: K3: am654: Introduce FIT generator script armv8: K3: am654: Add support for generating build targets Kconfig | 2 +- MAINTAINERS | 1 + arch/arm/Kconfig | 8 ++ arch/arm/Makefile | 1 + arch/arm/include/asm/spl.h | 2 +- arch/arm/lib/vectors.S | 8 ++ arch/arm/mach-k3/Kconfig | 50 ++++++++ arch/arm/mach-k3/Makefile | 7 ++ arch/arm/mach-k3/am6_init.c | 123 +++++++++++++++++++ arch/arm/mach-k3/arm64-mmu.c | 45 +++++++ arch/arm/mach-k3/config.mk | 21 ++++ arch/arm/mach-k3/include/mach/am6_hardware.h | 44 +++++++ arch/arm/mach-k3/include/mach/am6_spl.h | 36 ++++++ arch/arm/mach-k3/include/mach/clock.h | 16 +++ arch/arm/mach-k3/include/mach/hardware.h | 12 ++ arch/arm/mach-k3/include/mach/spl.h | 12 ++ common/spl/Kconfig | 2 +- drivers/serial/ns16550.c | 5 +- scripts/Makefile.spl | 9 ++ tools/k3/k3_fit_atf.sh | 98 +++++++++++++++ 20 files changed, 497 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-k3/Kconfig create mode 100644 arch/arm/mach-k3/Makefile create mode 100644 arch/arm/mach-k3/am6_init.c create mode 100644 arch/arm/mach-k3/arm64-mmu.c create mode 100644 arch/arm/mach-k3/config.mk create mode 100644 arch/arm/mach-k3/include/mach/am6_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/am6_spl.h create mode 100644 arch/arm/mach-k3/include/mach/clock.h create mode 100644 arch/arm/mach-k3/include/mach/hardware.h create mode 100644 arch/arm/mach-k3/include/mach/spl.h create mode 100755 tools/k3/k3_fit_atf.sh -- 2.18.0

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[U-Boot] [PATCH] env: common: load read-only variables after reset
by Yaniv Levinsky 27 Aug '18

27 Aug '18

U-Boot fails to load read-only variables from storage after a reset. It happens because the environment hash table prevents creating read-only variables unless the H_FORCE flag is passed. In the following example, the variable "test" is set to read-only in the board header file (#define CONFIG_ENV_FLAGS_LIST_DEFAULT "test:sr"): U-Boot> printenv .flags .flags=test:sr U-Boot> setenv -f test 1 U-Boot> printenv test test=1 U-Boot> savee Saving Environment to SPI Flash ... OK U-Boot> reset ... Loading Environment from SPI Flash... ## Error: Can't create "test" himport_r: can't insert "test=1" into hash table ... U-Boot> printenv test ## Error: "test" not defined Pass the H_FORCE flag when importing the environment from storage. Signed-off-by: Yaniv Levinsky <yaniv.levinsky(a)compulab.co.il> --- env/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/env/common.c b/env/common.c index 3317cef355..de8dd47e9b 100644 --- a/env/common.c +++ b/env/common.c @@ -119,7 +119,7 @@ int env_import(const char *buf, int check) } } - if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0, 0, + if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', H_FORCE, 0, 0, NULL)) { gd->flags |= GD_FLG_ENV_READY; return 0; -- 2.18.0

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[U-Boot] [PATCH] armv8:fsl-layerscape: Add support for Chassis 3.2
by Priyanka Jain 27 Aug '18

27 Aug '18

NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ .../cpu/armv8/fsl-layerscape/doc/README.lsch3_2 | 27 ++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 27 +++++++++++++++++++++- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 +++++++ 4 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index fd31ae1..81eec78 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -180,6 +180,9 @@ config FSL_LSCH2 config FSL_LSCH3 bool +config NXP_LSCH3_2 + bool + config FSL_MC_ENET bool "Management Complex network" depends on ARCH_LS2080A || ARCH_LS1088A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 new file mode 100644 index 0000000..3ecf645 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 @@ -0,0 +1,27 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +NXP LayerScape with Chassis Generation 3.2 + +This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2 +for example LX2160A. + +This architecture is enhancement over Chassis Generation 3 with +few differences mentioned below + +1)DDR Layout +============ +Entire DDR region splits into three regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff, + - Region 3 is at address 0x60_0000_0000 to the top of memory, + for example 140GB, 0x63_7fff_ffff. + +All DDR memory is marked as cache-enabled. + +2)IFC is removed + +3)Number of I2C controllers increased to 8 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 48d0ab1..5ee3a43 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * Copyright 2014-2015, Freescale Semiconductor */ @@ -36,15 +36,19 @@ static struct cpu_type cpu_type_list[] = { #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#endif #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#endif #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 @@ -64,8 +68,15 @@ static struct cpu_type cpu_type_list[] = { #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#ifdef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 +#else #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#endif #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 @@ -147,6 +158,13 @@ static struct mm_region early_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_SIZE, @@ -292,6 +310,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_SIZE, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index b0cec74..79bcb9f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -21,7 +21,9 @@ #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#endif #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 @@ -45,6 +47,12 @@ #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#ifdef CONFIG_NXP_LSCH3_2 +#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) +#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) +#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) +#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) +#endif #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) -- 2.7.4

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[U-Boot] [PATCH][v2] driver: net: fsl-mc: Memset MC reserve ram memory before usage
by Prabhakar Kushwaha 27 Aug '18

27 Aug '18

It is required to clean Management Complex reserve memory before any usage. So memset MC reserve memory. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: - updated patch subject - Consider case of dpl apply and mc_boot failure drivers/net/fsl-mc/mc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 940025a467..16ee0b34b9 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -2,6 +2,7 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. * Copyright 2017 NXP + * Copyright 2017-2018 NXP */ #include <common.h> #include <errno.h> @@ -29,6 +30,7 @@ #define MC_BOOT_ENV_VAR "mcinitcmd" DECLARE_GLOBAL_DATA_PTR; +static int mc_memset_resv_ram; static int mc_boot_status = -1; static int mc_dpl_applied = -1; #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET @@ -810,6 +812,11 @@ u64 mc_get_dram_addr(void) { size_t mc_ram_size = mc_get_dram_block_size(); + if (!mc_memset_resv_ram || get_mc_boot_status()) { + mc_memset_resv_ram = 1; + memset((void *)gd->arch.resv_ram, 0, mc_ram_size); + } + return (gd->arch.resv_ram + mc_ram_size - 1) & MC_RAM_BASE_ADDR_ALIGNMENT_MASK; } -- 2.14.1

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[U-Boot] mtd: spi: Full DM conversion timeline
by Ashish Kumar 27 Aug '18

27 Aug '18

Hello Jagan, > -----Original Message----- > From: Jagan Teki [mailto:jagannadh.teki@gmail.com] > Sent: Monday, May 14, 2018 3:18 PM > To: Ashish Kumar <ashish.kumar(a)nxp.com> > Cc: Jagan Teki <jagan(a)amarulasolutions.com>; York Sun > <york.sun(a)nxp.com>; Prabhakar Kushwaha > <prabhakar.kushwaha(a)nxp.com>; Yogesh Narayan Gaur > <yogeshnarayan.gaur(a)nxp.com>; Poonam Aggrwal > <poonam.aggrwal(a)nxp.com>; u-boot(a)lists.denx.de > Subject: Re: mtd: spi-nor: new NXP FlexSPI driver location & framework to > use ? > > On Mon, May 14, 2018 at 2:42 PM, Ashish Kumar <ashish.kumar(a)nxp.com> > wrote: > > > > > >> -----Original Message----- > >> From: Jagan Teki [mailto:jagannadh.teki@gmail.com] > >> Sent: Friday, May 11, 2018 11:31 AM > >> To: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> > >> Cc: Jagan Teki <jagan(a)amarulasolutions.com>; York Sun > >> <york.sun(a)nxp.com>; Yogesh Narayan Gaur > <yogeshnarayan.gaur(a)nxp.com>; > >> Poonam Aggrwal <poonam.aggrwal(a)nxp.com>; Ashish Kumar > >> <ashish.kumar(a)nxp.com>; u- boot(a)lists.denx.de > >> Subject: Re: mtd: spi-nor: new NXP FlexSPI driver location & framework to > use ? > >> > >> On Fri, May 11, 2018 at 11:08 AM, Prabhakar Kushwaha > >> <prabhakar.kushwaha(a)nxp.com> wrote: > >> > Dear Jagan, > >> > > >> > NXP is coming up with new FlexSPI controller. It is similar to > >> > existing QSPI with > >> enhanced feature-set. > >> > We have the driver ready as per existing framework i.e. driver/spi. > >> > > >> > From recend discussion, we go to know about framework change. > >> > Migration of qspi drivers in u-boot-spi/drivers/mtd/spi-nor/ > >> git://git.denx.de/u-boot-spi.git branch mtd-spinor-working. > >> > > >> > We are in dilemma for sending FlexSPI driver upstream. > >> > Do we follow existing framework i.e. driver/spi or new proposed > framework > >> i.e. u-boot-spi/drivers/mtd/spi-nor/ > >> > > >> > Also, do we have any timeline of u-boot-spi/drivers/mtd/spi-nor/ to > >> > become > >> default. > >> > >> Idea is to move spi-nor, mtd-spinor-working is paused because of > >> non-dm drivers accessing. We are clear that we can't create another > >> legacy layer to access spi-nor for the sake of non-dm driver to work > >> which eventually ended-up another mess and also no one take care of > >> non-dm conversion to dm if we give such feasibility. So we exported a > >> deadline for full SPI/SPI_FLASH DM conversion till v2018.09. Once all these > relevant conversion done, will try to move. > >> > > Hello Jagan, > > > > You have mentioned here > > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fgit. > > denx.de%2F%3Fp%3Du-boot- > spi.git%3Ba%3Dcommitdiff%3Bh%3Dc4e68d3aa8178f6 > > > aa63a79c4f8f459c0e3ed58e8&data=02%7C01%7Cashish.kumar%40nxp.com% > 7Ca4d3 > > > 2392ca7d4a0a5ead08d5b97fbeb3%7C686ea1d3bc2b4c6fa92cd99c5c301635% > 7C0%7C > > > 0%7C636618880665899108&sdata=yAOW42d%2F%2B6W47PCURhbnzyD3sfS > VloRtafRz% > > 2FBJmrRM%3D&reserved=0 > > > > Snip from above link: > > +Partially converted: > > + drivers/spi/atcspi200_spi.c > > + drivers/spi/davinci_spi.c > > + drivers/spi/fsl_dspi.c > > + drivers/spi/fsl_qspi.c > > > > That fsl_qspi.c is partial converted to DM model, is there any guide line to > follow for missing stuff ? > > We should fully convert the driver into dm, no #ifdef CONFIG_DM_SPI Could you please let me know if timeline for migration to full-DM mode has moved forward ? My patch(drivers/spi/fsl_qspi.c) is dependent upon below mentioned patch-sets acceptance. http://patchwork.ozlabs.org/patch/935860/ http://patchwork.ozlabs.org/patch/935858/ Regards Ashish

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[U-Boot] [PATCH] cmd: ubi: change 'default y' for SUNXI to 'imply' in Kconfig
by Masahiro Yamada 26 Aug '18

26 Aug '18

It is not preferred to put SUNXI-specific code in the common place. Change it to 'imply' property of ARCH_SUNXI. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/Kconfig | 1 + cmd/Kconfig | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7d394f2..a6ce155 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -796,6 +796,7 @@ config ARCH_SUNXI select USB_KEYBOARD if DISTRO_DEFAULTS select USE_TINY_PRINTF imply CMD_GPT + imply CMD_UBI if NAND imply DISTRO_DEFAULTS imply FAT_WRITE imply OF_LIBFDT_OVERLAY diff --git a/cmd/Kconfig b/cmd/Kconfig index aec2090..159ebaa 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1792,7 +1792,6 @@ config CMD_UBI select CRC32 select MTD_UBI select CMD_MTDPARTS - default y if NAND_SUNXI help UBI is a software layer above MTD layer which admits use of LVM-like logical volumes on top of MTD devices, hides some complexities of -- 2.7.4

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[U-Boot] [PATCH] configs: am57xx: change default board name to beagle_x15
by Praneeth Bajjuri 26 Aug '18

26 Aug '18

beagleboard x15 is the first supported platform variant of am57xx in AOSP (android open source project) now. changing board name to stay in consistent with aosp target name. Signed-off-by: Praneeth Bajjuri <praneeth(a)ti.com> --- configs/am57xx_evm_defconfig | 2 +- configs/am57xx_hs_evm_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 1572dc80db03..07ab01e921bf 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -14,7 +14,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard" +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_MISC_INIT_R is not set diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 895719286dc5..0522c10b01c4 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -20,7 +20,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard" +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_MISC_INIT_R is not set -- 2.7.4

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[U-Boot] [PATCH 0/2] efi_loader: pass system table in loaded image protocol
by Heinrich Schuchardt 26 Aug '18

26 Aug '18

The system table must be passed as a pointer in the loaded image protocol. A unit test is supplied. Heinrich Schuchardt (2): efi_loader: pass system table in loaded image protocol efi_selftest: test for loaded image protocol lib/efi_loader/efi_boottime.c | 1 + lib/efi_selftest/Makefile | 1 + lib/efi_selftest/efi_selftest_loaded_image.c | 109 +++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 lib/efi_selftest/efi_selftest_loaded_image.c -- 2.18.0

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