July 2018 - U-Boot

[U-Boot] [PATCH] common: build ymodem only on need
by Jun Nie 10 Nov '18

10 Nov '18

Build ymodem only on need to shrink spl image size. Signed-off-by: Jun Nie <jun.nie(a)linaro.org> --- common/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/Makefile b/common/Makefile index c7bde23..0614348 100644 --- a/common/Makefile +++ b/common/Makefile @@ -133,4 +133,5 @@ obj-y += command.o obj-$(CONFIG_$(SPL_)LOG) += log.o obj-$(CONFIG_$(SPL_)LOG_CONSOLE) += log_console.o obj-y += s_record.o -obj-y += xyzModem.o +obj-$(CONFIG_CMD_LOADB) += xyzModem.o +obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o -- 1.9.1

2 1

[U-Boot] [PATCH] spi: Zap mpc8xx_spi driver
by Jagan Teki 06 Nov '18

06 Nov '18

- Driver not used by any boards - No update on 'dm conversion' Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/Kconfig | 6 - drivers/spi/Makefile | 1 - drivers/spi/mpc8xx_spi.c | 336 ----------------------------------------------- 3 files changed, 343 deletions(-) delete mode 100644 drivers/spi/mpc8xx_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 235a8c7d73..fd3f115ccf 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -274,12 +274,6 @@ config LPC32XX_SSP help Enable support for SPI on LPC32xx -config MPC8XX_SPI - bool "MPC8XX SPI Driver" - depends on 8xx - help - Enable support for SPI on MPC8XX - config MPC8XXX_SPI bool "MPC8XXX SPI Driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b6000fd9a..f104836630 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o -obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c deleted file mode 100644 index b5bd558526..0000000000 --- a/drivers/spi/mpc8xx_spi.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * <nboppuri(a)trinetcommunication.com>, - * <pmpatel(a)trinetcommunication.com> - * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen(a)icn.siemens.de> - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de>. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd(a)denx.de - * - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <linux/ctype.h> -#include <malloc.h> -#include <post.h> -#include <serial.h> - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0xb00 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 -#endif - -#define CPM_SPI_BASE_RX CPM_SPI_BASE -#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t)) - -/* ------------------- - * Function prototypes - * ------------------- */ -ssize_t spi_xfer(size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f(void) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port B SPI pins -> page 34-8 MPC860UM - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) - * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) - * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) - * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) - * -------------------------------------------- */ - clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO - * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI - * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK - * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM - * ---------------------------------------------- */ - setbits_be32(&cp->cp_pbdir, 0x0000000F); - - /* ---------------------------------------------- - * open drain or active output - * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO - * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI - * PBODR[30] = 0 [0x00000002] -> active output: SPICLK - * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM - * ---------------------------------------------- */ - - clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008); - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - out_be32(&spi->spi_rstate, 0); - out_be32(&spi->spi_rdp, 0); - out_be16(&spi->spi_rbptr, 0); - out_be16(&spi->spi_rbc, 0); - out_be32(&spi->spi_rxtmp, 0); - out_be32(&spi->spi_tstate, 0); - out_be32(&spi->spi_tdp, 0); - out_be16(&spi->spi_tbptr, 0); - out_be16(&spi->spi_tbc, 0); - out_be32(&spi->spi_txtmp, 0); - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX); - out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX); - out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX); - -/* 4 */ - /* Init SPI Tx + Rx Parameters */ - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) - ; - - out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | - CPM_CR_FLG); - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) - ; - -/* 5 */ - /* Set SDMA configuration register */ - out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); - -/* 6 */ - /* Set to big endian. */ - out_8(&spi->spi_tfcr, SMC_EB); - out_8(&spi->spi_rfcr, SMC_EB); - -/* 7 */ - /* Set maximum receive size. */ - out_be16(&spi->spi_mrblr, MAX_BUFFER); - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - clrbits_be16(&tbdf->cbd_sc, BD_SC_READY); - clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY); - - /* Set the bd's rx and tx buffer address pointers */ - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - -/* 10 + 11 */ - out_8(&cp->cp_spim, 0); /* Mask all SPI events */ - out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r(void) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *)malloc(MAX_BUFFER); - txbuf = (uchar *)malloc(MAX_BUFFER); - - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) - break; - udelay(1000); - } - if (i >= 1000) - printf("*** spi_write: Time out while writing!\n"); - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer(size_t count) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - int tm; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Set CS for device */ - clrbits_be32(&cp->cp_pbdat, 0x0001); - - /* Setting tx bd status and data length */ - out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); - out_be16(&tbdf->cbd_datlen, count); - - /* Setting rx bd status and data length */ - out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); - out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */ - - clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR | - SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8)); - out_8(&cp->cp_spim, 0); /* Mask all SPI events */ - out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - - /* start spi transfer */ - setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm = 0; tm < 1000; ++tm) { - if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */ - break; - if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0) - break; - udelay(1000); - } - if (tm >= 1000) - printf("*** spi_xfer: Time out while xferring to/from SPI!\n"); - - /* Clear CS for device */ - setbits_be32(&cp->cp_pbdat, 0x0001); - - return count; -} -- 2.14.3

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[U-Boot] [PATCH] power: regulator: denied disable on always-on regulator
by Patrice Chotard 05 Nov '18

05 Nov '18

From: Patrick Delaunay <patrick.delaunay(a)st.com> Don't disable regulator which are tagged as "regulator-always-on" in DT. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- drivers/power/regulator/regulator-uclass.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4da8e43259fc..4511625ff251 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -106,10 +106,15 @@ int regulator_get_enable(struct udevice *dev) int regulator_set_enable(struct udevice *dev, bool enable) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; if (!ops || !ops->set_enable) return -ENOSYS; + uc_pdata = dev_get_uclass_platdata(dev); + if (!enable && uc_pdata->always_on) + return -EACCES; + return ops->set_enable(dev, enable); } -- 1.9.1

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[U-Boot] [PATCH v1 1/1] spi: lpc32xx_ssp: DM conversion
by Akash Gajjar 05 Nov '18

05 Nov '18

From: Akash Gajjar <gajjar04akash(a)gmail.com> This patch adds support for DM to the LPC32xx SSP SPI driver. Some TODOs are left over for later, These would be enhancements to the original functionality, and can come later. The legacy functionality is removed in this version. Signed-off-by: Akash Gajjar <akash(a)openedev.com> --- drivers/spi/Kconfig | 10 +- drivers/spi/lpc32xx_ssp.c | 145 +++++++++++++++-------------- include/dm/platform_data/spi_lpc32xx_ssp.h | 15 +++ 3 files changed, 93 insertions(+), 77 deletions(-) create mode 100644 include/dm/platform_data/spi_lpc32xx_ssp.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ec92b84..2297d4a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -99,6 +99,11 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config LPC32XX_SSP + bool "LPC32XX SPI Driver" + help + Enable support for SPI on LPC32xx + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" help @@ -277,11 +282,6 @@ config KIRKWOOD_SPI Enable support for SPI on various Marvell SoCs, such as Kirkwood and Armada 375. -config LPC32XX_SSP - bool "LPC32XX SPI Driver" - help - Enable support for SPI on LPC32xx - config MPC8XX_SPI bool "MPC8XX SPI Driver" depends on MPC8xx diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c index e2a593b..ae41b57 100644 --- a/drivers/spi/lpc32xx_ssp.c +++ b/drivers/spi/lpc32xx_ssp.c @@ -4,6 +4,9 @@ * (C) Copyright 2014 DENX Software Engineering GmbH * Written-by: Albert ARIBAUD <albert.aribaud(a)3adev.fr> * + * Support for device model: + * Copyright (C) 2018 Akash Gajjar <akash(a)openedev.com> + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,6 +16,8 @@ #include <malloc.h> #include <spi.h> #include <asm/arch/clk.h> +#include <dm.h> +#include <dm/platform_data/spi_lpc32xx_ssp.h> /* SSP chip registers */ struct ssp_regs { @@ -36,90 +41,36 @@ struct ssp_regs { /* SSP status RX FIFO not empty bit */ #define SSP_SR_RNE 0x0004 -/* lpc32xx spi slave */ -struct lpc32xx_spi_slave { - struct spi_slave slave; +struct lpc32xx_ssp_spi_priv { struct ssp_regs *regs; }; -static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave( - struct spi_slave *slave) +static int lpc32xx_ssp_spi_claim_bus(struct udevice *dev) { - return container_of(slave, struct lpc32xx_spi_slave, slave); -} - -/* spi_init is called during boot when CONFIG_CMD_SPI is defined */ -void spi_init(void) -{ - /* - * nothing to do: clocking was enabled in lpc32xx_ssp_enable() - * and configuration will be done in spi_setup_slave() - */ + return 0; } -/* the following is called in sequence by do_spi_xfer() */ - -struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +static int lpc32xx_ssp_spi_release_bus(struct udevice *dev) { - struct lpc32xx_spi_slave *lslave; - - /* we only set up SSP0 for now, so ignore bus */ - - if (mode & SPI_3WIRE) { - pr_err("3-wire mode not supported"); - return NULL; - } - - if (mode & SPI_SLAVE) { - pr_err("slave mode not supported\n"); - return NULL; - } - - if (mode & SPI_PREAMBLE) { - pr_err("preamble byte skipping not supported\n"); - return NULL; - } - - lslave = spi_alloc_slave(struct lpc32xx_spi_slave, bus, cs); - if (!lslave) { - printf("SPI_error: Fail to allocate lpc32xx_spi_slave\n"); - return NULL; - } - - lslave->regs = (struct ssp_regs *)SSP0_BASE; - - /* - * 8 bit frame, SPI fmt, 500kbps -> clock divider is 26. - * Set SCR to 0 and CPSDVSR to 26. - */ - - writel(0x7, &lslave->regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */ - writel(26, &lslave->regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */ - writel(0, &lslave->regs->imsc); /* do not raise any interrupts */ - writel(0, &lslave->regs->icr); /* clear any pending interrupt */ - writel(0, &lslave->regs->dmacr); /* do not do DMAs */ - writel(SSP_CR1_SSP_ENABLE, &lslave->regs->cr1); /* enable SSP0 */ - return &lslave->slave; + return 0; } -void spi_free_slave(struct spi_slave *slave) +static int lpc32xx_ssp_spi_set_speed(struct udevice *bus, uint hz) { - struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave); - - debug("(lpc32xx) spi_free_slave: 0x%08x\n", (u32)lslave); - free(lslave); + return 0; } -int spi_claim_bus(struct spi_slave *slave) +static int lpc32xx_ssp_spi_set_mode(struct udevice *bus, uint mode) { - /* only one bus and slave so far, always available */ return 0; } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int lpc32xx_ssp_spi_xfer(struct udevice *dev, uint bitlen, + const void *dout, void *din, ulong flags) { - struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave); + struct udevice *bus = dev->parent; + struct lpc32xx_ssp_priv *priv = dev_get_priv(bus); + struct ssp_regs *regs = priv->regs; int bytelen = bitlen >> 3; int idx_out = 0; int idx_in = 0; @@ -127,18 +78,68 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, start_time = get_timer(0); while ((idx_out < bytelen) || (idx_in < bytelen)) { - int status = readl(&lslave->regs->sr); + int status = readl(&regs->sr); if ((idx_out < bytelen) && (status & SSP_SR_TNF)) - writel(((u8 *)dout)[idx_out++], &lslave->regs->data); + writel(((u8 *)dout)[idx_out++], &regs->data); if ((idx_in < bytelen) && (status & status & SSP_SR_RNE)) - ((u8 *)din)[idx_in++] = readl(&lslave->regs->data); + ((u8 *)din)[idx_in++] = readl(&regs->data); if (get_timer(start_time) >= CONFIG_LPC32XX_SSP_TIMEOUT) return -1; } + + return 0; +} + +static int lpc32xx_ssp_spi_probe(struct udevice *bus) +{ + struct lpc32xx_ssp_spi_platdata *plat = bus->platdata; + struct lpc32xx_ssp_spi_priv = dev_get_priv(bus); + + priv->regs = plat->regs; + return 0; } -void spi_release_bus(struct spi_slave *slave) +static const struct dm_spi_ops lpc32xx_ssp_spi_ops = { + .claim_bus = lpc32xx_ssp_spi_claim_bus, + .release_bus = lpc32xx_ssp_spi_release_bus, + .xfer = lpc32xx_ssp_spi_xfer, + .set_speed = lpc32xx_ssp_spi_set_speed, + .set_mode = lpc32xx_ssp_spi_set_mode, +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int lpc32xx_ssp_spi_ofdata_to_platadata(struct udevice *bus) { - /* do nothing */ + struct lpc32xx_ssp_spi_platdata *plat = bus->platdata; + fdt_addr_t addr; + + addr = devfdt_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs = (struct struct ssp_regs *)addr; + + return 0; } + +/* TODO: update compatibel device tree */ +static const struct udevice_id lpc32xx_ssp_spi_ids[] = { + { .compatible = "" }, + {} +}; +#endif + +U_BOOT_DRIVER(lpc32xx_ssp_spi) = { + .name = "lpc32xx_ssp_spi", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = lpc32xx_ssp_spi_ids, + .ofdata_to_platdata = lpc32xx_ssp_spi_ofdata_to_platadata, + .platdata_auto_alloc_size = sizeof(struct lpc32xx_ssp_spi_platdata), +#endif + .ops = &lpc32xx_ssp_spi_ops, + .priv_auto_alloc_size = sizeof(struct lpc32xx_ssp_spi_priv), + .probe = lpc32xx_ssp_spi_probe, +}; +#endif diff --git a/include/dm/platform_data/spi_lpc32xx_ssp.h b/include/dm/platform_data/spi_lpc32xx_ssp.h new file mode 100644 index 0000000..ea5cccf --- /dev/null +++ b/include/dm/platform_data/spi_lpc32xx_ssp.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2018 Akash Gajjar <akash(a)openedev.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __lpc32xx_ssp_h +#define __lpc32xx_ssp_h + +struct lpc32xx_ssp_spi_platdata { + struct ssp_regs *regs; +}; + +#endif /* __lpc32xx_ssp_h */ + -- 2.7.4

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[U-Boot] [PATCH] sunxi: lower the DDR frequency of Orange Pi Prime
by Icenowy Zheng 29 Oct '18

29 Oct '18

When I use Orange Pi Prime to do some heavy compliation tasks, the gcc compiler sometimes mysteriously segfaults, and memtester catches memory error. As the lima-memtester cannot support H5 (Mali-450 GPU equipped), there's no really reliable way to detect DRAM stability except try and error. Lower the DDR frequency to 624MHz seems to solved the issue. Set the default frequency to 624MHz in the defconfig, as 672MHz is observed to be unstable at least on my board. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> --- configs/orangepi_prime_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 3d87374002..88eaf12741 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN50I_H5=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -- 2.13.6

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[U-Boot] [PATCH 0/6] driver: net: fsl-mc: Add support of multiple phys for dpmac
by Pankaj Bansal 22 Oct '18

22 Oct '18

This patch set adds support of multiple phys for one dpmac Till now we have had cases where we had one phy device per dpmac. Now, with the upcoming products (LX2160AQDS), we have cases, where there are sometimes two phy devices for one dpmac. One phy for TX lanes and one phy for RX lanes. To handle such cases, add the support for multiple phys in ethernet driver. The ethernet link is up if all the phy devices connected to one dpmac report link up. also the link capabilities are limited by the weakest phy device. i.e. say if there are two phys for one dpmac. one operates at 10G without autoneg and other operate at 1G with autoneg. Then the ethernet interface will operate at 1G without autoneg. Pankaj Bansal (6): driver: net: fsl-mc: modify the label name driver: net: fsl-mc: remove unused strcture elements driver: net: fsl-mc: fix error handing in init_phy driver: net: fsl-mc: Modify the dpmac link detection method driver: net: fsl-mc: initialize dpmac irrespective of phy driver: net: fsl-mc: Add support of multiple phys for dpmac board/freescale/ls1088a/eth_ls1088aqds.c | 18 +-- board/freescale/ls1088a/eth_ls1088ardb.c | 21 +-- board/freescale/ls2080aqds/eth.c | 26 +-- board/freescale/ls2080ardb/eth_ls2080rdb.c | 24 +-- drivers/net/fsl-mc/mc.c | 6 +- drivers/net/ldpaa_eth/ldpaa_eth.c | 180 +++++++++++++-------- drivers/net/ldpaa_eth/ldpaa_eth.h | 1 - drivers/net/ldpaa_eth/ldpaa_wriop.c | 49 ++++-- include/fsl-mc/ldpaa_wriop.h | 22 +-- 9 files changed, 209 insertions(+), 138 deletions(-) -- 2.17.1

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[U-Boot] [RFC PATCH 0/3] sunxi: extend SPL header to propagate DRAM size
by Andre Przywara 22 Oct '18

22 Oct '18

This series tries to solve three issues we currently have on Allwinner boards: - The DRAM sizing routine can only cope with power-of-two sized DRAM. - The DRAM sizing routine steps through all DRAM, possibly hitting secure memory. - The SPL header versioning is quite strict and tends to break every time we need to update it. So I thought about introducing something along the lines of semantic versioning[1], where we can add backwards-compatible changes to the SPL header without breaking every tool. This is introduced in the first patch. The second patch does some refactoring, so that the third patch can use the newly gained freedom to store the DRAM size. The SPL knows the DRAM size very well, so we store this in the SPL header, so that U-Boot proper can pick it up from there. This saves the call to get_ram_size() with its deficiencies. More information in the respective commit messages. I understand that this versioning solution is not fully future-proof, but we have only one byte for the version, and I just wanted to start discussion on this. There is a corresponding patch for sunxi-tools as well I am posting shortly. [1] https://semver.org Cheers, Andre. Andre Przywara (3): sunxi: Extend SPL header versioning sunxi: board.c: refactor SPL header checks sunxi: store DRAM size in SPL header arch/arm/include/asm/arch-sunxi/spl.h | 22 ++++++++---- board/sunxi/board.c | 66 ++++++++++++++++++++++++++++------- 2 files changed, 70 insertions(+), 18 deletions(-) -- 2.14.1

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[U-Boot] [PATCH 00/41] imx: add i.MX8QXP support
by Peng Fan 18 Oct '18

18 Oct '18

This patchset is to upstream i.MX8QXP and mek board support, with some drivers update to support i.MX8QXP. The information about the processor could be found https://www.nxp.com/products/processors-and-microcontrollers/applications-p… The architecture of i.MX8QXP is different from i.MX6/7/8M, inside i.MX8QXP, there is a dedicated processor(SCU) used for power/clock/pin/ pad/resource management/thermal and etc. The ACore need to communicate with SCU using SCFW API. The SCFW API is exported by SCFW, so we directly import it into U-Boot source code. Gao Pan (1): imx: lpi2c: fix clock issue when NACK detected Peng Fan (32): imx: import SCFW API imx: add Kconfig entry for i.MX8 arm: build mach-imx for i.MX8 imx8: add IPC communication support between ACore and SCU arm: global_data: introduce ipc_channel_handle imx: boot_mode: Add FLEXSPI boot entry imx8: add imx-regs header file imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined imx: add i.MX8 cpu type imx8: add basic cpu support imx8: add boot device detection imx8: implement mmc_get_env_dev imx8: implement imx_get_mac_from_fuse imx8: implement get_board_serial imx8: add mmu and dram related functiions imx8: add bootaux support imx8: add arch_cpu_init imx8: add clock driver imx8: add iomux configuration code serial_lpuart: Update lpuart driver to support i.MX8 net: fec: do not access reserved register for i.MX8 gpio: mxc_gpio: add support for i.MX8 pinctrl: Add pinctrl driver for i.MX8 power: Add power domain driver for i.MX8 power: Add PD device lookup interface to power domain uclass power-domain: add dummy functions when CONFIG_POWER_DOMAIN not defined dm: core: device: enable power domain in probe drivers: regulator: fixed: add off-on-delay-us log: include command header file i2c-mux: pca954x: support pca9646 i2c switch dts: imx8qxp: Add DTS and binding header files imx: 8qxp_mek: Add i.MX8QXP MEK board support Ye Li (8): fsl_esdhc: Update usdhc driver to support i.MX8 serial: lpuart: Enable RX and TX FIFO imx_lpi2c: Update lpi2c driver to support imx8 lpi2c: Fix bus stop problem in xfer lpi2c: Add bus busy error handling net: fec_mxc: Add the init_clk_fec function sata: Add i.MX8 SATA support mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue arch/arm/Kconfig | 8 + arch/arm/Makefile | 2 +- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8qxp-mek.dts | 416 +++++ arch/arm/dts/fsl-imx8qxp.dtsi | 1593 ++++++++++++++++++++ arch/arm/include/asm/arch-imx/cpu.h | 5 + arch/arm/include/asm/arch-imx8/clock.h | 36 + arch/arm/include/asm/arch-imx8/cpu.h | 26 + arch/arm/include/asm/arch-imx8/fsl_mu_hal.h | 54 + arch/arm/include/asm/arch-imx8/gpio.h | 22 + arch/arm/include/asm/arch-imx8/i2c.h | 34 + arch/arm/include/asm/arch-imx8/imx-regs.h | 119 ++ arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 + arch/arm/include/asm/arch-imx8/imx8qm_pads.h | 295 ++++ arch/arm/include/asm/arch-imx8/imx8qxp_pads.h | 200 +++ arch/arm/include/asm/arch-imx8/iomux.h | 40 + arch/arm/include/asm/arch-imx8/power-domain.h | 15 + arch/arm/include/asm/arch-imx8/sci/ipc.h | 67 + arch/arm/include/asm/arch-imx8/sci/rpc.h | 131 ++ arch/arm/include/asm/arch-imx8/sci/sci.h | 39 + arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h | 160 ++ arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 523 +++++++ arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 568 +++++++ arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 686 +++++++++ arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 759 ++++++++++ arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h | 306 ++++ arch/arm/include/asm/arch-imx8/sci/types.h | 862 +++++++++++ arch/arm/include/asm/arch-imx8/sys_proto.h | 19 + arch/arm/include/asm/global_data.h | 4 + arch/arm/include/asm/mach-imx/boot_mode.h | 1 + arch/arm/include/asm/mach-imx/sys_proto.h | 3 + arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8/Kconfig | 26 + arch/arm/mach-imx/imx8/Makefile | 13 + arch/arm/mach-imx/imx8/clock.c | 361 +++++ arch/arm/mach-imx/imx8/cpu.c | 783 ++++++++++ arch/arm/mach-imx/imx8/fsl_mu_hal.c | 28 + arch/arm/mach-imx/imx8/iomux.c | 47 + arch/arm/mach-imx/imx8/sci/ipc.c | 100 ++ arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h | 54 + arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c | 76 + arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h | 76 + arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c | 515 +++++++ arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h | 68 + arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c | 475 ++++++ arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h | 73 + arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c | 460 ++++++ arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h | 83 + arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c | 645 ++++++++ arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h | 67 + arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c | 365 +++++ board/freescale/imx8qxp_mek/Kconfig | 14 + board/freescale/imx8qxp_mek/MAINTAINERS | 6 + board/freescale/imx8qxp_mek/Makefile | 7 + board/freescale/imx8qxp_mek/imx8qxp_mek.c | 159 ++ configs/imx8qxp_mek_defconfig | 47 + drivers/ata/Kconfig | 6 + drivers/ata/Makefile | 1 + drivers/ata/ahci.c | 25 + drivers/ata/sata_imx.c | 64 + drivers/core/device.c | 7 + drivers/gpio/mxc_gpio.c | 30 +- drivers/i2c/imx_lpi2c.c | 82 +- drivers/i2c/muxes/pca954x.c | 9 +- drivers/mmc/fsl_esdhc.c | 32 +- drivers/net/fec_mxc.c | 9 +- drivers/pinctrl/nxp/Kconfig | 18 + drivers/pinctrl/nxp/Makefile | 2 + drivers/pinctrl/nxp/pinctrl-imx.c | 209 +-- drivers/pinctrl/nxp/pinctrl-imx.h | 16 + drivers/pinctrl/nxp/pinctrl-imx8.c | 42 + drivers/pinctrl/nxp/pinctrl-scu.c | 72 + drivers/power/domain/Kconfig | 6 + drivers/power/domain/Makefile | 1 + drivers/power/domain/imx8-power-domain.c | 315 ++++ drivers/power/domain/power-domain-uclass.c | 42 + drivers/power/regulator/fixed.c | 6 + drivers/serial/serial_lpuart.c | 48 +- include/configs/imx8qxp_mek.h | 157 ++ include/dt-bindings/clock/imx8qxp-clock.h | 533 +++++++ include/dt-bindings/pinctrl/pads-imx8qm.h | 975 ++++++++++++ include/dt-bindings/pinctrl/pads-imx8qxp.h | 770 ++++++++++ include/dt-bindings/soc/imx8_pd.h | 197 +++ include/dt-bindings/soc/imx_rsrc.h | 560 +++++++ include/fsl_lpuart.h | 2 +- .../asm/arch-mx7ulp => include}/imx_lpi2c.h | 0 include/log.h | 1 + include/power-domain.h | 52 + 88 files changed, 15691 insertions(+), 157 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi create mode 100644 arch/arm/include/asm/arch-imx8/clock.h create mode 100644 arch/arm/include/asm/arch-imx8/cpu.h create mode 100644 arch/arm/include/asm/arch-imx8/fsl_mu_hal.h create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h create mode 100644 arch/arm/include/asm/arch-imx8/i2c.h create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_pads.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_pads.h create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/ipc.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/rpc.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h create mode 100755 arch/arm/include/asm/arch-imx8/sci/types.h create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h create mode 100644 arch/arm/mach-imx/imx8/Kconfig create mode 100644 arch/arm/mach-imx/imx8/Makefile create mode 100644 arch/arm/mach-imx/imx8/clock.c create mode 100644 arch/arm/mach-imx/imx8/cpu.c create mode 100644 arch/arm/mach-imx/imx8/fsl_mu_hal.c create mode 100644 arch/arm/mach-imx/imx8/iomux.c create mode 100644 arch/arm/mach-imx/imx8/sci/ipc.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c create mode 100644 board/freescale/imx8qxp_mek/Kconfig create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS create mode 100644 board/freescale/imx8qxp_mek/Makefile create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c create mode 100644 configs/imx8qxp_mek_defconfig create mode 100644 drivers/ata/sata_imx.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c create mode 100644 drivers/power/domain/imx8-power-domain.c create mode 100644 include/configs/imx8qxp_mek.h create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h create mode 100644 include/dt-bindings/soc/imx8_pd.h create mode 100644 include/dt-bindings/soc/imx_rsrc.h rename {arch/arm/include/asm/arch-mx7ulp => include}/imx_lpi2c.h (100%) -- 2.14.1

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[U-Boot] [PATCH v5 00/13] efi: Enable basic sandbox support for EFI loader
by Simon Glass 15 Oct '18

15 Oct '18

A limitation of the EFI loader at present is that it does not build with sandbox. This makes it hard to write tests, since sandbox is used for most testing in U-Boot. This series enables the EFI loader feature. It allows sandbox to build and run a trivial function which calls the EFI API to output a message. This series is at u-boot-dm/efi-working Changes in v5: - Add new patch to disallow CMD_BOOTEFI_SELFTEST on sandbox - Drop call to efi_init_obj_list() which is now done in do_bootefi() - Drop period after "elf" in comment - Introduce load_options_path to specifyc U-Boot env var for load_options_path - Rebase to master Changes in v4: - Move the fix to query_console_serial() - Rebase to master - Update SPDX tags Changes in v3: - Add new patch to init the 'rows' and 'cols' variables - Add new patch to rename bootefi_test_finish() to bootefi_run_finish() - Add new patch to split out test init/uninit into functions - Add patch to create a function to set up for running EFI code - Drop incorrect map_sysmem() in write_smbios_table() - Init the 'rows' and 'cols' vars to avoid a compiler error (gcc 4.8.4) - Rebase to master Changes in v2: - Rebase to master - Update to use mapmem instead of a cast Simon Glass (13): efi: Don't allow CMD_BOOTEFI_SELFTEST on sandbox efi: Init the 'rows' and 'cols' variables efi: sandbox: Adjust memory usage for sandbox sandbox: smbios: Update to support sandbox efi: sandbox: Add distroboot support efi: sandbox: Add relocation constants efi: Add a comment about duplicated ELF constants efi: sandbox: Enable EFI loader builder for sandbox efi: Split out test init/uninit into functions efi: sandbox: Add a simple 'bootefi test' command efi: Create a function to set up for running EFI code efi: Rename bootefi_test_finish() to bootefi_run_finish() buildman: Add a --boards option to specify particular boards to build cmd/bootefi.c | 153 ++++++++++++++++++++++---------- include/config_distro_bootcmd.h | 2 +- include/efi_loader.h | 3 + lib/efi_loader/Kconfig | 12 ++- lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_console.c | 5 +- lib/efi_loader/efi_memory.c | 31 ++++--- lib/efi_loader/efi_runtime.c | 7 ++ lib/efi_loader/efi_test.c | 16 ++++ lib/efi_selftest/Kconfig | 2 +- lib/smbios.c | 32 +++++-- tools/buildman/README | 12 ++- tools/buildman/board.py | 28 +++++- tools/buildman/cmdline.py | 4 +- tools/buildman/control.py | 20 ++++- tools/buildman/test.py | 31 ++++--- 16 files changed, 264 insertions(+), 95 deletions(-) create mode 100644 lib/efi_loader/efi_test.c -- 2.18.0.rc1.244.gcf134e6275-goog

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[U-Boot] [BUG] snow: mmc: SD card access broken: unable to select a mode
by Guillaume Gardet 15 Oct '18

15 Oct '18

Hi Jaehoon, There are problems with SD card access on Samsung Chromebook (snow) with latest master (and also 2018.05-rc1 and 2018.03). eMMC is ok, but SD card access leads to 'unable to select a mode' problem. If I disable HS mode, I can access the SD card without problem: ******************************************************************************** diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 23f642980bf..28f4fa0f213 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -508,7 +508,8 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, cfg->host_caps |= MMC_MODE_4BIT; cfg->host_caps &= ~MMC_MODE_8BIT; } - cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; + /* Temp workaround for Chromebook snow to avoid the 'unable to select a mode' error */ +// cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; } ******************************************************************************** Once we try to select HS mode, all access to SD card result in failure, even when trying to setup a lower frequency mode, including SD legacy at 25 MHz. Any idea what is going? Maybe you have fixes pending? Guillaume

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