July 2018 - U-Boot

[U-Boot] [PATCH V2] drivers: regulator: fixed: add u-boot, off-on-delay-us
by Peng Fan 26 Jul '18

26 Jul '18

Add u-boot,off-on-delay-us for fixed regulator. Depends on board design, the gpio regulator sometimes connects with a big capacitance. When need to off, then on the regulator, if there is no enough delay, the voltage does not drop to 0, so introduce this property to handle such case. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Cc: Simon Glass <sjg(a)chromium.org> --- Simon, I droped your reviewed-by tag in V2, because I changed "off-on-delay-us" to "u-boot,off-on-delay-us" and add devicetree bindings. Thanks, Peng. .../devicetree/bindings/regulator/fixed-regulator.txt | 16 ++++++++++++++++ drivers/power/regulator/fixed.c | 6 ++++++ 2 files changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/fixed-regulator.txt diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt new file mode 100644 index 0000000000..2b241cf563 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt @@ -0,0 +1,16 @@ +Fixed Voltage regulators + +Check Linux Kernel +Documentation/devicetree/bindings/regulator/fixed-regulator.txt + +U-Boot Specific: +Optional properties: +- u-boot,off-on-delay-us: off delay time in microseconds + +Example: + + abc: fixedregulator@0 { + ... + u-boot,off-on-delay-us = <80000>; + ... + }; diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 0be5b7bd51..c5fe0ba43d 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -16,6 +16,7 @@ struct fixed_regulator_platdata { struct gpio_desc gpio; /* GPIO for regulator enable control */ unsigned int startup_delay_us; + unsigned int off_on_delay_us; }; static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) @@ -50,6 +51,8 @@ static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) /* Get optional ramp up delay */ dev_pdata->startup_delay_us = dev_read_u32_default(dev, "startup-delay-us", 0); + dev_pdata->off_on_delay_us = dev_read_u32_default(dev, + "u-boot,off-on-delay-us", 0); return 0; } @@ -123,6 +126,9 @@ static int fixed_regulator_set_enable(struct udevice *dev, bool enable) udelay(dev_pdata->startup_delay_us); debug("%s: done\n", __func__); + if (!enable && dev_pdata->off_on_delay_us) + udelay(dev_pdata->off_on_delay_us); + return 0; } -- 2.14.1

4 6

[U-Boot] [PATCH] Makefile: Fix 'clean' target
by Tom Rini 26 Jul '18

26 Jul '18

Now that we have removed the DocBook files we need to not try and clean that directory. Reported-by: ericywl <midnight2903(a)gmail.com> Fixes: 78a88f7930be ("doc: Replace DocBook with sphinx-based docs") Signed-off-by: Tom Rini <trini(a)konsulko.com> --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index d1246e063f85..79cbad22db82 100644 --- a/Makefile +++ b/Makefile @@ -1603,7 +1603,7 @@ clean: rm-files := $(CLEAN_FILES) clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f)) -clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook) +clean-dirs := $(addprefix _clean_, $(clean-dirs)) PHONY += $(clean-dirs) clean archclean $(clean-dirs): @@ -1685,7 +1685,7 @@ help: @echo ' coccicheck - Execute static code analysis with Coccinelle' @echo '' @echo 'Documentation targets:' - @$(MAKE) -f $(srctree)/doc/DocBook/Makefile dochelp + @$(MAKE) -f $(srctree)/Documentation/Makefile dochelp @echo '' @echo ' make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build' @echo ' make V=2 [targets] 2 => give reason for rebuild of target' -- 2.7.4

1 1

[U-Boot] [GIT PULL] u-boot-uniphier/master
by Masahiro Yamada 26 Jul '18

26 Jul '18

Hi Tom, Please pull UniPhier updates + Kconfig warning fix. Thanks. The following changes since commit 323a73adc9a1bf2de43fe03bdd9c3038ce7c2784: mtd: nand: add new enum for storing ECC algorithm (2018-07-23 14:33:21 -0400) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to 7ef5b1e7ed040683ff551f0234c471ce0d76828c: ARM: uniphier: enable distro boot (2018-07-25 08:47:53 +0900) ---------------------------------------------------------------- Luis Araneda (1): kconfig: Avoid format overflow warning from GCC 8.1 Masahiro Yamada (8): mtd: nand: denali: correct buffer alignment for DMA transfer fdt_support: make fdt_fixup_mtdparts() prototype more specific board: constify struct node_info array ARM: uniphier: clean-up ft_board_setup() ARM: uniphier: split ft_board_setup() out to a separate file ARM: uniphier: support fdt_fixup_mtdparts ARM: uniphier: enable MTD partition and UBI ARM: uniphier: enable distro boot arch/arm/Kconfig | 2 + arch/arm/mach-uniphier/Kconfig | 1 - arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/board_late_init.c | 8 +-- arch/arm/mach-uniphier/dram_init.c | 35 --------- arch/arm/mach-uniphier/fdt-fixup.c | 64 +++++++++++++++++ board/CarMediaLab/flea3/flea3.c | 2 +- board/compulab/cm_fx6/cm_fx6.c | 2 +- board/freescale/bsc9131rdb/bsc9131rdb.c | 2 +- board/freescale/bsc9132qds/bsc9132qds.c | 2 +- board/gateworks/gw_ventana/gw_ventana.c | 2 +- board/isee/igep003x/board.c | 2 +- board/isee/igep00x0/igep00x0.c | 2 +- board/toradex/colibri_imx7/colibri_imx7.c | 2 +- board/toradex/colibri_vf/colibri_vf.c | 2 +- common/fdt_support.c | 13 ++-- configs/uniphier_ld4_sld8_defconfig | 6 +- configs/uniphier_v7_defconfig | 6 +- configs/uniphier_v8_defconfig | 5 +- doc/README.uniphier | 55 ++++++++++++++ drivers/mtd/nand/denali.c | 2 +- include/configs/uniphier.h | 84 +++++++++++----------- include/fdt_support.h | 11 ++- scripts/kconfig/confdata.c | 2 +- 24 files changed, 206 insertions(+), 107 deletions(-) create mode 100644 arch/arm/mach-uniphier/fdt-fixup.c -- Best Regards Masahiro Yamada

2 1

[U-Boot] [PATCH v4 0/8] LS1046A SMMU enabling patches
by laurentiu.tudor＠nxp.com 26 Jul '18

26 Jul '18

From: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> This patch series adds the required devices setup and device tree fixups for SMMU enablement on LS1046A chips. The approach taken tries to mimic the implementation of PAMU LIODN setup on booke powerpc. First 4 patches contain some fixes and add some missing bits & pieces. Last 3 patches add the actual infrastructure for ICID setup, qman portal and fman ICID configuration. Changes in v4: - added missing SEC ICID config - updated macro params to match arguments - supplemental comments Changes in v3: - cleaner QMAN_BAR setup - moved SoC specific bits from generic ICID arch setup to board code Changes in v2: - drop CONFIG_SYS_ prefix from newly introduced defines in patch [1/7] Laurentiu Tudor (8): armv8: fsl-layerscape: add missing register blocks base address defines armv8: ls1046a: advertise QMan v3 in configuration misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms armv8: fsl-layerscape: add missing debug stream ID armv8: ls1046a: initial icid setup support armv8: ls1046a: add icid setup for qman portals armv8: ls1046a: setup fman ports ICIDs and device tree armv8: ls1046a: setup SEC ICIDs and fix up device tree arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/icid.c | 192 ++++++++++++++++++ .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 90 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 + .../include/asm/arch-fsl-layerscape/config.h | 1 + .../asm/arch-fsl-layerscape/fsl_icid.h | 114 +++++++++++ .../asm/arch-fsl-layerscape/fsl_portals.h | 24 +++ .../asm/arch-fsl-layerscape/immap_lsch2.h | 18 +- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 + board/freescale/ls1046aqds/ls1046aqds.c | 2 + board/freescale/ls1046ardb/ls1046ardb.c | 3 + drivers/crypto/fsl/jr.c | 2 +- drivers/misc/fsl_portals.c | 45 +++- scripts/config_whitelist.txt | 2 - 14 files changed, 480 insertions(+), 18 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h -- 2.17.1

4 11

[U-Boot] [PATCH v3] mtd: add spi flash id s25fl128l
by Clément Laigle 26 Jul '18

26 Jul '18

Add support for SPANSION s25fl128l Changes for v2: - Fix EXT_ID Changes for v3: - s25fl128l have only one version and no EXT_ID Signed-off-by: Clément Laigle <c.laigle(a)catie.fr> Cc: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/mtd/spi/spi_flash_ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 3cdee508c8..604b445e87 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -109,6 +109,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, {"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, {"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, RD_FULL | WR_QPP) } {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, -- 2.17.1

1 0

[U-Boot] [PATCH] Makefile: Fix make clean with DocBook
by Jagan Teki 26 Jul '18

26 Jul '18

doc/DocBook has removed in below commit "doc: Replace DocBook with sphinx-based docs" (sha1: 78a88f7930becb78afef09c1237a8e4edc1b01e1) and missed to remove it from clean-dirs, otherwise 'make clean' shows an error as below. $ make clean scripts/Makefile.clean:15: doc/DocBook/Makefile: No such file or directory make[1]: *** No rule to make target 'doc/DocBook/Makefile'. Stop. Makefile:1610: recipe for target '_clean_doc/DocBook' failed make: *** [_clean_doc/DocBook] Error 2 Cc: Mario Six <mario.six(a)gdsys.cc> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Makefile b/Makefile index d1246e063f..5224c34c96 100644 --- a/Makefile +++ b/Makefile @@ -1603,7 +1603,7 @@ clean: rm-files := $(CLEAN_FILES) clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f)) -clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook) +clean-dirs := $(addprefix _clean_, $(clean-dirs)) PHONY += $(clean-dirs) clean archclean $(clean-dirs): @@ -1685,7 +1685,6 @@ help: @echo ' coccicheck - Execute static code analysis with Coccinelle' @echo '' @echo 'Documentation targets:' - @$(MAKE) -f $(srctree)/doc/DocBook/Makefile dochelp @echo '' @echo ' make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build' @echo ' make V=2 [targets] 2 => give reason for rebuild of target' -- 2.17.1

1 0

[U-Boot] [PATCH v2] mtd: add spi flash id s25fl128l
by Clément Laigle 26 Jul '18

26 Jul '18

Add support for SPANSION s25fl128l 256k and 64k Changes for v2: - Fix EXT_ID Signed-off-by: Clément Laigle <c.laigle(a)catie.fr> --- drivers/mtd/spi/spi_flash_ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 9212373dae..bfc569fbf0 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -107,6 +107,8 @@ const struct spi_flash_info spi_flash_ids[] = { {"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, {"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, {"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"s25fl128l_256k", INFO(0x016018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, + {"s25fl128l_64k", INFO(0x016018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, -- 2.17.1

2 1

[U-Boot] [PATCH 1/1] arm: socfpga: Add support for the ReflexCES R329 board
by Xavier Ruppen 25 Jul '18

25 Jul '18

The ReflexCES PCIe carrier board Arria 10 SoC SoM (R329) provides access to all the features of the Arria 10 SoC SoM (R315) (Ethernet, OTG USB, Transceivers, UART) and adds further functions, including SFP+ connectors, PCIe x8 Gen3, USB3.0 and a wifi interface. No fpga portion is provided in fit_spl_fpga.its as MSEL is hardwired on this board. Thus, a bitstream is loaded before booting by using the EPCQ. It is possible to load a bitstream from the HPS (packaged in the .sfp file) but a small hardware mod on the MSEL lines is required (tested and works). Signed-off-by: Xavier Ruppen <xruppen(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> --- This patch was created and tested against u-boot-socfpga/arria10_sdmmc. The handoff.dtsi file was created by meld'ing the (old) .dts file provided by ReflexCES and socfpga_arria10_socdk_sdmmc_handoff.dtsi. The board was tested with what I believe is the factory bitstream written in the EPCQ. As I copied and pasted the majority of the files from the arria10-socdk, I purposely ignored a bunch of checkpatch warnings, i.e. lenghty lines and a missing SPDX-License-Identifier in the .dts(i) files. arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria10_r329.dts | 108 ++++++ .../arm/dts/socfpga_arria10_r329_handoff.dtsi | 350 ++++++++++++++++++ arch/arm/mach-socfpga/Kconfig | 7 + board/reflexces/r329-a10-pcie/Kconfig | 18 + board/reflexces/r329-a10-pcie/MAINTAINERS | 8 + board/reflexces/r329-a10-pcie/Makefile | 5 + .../reflexces/r329-a10-pcie/fit_spl_fpga.its | 45 +++ board/reflexces/r329-a10-pcie/socfpga.c | 6 + configs/socfpga_r329_a10_pcie_defconfig | 67 ++++ include/configs/socfpga_r329_a10_pcie.h | 50 +++ 11 files changed, 665 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_r329.dts create mode 100644 arch/arm/dts/socfpga_arria10_r329_handoff.dtsi create mode 100644 board/reflexces/r329-a10-pcie/Kconfig create mode 100644 board/reflexces/r329-a10-pcie/MAINTAINERS create mode 100644 board/reflexces/r329-a10-pcie/Makefile create mode 100644 board/reflexces/r329-a10-pcie/fit_spl_fpga.its create mode 100644 board/reflexces/r329-a10-pcie/socfpga.c create mode 100644 configs/socfpga_r329_a10_pcie_defconfig create mode 100644 include/configs/socfpga_r329_a10_pcie.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 946023093d..05cd7af467 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -188,6 +188,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_arria10_r329.dtb \ socfpga_cyclone5_is1.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_dbm_soc1.dtb \ diff --git a/arch/arm/dts/socfpga_arria10_r329.dts b/arch/arm/dts/socfpga_arria10_r329.dts new file mode 100644 index 0000000000..8869ef0fe7 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_r329.dts @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2015 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +#include "socfpga_arria10_r329_handoff.dtsi" + +/ { + model = "Reflex CES R329 SOM-A10 PCIe"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + ethernet0 = &gmac1; + serial0 = &uart0; + }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0xC0000000>; /* 3GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + + /* + * These skews assume the user's FPGA design is adding 600ps of delay + * for TX_CLK on Arria 10. + * + * All skews are offset since hardware skew values for the ksz9031 + * range from a negative skew to a positive skew. + * See the micrel-ksz90x1.txt Documentation file for details. + */ + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + max-frame-size = <3800>; + status = "okay"; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog1 { + status = "okay"; +}; + +&mmc { + u-boot,dm-pre-reloc; + status = "okay"; + num-slots = <1>; + cap-sd-highspeed; + bus-width = <4>; + non-removable; +}; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_r329_handoff.dtsi b/arch/arm/dts/socfpga_arria10_r329_handoff.dtsi new file mode 100644 index 0000000000..462cad912c --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_r329_handoff.dtsi @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright (C) 2016-2017 Intel Corporation + * + *<auto-generated> + * This code was generated by a tool based on + * handoffs from both Qsys and Quartus. + * + * Changes to this file may be lost if + * the code is regenerated. + *</auto-generated> + */ + +#include "socfpga_arria10.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */ + + chosen { + cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */ + }; + + /* Clock sources */ + clocks { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + + /* Clock source: altera_arria10_hps_eosc1 */ + altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "altera_arria10_hps_eosc1-clk"; + }; + + /* Clock source: altera_arria10_hps_cb_intosc_ls */ + altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk"; + }; + + /* Clock source: altera_arria10_hps_f2h_free */ + altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "altera_arria10_hps_f2h_free-clk"; + }; + }; + + /* + * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_clk_mgr: clock_manager@0xffd04000 { + u-boot,dm-pre-reloc; + compatible = "altr,socfpga-a10-clk-init"; + reg = <0xffd04000 0x00000200>; + reg-names = "soc_clock_manager_OCP_SLV"; + + /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */ + mainpll { + u-boot,dm-pre-reloc; + vco0-psrc = <0>; /* Field: vco0.psrc */ + vco1-denom = <1>; /* Field: vco1.denom */ + vco1-numer = <127>; /* Field: vco1.numer */ + mpuclk-cnt = <0>; /* Field: mpuclk.cnt */ + mpuclk-src = <0>; /* Field: mpuclk.src */ + nocclk-cnt = <0>; /* Field: nocclk.cnt */ + nocclk-src = <0>; /* Field: nocclk.src */ + cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */ + cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */ + cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */ + cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */ + cntr6clk-cnt = <7>; /* Field: cntr6clk.cnt */ + cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */ + cntr7clk-src = <0>; /* Field: cntr7clk.src */ + cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */ + cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */ + cntr9clk-src = <0>; /* Field: cntr9clk.src */ + cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */ + nocdiv-l4mainclk = <2>; /* Field: nocdiv.l4mainclk */ + nocdiv-l4mpclk = <2>; /* Field: nocdiv.l4mpclk */ + nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */ + nocdiv-csatclk = <2>; /* Field: nocdiv.csatclk */ + nocdiv-cstraceclk = <0>; /* Field: nocdiv.cstraceclk */ + nocdiv-cspdbgclk = <0>; /* Field: nocdiv.cspdbgclk */ + }; + + /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */ + perpll { + u-boot,dm-pre-reloc; + vco0-psrc = <0>; /* Field: vco0.psrc */ + vco1-denom = <1>; /* Field: vco1.denom */ + vco1-numer = <119>; /* Field: vco1.numer */ + cntr2clk-cnt = <5>; /* Field: cntr2clk.cnt */ + cntr2clk-src = <1>; /* Field: cntr2clk.src */ + cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */ + cntr3clk-src = <1>; /* Field: cntr3clk.src */ + cntr4clk-cnt = <14>; /* Field: cntr4clk.cnt */ + cntr4clk-src = <1>; /* Field: cntr4clk.src */ + cntr5clk-cnt = <374>; /* Field: cntr5clk.cnt */ + cntr5clk-src = <1>; /* Field: cntr5clk.src */ + cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */ + cntr6clk-src = <0>; /* Field: cntr6clk.src */ + cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */ + cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */ + cntr8clk-src = <0>; /* Field: cntr8clk.src */ + cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */ + emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */ + emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */ + emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */ + gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */ + }; + + /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */ + alteragrp { + u-boot,dm-pre-reloc; + nocclk = <0x03840003>; /* Register: nocclk */ + mpuclk = <0x03840001>; /* Register: mpuclk */ + }; + }; + + /* + * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver + * Version: 1.0 + * Binding: pinmux + */ + i_io48_pin_mux: pinmux@0xffd07000 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "pinctrl-single"; + reg = <0xffd07000 0x00000800>; + reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; + + /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */ + shared { + u-boot,dm-pre-reloc; + reg = <0xffd07000 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + <0x00000000 0x0000000d>, /* Register: pinmux_shared_io_q1_1 */ + <0x00000004 0x0000000d>, /* Register: pinmux_shared_io_q1_2 */ + <0x00000008 0x0000000d>, /* Register: pinmux_shared_io_q1_3 */ + <0x0000000c 0x0000000d>, /* Register: pinmux_shared_io_q1_4 */ + <0x00000010 0x00000000>, /* Register: pinmux_shared_io_q1_5 */ + <0x00000014 0x00000000>, /* Register: pinmux_shared_io_q1_6 */ + <0x00000018 0x00000001>, /* Register: pinmux_shared_io_q1_7 */ + <0x0000001c 0x00000001>, /* Register: pinmux_shared_io_q1_8 */ + <0x00000020 0x00000001>, /* Register: pinmux_shared_io_q1_9 */ + <0x00000024 0x00000001>, /* Register: pinmux_shared_io_q1_10 */ + <0x00000028 0x0000000a>, /* Register: pinmux_shared_io_q1_11 */ + <0x0000002c 0x0000000a>, /* Register: pinmux_shared_io_q1_12 */ + <0x00000030 0x00000008>, /* Register: pinmux_shared_io_q2_1 */ + <0x00000034 0x00000008>, /* Register: pinmux_shared_io_q2_2 */ + <0x00000038 0x00000008>, /* Register: pinmux_shared_io_q2_3 */ + <0x0000003c 0x00000008>, /* Register: pinmux_shared_io_q2_4 */ + <0x00000040 0x00000008>, /* Register: pinmux_shared_io_q2_5 */ + <0x00000044 0x00000008>, /* Register: pinmux_shared_io_q2_6 */ + <0x00000048 0x00000008>, /* Register: pinmux_shared_io_q2_7 */ + <0x0000004c 0x00000008>, /* Register: pinmux_shared_io_q2_8 */ + <0x00000050 0x00000008>, /* Register: pinmux_shared_io_q2_9 */ + <0x00000054 0x00000008>, /* Register: pinmux_shared_io_q2_10 */ + <0x00000058 0x00000008>, /* Register: pinmux_shared_io_q2_11 */ + <0x0000005c 0x00000008>, /* Register: pinmux_shared_io_q2_12 */ + <0x00000060 0x00000008>, /* Register: pinmux_shared_io_q3_1 */ + <0x00000064 0x00000008>, /* Register: pinmux_shared_io_q3_2 */ + <0x00000068 0x00000008>, /* Register: pinmux_shared_io_q3_3 */ + <0x0000006c 0x00000008>, /* Register: pinmux_shared_io_q3_4 */ + <0x00000070 0x00000008>, /* Register: pinmux_shared_io_q3_5 */ + <0x00000074 0x00000008>, /* Register: pinmux_shared_io_q3_6 */ + <0x00000078 0x00000008>, /* Register: pinmux_shared_io_q3_7 */ + <0x0000007c 0x00000008>, /* Register: pinmux_shared_io_q3_8 */ + <0x00000080 0x00000008>, /* Register: pinmux_shared_io_q3_9 */ + <0x00000084 0x00000008>, /* Register: pinmux_shared_io_q3_10 */ + <0x00000088 0x00000008>, /* Register: pinmux_shared_io_q3_11 */ + <0x0000008c 0x00000008>, /* Register: pinmux_shared_io_q3_12 */ + <0x00000090 0x00000008>, /* Register: pinmux_shared_io_q4_1 */ + <0x00000094 0x00000008>, /* Register: pinmux_shared_io_q4_2 */ + <0x00000098 0x00000008>, /* Register: pinmux_shared_io_q4_3 */ + <0x0000009c 0x00000008>, /* Register: pinmux_shared_io_q4_4 */ + <0x000000a0 0x00000008>, /* Register: pinmux_shared_io_q4_5 */ + <0x000000a4 0x00000008>, /* Register: pinmux_shared_io_q4_6 */ + <0x000000a8 0x00000008>, /* Register: pinmux_shared_io_q4_7 */ + <0x000000ac 0x00000008>, /* Register: pinmux_shared_io_q4_8 */ + <0x000000b0 0x00000008>, /* Register: pinmux_shared_io_q4_9 */ + <0x000000b4 0x00000008>, /* Register: pinmux_shared_io_q4_10 */ + <0x000000b8 0x00000008>, /* Register: pinmux_shared_io_q4_11 */ + <0x000000bc 0x00000008>; /* Register: pinmux_shared_io_q4_12 */ + }; + + /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ + dedicated { + u-boot,dm-pre-reloc; + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + <0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */ + <0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */ + <0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */ + <0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */ + <0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */ + <0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */ + <0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */ + <0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */ + <0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */ + <0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */ + <0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */ + <0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */ + <0x0000003c 0x0000000f>, /* Register: pinmux_dedicated_io_16 */ + <0x00000040 0x0000000f>; /* Register: pinmux_dedicated_io_17 */ + }; + + /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ + dedicated_cfg { + u-boot,dm-pre-reloc; + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x003f3f3f>; + pinctrl-single,pins = + <0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */ + <0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */ + <0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */ + <0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */ + <0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */ + <0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */ + <0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */ + <0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */ + <0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */ + <0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */ + <0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */ + <0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */ + <0x00000130 0x000a282a>, /* Register: configuration_dedicated_io_12 */ + <0x00000134 0x000a282a>, /* Register: configuration_dedicated_io_13 */ + <0x00000138 0x000a282a>, /* Register: configuration_dedicated_io_14 */ + <0x0000013c 0x000a282a>, /* Register: configuration_dedicated_io_15 */ + <0x00000140 0x000a282a>, /* Register: configuration_dedicated_io_16 */ + <0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */ + }; + + /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */ + fpga { + u-boot,dm-pre-reloc; + reg = <0xffd07400 0x00000100>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000001>; + pinctrl-single,pins = + <0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */ + <0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */ + <0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */ + <0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */ + <0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */ + <0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */ + <0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */ + <0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */ + <0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */ + <0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */ + <0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */ + <0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */ + <0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */ + <0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */ + <0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */ + <0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */ + <0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */ + }; + }; + + /* + * Driver: altera_arria10_soc_noc_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_noc: noc@0xffd10000 { + u-boot,dm-pre-reloc; + compatible = "altr,socfpga-a10-noc"; + reg = <0xffd10000 0x00008000>; + reg-names = "mpu_m0"; + + firewall { + u-boot,dm-pre-reloc; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit + */ + mpu0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit + */ + l3-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit + */ + fpga2sdram0-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit + */ + fpga2sdram1-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit + */ + fpga2sdram2-0 = <0x00000000 0x0000ffff>; + }; + }; + + hps_fpgabridge0: fpgabridge@0 { + compatible = "altr,socfpga-hps2fpga-bridge"; + init-val = <1>; + }; + + hps_fpgabridge1: fpgabridge@1 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + init-val = <1>; + }; + + hps_fpgabridge2: fpgabridge@2 { + compatible = "altr,socfpga-fpga2hps-bridge"; + init-val = <1>; + }; + + hps_fpgabridge3: fpgabridge@3 { + compatible = "altr,socfpga-fpga2sdram0-bridge"; + init-val = <1>; + }; + + hps_fpgabridge4: fpgabridge@4 { + compatible = "altr,socfpga-fpga2sdram1-bridge"; + init-val = <0>; + }; + + hps_fpgabridge5: fpgabridge@5 { + compatible = "altr,socfpga-fpga2sdram2-bridge"; + init-val = <1>; + }; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 30b475254c..7e96b7e976 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -28,6 +28,10 @@ config TARGET_SOCFPGA_ARRIA10_SOCDK bool "Altera SOCFPGA SoCDK (Arria 10)" select TARGET_SOCFPGA_ARRIA10 +config TARGET_SOCFPGA_ARRIA10_R329 + bool "Reflex CES SOCFPGA R329 PCIe (Arria 10)" + select TARGET_SOCFPGA_ARRIA10 + config TARGET_SOCFPGA_ARRIA5_SOCDK bool "Altera SOCFPGA SoCDK (Arria V)" select TARGET_SOCFPGA_ARRIA5 @@ -78,6 +82,7 @@ endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK + default "r329-a10-pcie" if TARGET_SOCFPGA_ARRIA10_R329 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO @@ -92,6 +97,7 @@ config SYS_BOARD config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK + default "reflexces" if TARGET_SOCFPGA_ARRIA10_R329 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES @@ -107,6 +113,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK + default "socfpga_r329_a10_pcie" if TARGET_SOCFPGA_ARRIA10_R329 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO diff --git a/board/reflexces/r329-a10-pcie/Kconfig b/board/reflexces/r329-a10-pcie/Kconfig new file mode 100644 index 0000000000..fe4a0267e7 --- /dev/null +++ b/board/reflexces/r329-a10-pcie/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SOCFPGA_ARRIA10 + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "r329-a10-pcie" + +config SYS_VENDOR + default "reflexces" + +config SYS_SOC + default "socfpga_arria10" + +config SYS_CONFIG_NAME + default "socfpga_r329_a10_pcie" + +endif diff --git a/board/reflexces/r329-a10-pcie/MAINTAINERS b/board/reflexces/r329-a10-pcie/MAINTAINERS new file mode 100644 index 0000000000..0ed98d8023 --- /dev/null +++ b/board/reflexces/r329-a10-pcie/MAINTAINERS @@ -0,0 +1,8 @@ +R329 BOARD +M: Xavier Ruppen <xruppen(a)gmail.com> +S: Maintained +F: board/reflexces/r329-a10-pcie/ +F: include/configs/socfpga_arria10_r329.h +F: configs/socfpga_r329_a10_pcie_defconfig +F: arch/arm/dts/socfpga_arria10_r329.dts +F: arch/arm/dts/socfpga_arria10_r329_handoff.dtsi diff --git a/board/reflexces/r329-a10-pcie/Makefile b/board/reflexces/r329-a10-pcie/Makefile new file mode 100644 index 0000000000..80d0004346 --- /dev/null +++ b/board/reflexces/r329-a10-pcie/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2015 Altera Corporation <www.altera.com> + +obj-y := socfpga.o diff --git a/board/reflexces/r329-a10-pcie/fit_spl_fpga.its b/board/reflexces/r329-a10-pcie/fit_spl_fpga.its new file mode 100644 index 0000000000..eb761263ab --- /dev/null +++ b/board/reflexces/r329-a10-pcie/fit_spl_fpga.its @@ -0,0 +1,45 @@ +/* + * The fitImage source for Reflex CES R329 loading U-Boot with bitstream on EPCQ. + * + * Copyright (C) 2018 Xavier Ruppen <xruppen(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; + +/ { + description = "FIT image with U-Boot proper"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot (32-bit)"; + data = /incbin/("../../../u-boot-nodtb.bin"); + type = "standalone"; + os = "U-Boot"; + arch = "arm"; + compression = "none"; + load = <0x01000040>; + entry = <0x01000040>; + }; + + fdt { + description = "Reflex CES R329 flat device-tree"; + data = /incbin/("../../../u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + load = <0x00f00000>; + }; + }; + + configurations { + default = "conf"; + conf { + description = "Reflex CES R329 SOM-A10_PCIe"; + loadables = "uboot"; + fdt = "fdt"; + }; + }; +}; diff --git a/board/reflexces/r329-a10-pcie/socfpga.c b/board/reflexces/r329-a10-pcie/socfpga.c new file mode 100644 index 0000000000..4c466cb944 --- /dev/null +++ b/board/reflexces/r329-a10-pcie/socfpga.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Altera Corporation <www.altera.com> + */ + +#include <common.h> diff --git a/configs/socfpga_r329_a10_pcie_defconfig b/configs/socfpga_r329_a10_pcie_defconfig new file mode 100644 index 0000000000..03f49f9587 --- /dev/null +++ b/configs/socfpga_r329_a10_pcie_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x01000040 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_TARGET_SOCFPGA_ARRIA10_R329=y +CONFIG_SPL=y +CONFIG_IDENT_STRING="socfpga_r329_a10_pcie" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_r329" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/reflexces/r329-a10-pcie/fit_spl_fpga.its" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_r329.dtb" +CONFIG_VERSION_VARIABLE=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FPGA_SUPPORT=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" +CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_FPGA_SOCFPGA=y +CONFIG_DM_GPIO=y +CONFIG_DWAPB_GPIO=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/include/configs/socfpga_r329_a10_pcie.h b/include/configs/socfpga_r329_a10_pcie.h new file mode 100644 index 0000000000..a802ff585b --- /dev/null +++ b/include/configs/socfpga_r329_a10_pcie.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015-2017 Altera Corporation <www.altera.com> + */ + +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__ +#define __CONFIG_SOCFGPA_ARRIA10_H__ + +#include <asm/arch/base_addr_a10.h> + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * U-Boot general configurations + */ +/* Cache options */ +#define CONFIG_SYS_DCACHE_OFF + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0xC0000000 + +/* Ethernet on SoC (EMAC) */ + +/* + * U-Boot environment configurations + */ + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * L4 OSC1 Timer 0 + */ +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +/* + * Flash configurations + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */ -- 2.17.1

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[U-Boot] [PATCH 0/3] add support for the asus C201 chromebook (4GiB)
by Marty E. Plummer 25 Jul '18

25 Jul '18

Build and boot tested on my chromebook, which was generously altered by Simon Glass to have a servo header and also generously provided a servo board itself to do debugging with. It ''works'', but has a few oddities. I can't seem to get it to see my external sdcard or a usb flash drive, so I've been having to ymodem my kernel, fdt, and initramfs over to test booting (which does work). The screen is a bit inconsistent on whether or not it activates any given power cycle, but when it does work, it works right. The changes to sdram_common.c were taken from coreboot, as it has otherwise identical code (minus the if (!size_mb) block), and actually works on my hardware. Marty E. Plummer (3): sf: Add GigaDevice gd25q32b entry rockchip: add support for veyron-speedy (ASUS Chromebook C201) rockchip: fix incorrect detection of ram size arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-veyron-speedy.dts | 189 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +- arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++ arch/arm/mach-rockchip/sdram_common.c | 62 ++++--- board/google/veyron/Kconfig | 16 ++ configs/chromebook_speedy_defconfig | 96 +++++++++++ drivers/mtd/spi/spi_flash_ids.c | 1 + 8 files changed, 353 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts create mode 100644 configs/chromebook_speedy_defconfig -- 2.17.0

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[U-Boot] [PATCH v3 0/6] Add support of CONFIG_BLK for STM32Fx platforms
by Patrice Chotard 25 Jul '18

25 Jul '18

This series : - adds support of CONFIG_BLK flag to STM32Fx platforms - enables CONFIG_BLK flag for STM32Fx based boards - adds missing clk_free() call in error path Changes in v3: - remove usage of "cd_inverted" DT property in dm_mmc_getcd() Changes in v2: - replace devfdt_get_addr() by dev_read_addr() - re-introduce arm_pl180_mmc_ofdata_to_platdata() Patrice Chotard (6): configs: stm32f429-evaluation: Enable CONFIG_BLK configs: stm32f746-disco: Enable CONFIG_BLK configs: stm32f469-disco: Enable CONFIG_BLK mmc: arm_pl180_mmci: Update to support CONFIG_BLK mmc: arm_pl180_mmci: Add missing clk_free mmc: arm_pl180_mmci: Remove cd_inverted host's struct field configs/stm32f429-evaluation_defconfig | 1 - configs/stm32f469-discovery_defconfig | 1 - configs/stm32f746-disco_defconfig | 1 - drivers/mmc/arm_pl180_mmci.c | 73 +++++++++++++++++++--------------- drivers/mmc/arm_pl180_mmci.h | 1 - 5 files changed, 42 insertions(+), 35 deletions(-) -- 1.9.1

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