June 2018 - U-Boot

[U-Boot] [PATCH 01/12] arch: arm: mach-rockchip: rk3288: Enable regulators in board_init
by Janine Hagemann 13 Jul '18

13 Jul '18

At start-up, the regulators have to be enabled. Let's use regulators_enable_boot_on() to enable the regulators needed for boot. Signed-off-by: Wadim Egorov <w.egorov(a)phytec.de> Signed-off-by: Janine Hagemann <j.hagemann(a)phytec.de> --- arch/arm/mach-rockchip/rk3288-board.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 8c128d4..759bfbe 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -159,6 +159,12 @@ err: #else int ret; + ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulator\n", __func__); + return ret; + } + /* We do some SoC one time setting here */ if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { ret = veyron_init(); -- 2.7.4

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[U-Boot] [PATCH v3 0/4] rk3288: veyron: Enable SDMMC when booting from SPI
by Carlo Caione 13 Jul '18

13 Jul '18

From: Carlo Caione <carlo(a)endlessm.com> These patches toghether with the previously submitted patch [0] enable the chromebook veyron jerry to use the SDMMC interface when U-Boot is not chainloaded by depthcharge but booted directly from SPI. [0] https://marc.info/?l=u-boot&m=152836928803742&w=2 Changelog: V2: - Add Reviewed-by - Expand comment on PATCH 2/3 V3: - More Reviewed-by + Acked-by - New PATCH 4/4 Carlo Caione (4): rk3288: veyron: Init boot-on regulators rk3288: Disable JTAG function from sdmmc0 IO rockchip: veyron: Set vcc33_sd regulator value rk3288: Convert register defines to const uintptr_t arch/arm/mach-rockchip/rk3288-board.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) -- 2.17.1

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[U-Boot] [PATCH] rockchip: board: lion-rk3368: increase phy autonegotiation timeout
by Jakob Unterwurzacher 13 Jul '18

13 Jul '18

The first dhcp command consistently fails with a timeout when the lion-rk3368 board is connected to a Zyxel GS1100-24E Gigabit Ethernet switch: ethernet@ff290000 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Increasing PHY_ANEG_TIMEOUT from the default 4000 to 8000 makes the first dhcp command work reliably. Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher(a)theobroma-systems.com> --- include/configs/lion_rk3368.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/lion_rk3368.h b/include/configs/lion_rk3368.h index b9c6bf8954..cae0f1ed29 100644 --- a/include/configs/lion_rk3368.h +++ b/include/configs/lion_rk3368.h @@ -12,5 +12,7 @@ #define KERNEL_LOAD_ADDR 0x280000 #define DTB_LOAD_ADDR 0x5600000 #define INITRD_LOAD_ADDR 0x5bf0000 +/* PHY needs longer aneg time at 1G */ +#define PHY_ANEG_TIMEOUT 8000 #endif -- 2.17.0

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[U-Boot] [PATCH 1/1] rockchip: rk3399: spl: add missing \n to output
by Heinrich Schuchardt 13 Jul '18

13 Jul '18

Without the patch SPL (in case of an error) creates an output like: U-Boot SPL board initMissing DTB The patch adds the missing line feed. So now we get: U-Boot SPL board init Missing DTB Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- arch/arm/mach-rockchip/rk3399-board-spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index d4e9a161a4f..0ffdcb88bda 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -124,7 +124,7 @@ void board_init_f(ulong dummy) * printascii("string"); */ debug_uart_init(); - printascii("U-Boot SPL board init"); + printascii("U-Boot SPL board init\n"); #endif ret = spl_early_init(); -- 2.17.1

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[U-Boot] [PATCH 1/1] rockchip: evb-rk3399: correct README for board bring up
by Heinrich Schuchardt 13 Jul '18

13 Jul '18

%s/rkflashtool/rkdeveloptool/ We are using rkdeveloptool not rkflashtool. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- board/rockchip/evb_rk3399/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README index ada8ca7f3c1..83214670462 100644 --- a/board/rockchip/evb_rk3399/README +++ b/board/rockchip/evb_rk3399/README @@ -65,7 +65,7 @@ Compile the U-Boot Compile the rkdeveloptool ======================= Follow instructions in latest README - > cd ../rkflashtool + > cd ../rkdeveloptool > autoreconf -i > ./configure > make -- 2.17.1

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[U-Boot] [PATCH 1/1] rockchip: doc: clarify usage of CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
by Heinrich Schuchardt 13 Jul '18

13 Jul '18

Change the description relating to CONFIG_SPL_ROCKCHIP_BACK_TO_BROM to clarify that both RK3288 and RK3036 use CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- doc/README.rockchip | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/doc/README.rockchip b/doc/README.rockchip index d35071d653e..a35ca6f2c4e 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -124,11 +124,11 @@ something like: => The rockchip bootrom can load and boot an initial spl, then continue to -load a second-level bootloader(ie. U-BOOT) as soon as it returns to bootrom. -Therefore RK3288 has another loading sequence like RK3036. The option of -U-Boot is controlled with this setting in U-Boot: +load a second-stage bootloader (ie. U-Boot) as soon as the control is returned +to the bootrom. Both the RK3288 and the RK3036 use this special boot sequence. +The configuration option enabling this is: - #define CONFIG_SPL_ROCKCHIP_BACK_TO_BROM + CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y You can create the image via the following operations: -- 2.17.1

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[U-Boot] [PATCH v1 0/4] Inject boot-device into DTS and use in distro-boot on the RK3399-Q7
by Philipp Tomsich 13 Jul '18

13 Jul '18

The RK3399-Q7 has the ability to bypass the on-module eMMC and SPI (which always come first in our boot-order) and force a boot from an external SD card. If this is the case, we want all later boot-stages notified and will modify our environment for distro-boot to also try to boot from the SD card before trying to boot from eMMC. Klaus Goger (1): rockchip: rk3399: change boot_target based on u-boot,spl-boot-device Philipp Tomsich (3): spl: record boot_device into spl_image and call spl_perform_fixups spl: document 'chosen/u-boot,spl-boot-device' rockchip: rk3399: inject 'u-boot,spl-boot-device' for next-stage arch/arm/mach-rockchip/rk3399-board-spl.c | 48 +++++++++++++++ board/theobroma-systems/puma_rk3399/puma-rk3399.c | 74 +++++++++++++++++++++++ common/spl/spl.c | 12 +++- doc/device-tree-bindings/chosen.txt | 10 +++ include/spl.h | 7 +++ 5 files changed, 150 insertions(+), 1 deletion(-) -- 2.1.4

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[U-Boot] [PATCH v2] rockchip: i2c: enable new I2C controller for rk3066 and rk3188
by Alexander Kochetkov 13 Jul '18

13 Jul '18

rk3066 and rk3188 has two I2C controller implementations. Current I2C driver wan't work with legacy implementation. Switching between controllers is performed using a bit inside GFR_SOC_CON1 register. The bit setting is performed by pinctrl driver. The patch ask pinctrl to do settings. Signed-off-by: Alexander Kochetkov <al.kochet(a)gmail.com> --- drivers/i2c/rk_i2c.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 85 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index 332280c..ce6b441 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -34,6 +34,18 @@ struct rk_i2c { unsigned int speed; }; +enum { + RK_I2C_LEGACY, + RK_I2C_NEW, +}; + +/** + * @controller_type: i2c controller type + */ +struct rk_i2c_soc_data { + int controller_type; +}; + static inline void rk_i2c_get_div(int div, int *divh, int *divl) { *divl = div / 2; @@ -381,9 +393,38 @@ static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus) static int rockchip_i2c_probe(struct udevice *bus) { struct rk_i2c *priv = dev_get_priv(bus); + struct rk_i2c_soc_data *soc_data; + struct udevice *pinctrl; + int bus_nr; + int ret; priv->regs = dev_read_addr_ptr(bus); + soc_data = (struct rk_i2c_soc_data*)dev_get_driver_data(bus); + + if (soc_data->controller_type == RK_I2C_LEGACY) { + ret = dev_read_alias_seq(bus, &bus_nr); + if (ret < 0) { + debug("%s: Could not get alias for %s: %d\n", + __func__, bus->name, ret); + return ret; + } + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + return ret; + } + + /* pinctrl will switch I2C to new type */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_I2C0 + bus_nr); + if (ret) { + debug("%s: Failed to switch I2C to new type %s: %d\n", + __func__, bus->name, ret); + return ret; + } + } + return 0; } @@ -392,12 +433,51 @@ static const struct dm_i2c_ops rockchip_i2c_ops = { .set_bus_speed = rockchip_i2c_set_bus_speed, }; +static const struct rk_i2c_soc_data rk3066_soc_data = { + .controller_type = RK_I2C_LEGACY, +}; + +static const struct rk_i2c_soc_data rk3188_soc_data = { + .controller_type = RK_I2C_LEGACY, +}; + +static const struct rk_i2c_soc_data rk3228_soc_data = { + .controller_type = RK_I2C_NEW, +}; + +static const struct rk_i2c_soc_data rk3288_soc_data = { + .controller_type = RK_I2C_NEW, +}; + +static const struct rk_i2c_soc_data rk3328_soc_data = { + .controller_type = RK_I2C_NEW, +}; + +static const struct rk_i2c_soc_data rk3399_soc_data = { + .controller_type = RK_I2C_NEW, +}; + static const struct udevice_id rockchip_i2c_ids[] = { - { .compatible = "rockchip,rk3066-i2c" }, - { .compatible = "rockchip,rk3188-i2c" }, - { .compatible = "rockchip,rk3288-i2c" }, - { .compatible = "rockchip,rk3328-i2c" }, - { .compatible = "rockchip,rk3399-i2c" }, + { + .compatible = "rockchip,rk3066-i2c", + .data = (ulong)&rk3066_soc_data, + }, + { + .compatible = "rockchip,rk3188-i2c", + .data = (ulong)&rk3188_soc_data, + }, + { + .compatible = "rockchip,rk3288-i2c", + .data = (ulong)&rk3288_soc_data, + }, + { + .compatible = "rockchip,rk3328-i2c", + .data = (ulong)&rk3328_soc_data, + }, + { + .compatible = "rockchip,rk3399-i2c", + .data = (ulong)&rk3399_soc_data, + }, { } }; -- 1.7.9.5

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[U-Boot] [PATCH] rockchip: rk3188: add rk_board_late_init() hook
by Alexander Kochetkov 13 Jul '18

13 Jul '18

All other rockchip boards have rk_board_late_init() hook, so add it to rk3188 boards also. Signed-off-by: Alexander Kochetkov <al.kochet(a)gmail.com> --- arch/arm/mach-rockchip/rk3188-board.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 916d18f..fc58aeb 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -20,6 +20,11 @@ DECLARE_GLOBAL_DATA_PTR; +__weak int rk_board_late_init(void) +{ + return 0; +} + int board_late_init(void) { struct rk3188_grf *grf; @@ -35,7 +40,7 @@ int board_late_init(void) NOC_REMAP_MASK << NOC_REMAP_SHIFT); } - return 0; + return rk_board_late_init(); } int board_init(void) -- 1.7.9.5

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[U-Boot] [PATCH 1/4 v2] armv8: fsl: remove sata support
by andy.tang＠nxp.com 13 Jul '18

13 Jul '18

From: Yuantian Tang <andy.tang(a)nxp.com> Remove the old implementation in order to enable DM for sata Signed-off-by: Tang Yuantian <andy.tang(a)nxp.com> --- v2: - no change arch/arm/cpu/armv8/fsl-layerscape/soc.c | 54 ------------------------ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 32 -------------- 2 files changed, 0 insertions(+), 86 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index bfd6639..8028d52 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -6,8 +6,6 @@ #include <common.h> #include <fsl_immap.h> #include <fsl_ifc.h> -#include <ahci.h> -#include <scsi.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <asm/io.h> @@ -330,36 +328,6 @@ void fsl_lsch3_early_init_f(void) #endif } -#ifdef CONFIG_SCSI_AHCI_PLAT -int sata_init(void) -{ - struct ccsr_ahci __iomem *ccsr_ahci; - -#ifdef CONFIG_SYS_SATA2 - ccsr_ahci = (void *)CONFIG_SYS_SATA2; - out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); - out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); - out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); -#endif - -#ifdef CONFIG_SYS_SATA1 - ccsr_ahci = (void *)CONFIG_SYS_SATA1; - out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); - out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); - out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); - - ahci_init((void __iomem *)CONFIG_SYS_SATA1); - scsi_scan(false); -#endif - - return 0; -} -#endif - /* Get VDD in the unit mV from voltage ID */ int get_core_volt_from_fuse(void) { @@ -400,25 +368,6 @@ int get_core_volt_from_fuse(void) } #elif defined(CONFIG_FSL_LSCH2) -#ifdef CONFIG_SCSI_AHCI_PLAT -int sata_init(void) -{ - struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; - - /* Disable SATA ECC */ - out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); - out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); - out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); - out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); - - ahci_init((void __iomem *)CONFIG_SYS_SATA); - scsi_scan(false); - - return 0; -} -#endif static void erratum_a009929(void) { @@ -719,9 +668,6 @@ int qspi_ahb_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { -#ifdef CONFIG_SCSI_AHCI_PLAT - sata_init(); -#endif #ifdef CONFIG_CHAIN_OF_TRUST fsl_setenv_chain_of_trust(); #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 9a219a6..6e3a420 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -85,39 +85,7 @@ struct cpu_type { #define SVR_DEV(svr) ((svr) >> 8) #define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) -/* ahci port register default value */ -#define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY2_CFG 0x28184d1f -#define AHCI_PORT_PHY3_CFG 0x0e081509 -#define AHCI_PORT_TRANS_CFG 0x08000029 -#define AHCI_PORT_AXICC_CFG 0x3fffffff - #ifndef __ASSEMBLY__ -/* AHCI (sata) register map */ -struct ccsr_ahci { - u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ - u32 pcfg; /* port config */ - u32 ppcfg; /* port phy1 config */ - u32 pp2c; /* port phy2 config */ - u32 pp3c; /* port phy3 config */ - u32 pp4c; /* port phy4 config */ - u32 pp5c; /* port phy5 config */ - u32 axicc; /* AXI cache control */ - u32 paxic; /* port AXI config */ - u32 axipc; /* AXI PROT control */ - u32 ptc; /* port Trans Config */ - u32 pts; /* port Trans Status */ - u32 plc; /* port link config */ - u32 plc1; /* port link config1 */ - u32 plc2; /* port link config2 */ - u32 pls; /* port link status */ - u32 pls1; /* port link status1 */ - u32 pcmdc; /* port CMD config */ - u32 ppcs; /* port phy control status */ - u32 pberr; /* port 0/1 BIST error */ - u32 cmds; /* port 0/1 CMD status error */ -}; - #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); int get_core_volt_from_fuse(void); -- 1.7.1

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