June 2018 - U-Boot

[U-Boot] [PATCH u-boot 0/2] Add support for the FriendlyElec NanoPi K2 board
by Neil Armstrong 20 Jul '18

20 Jul '18

This adds platform code for the FriendlyElec NanoPi K2 board based on a Meson GXBB (S905) SoC with the Meson GXBB configuration. This initial submission only supports: - UART - MMC/SDCard - Ethernet - Reset Controller - Clock controller A sync with Linux 4.17 to get the device tree is also necessary. Neil Armstrong (1): ARM: dts: sync meson-gxbb-nanopi-k2 from Linux 4.17 Thomas McKahan (1): boards: amlogic: Add FriendlyElec NanoPi K2 board support arch/arm/dts/Makefile | 2 + arch/arm/dts/meson-gxbb-nanopi-k2.dts | 323 ++++++++++++++++++++++++++++++++++ arch/arm/mach-meson/Kconfig | 8 + board/amlogic/nanopi-k2/Kconfig | 12 ++ board/amlogic/nanopi-k2/MAINTAINERS | 6 + board/amlogic/nanopi-k2/Makefile | 7 + board/amlogic/nanopi-k2/README | 99 +++++++++++ board/amlogic/nanopi-k2/nanopi-k2.c | 61 +++++++ configs/nanopi-k2_defconfig | 40 +++++ include/configs/nanopi-k2.h | 18 ++ 10 files changed, 576 insertions(+) create mode 100644 arch/arm/dts/meson-gxbb-nanopi-k2.dts create mode 100644 board/amlogic/nanopi-k2/Kconfig create mode 100644 board/amlogic/nanopi-k2/MAINTAINERS create mode 100644 board/amlogic/nanopi-k2/Makefile create mode 100644 board/amlogic/nanopi-k2/README create mode 100644 board/amlogic/nanopi-k2/nanopi-k2.c create mode 100644 configs/nanopi-k2_defconfig create mode 100644 include/configs/nanopi-k2.h -- 2.7.4

2 5

[U-Boot] [PATCH 1/1] ARM: qemu-arm: enable RTC
by Heinrich Schuchardt 20 Jul '18

20 Jul '18

QEMU provides an emulated ARM AMBA PrimeCell PL031 RTC. The patch sets the base address in the board include file according to the definition in hw/arm/virt.c of the QEMU source. It defines the Kconfig option for the existing driver, and enables the RTC driver in qemu_arm64_defconfig and qemu_arm_defconfig as well as the date command. We need an RTC to provide the GetTime() runtime service in the UEFI subsystem. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- configs/qemu_arm64_defconfig | 2 ++ configs/qemu_arm_defconfig | 2 ++ drivers/rtc/Kconfig | 7 +++++++ include/configs/qemu-arm.h | 3 +++ 4 files changed, 14 insertions(+) diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index cdf5072fe4..e9a35d010f 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -9,6 +9,7 @@ CONFIG_DISTRO_DEFAULTS=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_DATE=y CONFIG_OF_BOARD=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y @@ -20,6 +21,7 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_RTC_PL031=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYSRESET=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index bbce6cd719..9d30dc31a5 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -9,6 +9,7 @@ CONFIG_DISTRO_DEFAULTS=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_DATE=y CONFIG_OF_BOARD=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y @@ -20,6 +21,7 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_RTC_PL031=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYSRESET=y diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index a3f8c8aecc..54365092ec 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -48,6 +48,13 @@ config RTC_RX8010SJ help Support for Epson RX8010SJ Real Time Clock devices. +config RTC_PL031 + bool "Enable ARM AMBA PL031 RTC driver" + help + The ARM PrimeCell Real Time Clock (PL031) is an optional SoC + peripheral based on the Advanced Microcontroller Bus Architecture + (AMBA). It is emulated in QEMU virtual ARM machines. + config RTC_MV bool "Enable Marvell RTC driver" depends on DM_RTC diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 095aec28b1..be516bac0c 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -24,6 +24,9 @@ /* For block devices, QEMU emulates an ICH9 AHCI controller over PCI */ #define CONFIG_SYS_SCSI_MAX_SCSI_ID 6 +/* QEMU emulates the ARM AMBA PL031 RTC */ +#define CONFIG_SYS_RTC_PL031_BASE 0x09010000 + /* Environment options */ #define CONFIG_ENV_SIZE SZ_64K -- 2.17.1

4 7

[U-Boot] [PATCH v4 0/3] Remove unused _relocate arguments
by Ivan Gorinov 20 Jul '18

20 Jul '18

EFI image handle and system table are not used in _relocate(). v4: Consistently use EFIABI for _relocate() everywhere. v3: Use EFIABI for _relocate() on x86; Rebased on u-boot/master. v2: Separated the changes in efi_main() arguments and calling convention. Ivan Gorinov (3): x86: Remove unused _relocate arguments arm: Remove unused _relocate arguments riscv: Remove unused _relocate arguments arch/arm/lib/crt0_aarch64_efi.S | 2 -- arch/arm/lib/crt0_arm_efi.S | 2 -- arch/arm/lib/reloc_aarch64_efi.c | 3 +-- arch/arm/lib/reloc_arm_efi.c | 3 +-- arch/riscv/lib/reloc_riscv_efi.c | 3 +-- arch/x86/lib/crt0_x86_64_efi.S | 3 --- arch/x86/lib/reloc_ia32_efi.c | 3 +-- arch/x86/lib/reloc_x86_64_efi.c | 3 +-- 8 files changed, 5 insertions(+), 17 deletions(-) -- 2.7.4

2 6

[U-Boot] [PATCH] arm/arm64: bitops: fix find_next_zero_bit to be compat with arm64
by Grygorii Strashko 20 Jul '18

20 Jul '18

Current implementation of find_next_zero_bit() is incompatible with arm64. Hence fix it by using BITS_PER_LONG define instead of constants and use generic ffz() implementation. Signed-off-by: Grygorii Strashko <grygorii.strashko(a)ti.com> --- arch/arm/include/asm/bitops.h | 41 +++++++++++++---------------------------- 1 file changed, 13 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 2750d9b..b02c454 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -15,6 +15,8 @@ #ifndef __ASM_ARM_BITOPS_H #define __ASM_ARM_BITOPS_H +#include <asm-generic/bitops/__ffs.h> + #ifdef __KERNEL__ #include <asm/proc-armv/system.h> @@ -108,50 +110,34 @@ static inline int __ilog2(unsigned int x) return generic_fls(x) - 1; } -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - int k; - - word = ~word; - k = 31; - if (word & 0x0000ffff) { k -= 16; word <<= 16; } - if (word & 0x00ff0000) { k -= 8; word <<= 8; } - if (word & 0x0f000000) { k -= 4; word <<= 4; } - if (word & 0x30000000) { k -= 2; word <<= 2; } - if (word & 0x40000000) { k -= 1; } - return k; -} +#define ffz(x) __ffs(~(x)) static inline int find_next_zero_bit(void *addr, int size, int offset) { - unsigned long *p = ((unsigned long *)addr) + (offset >> 5); - unsigned long result = offset & ~31UL; + unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG); + unsigned long result = offset & ~(BITS_PER_LONG - 1); unsigned long tmp; if (offset >= size) return size; size -= result; - offset &= 31UL; + offset &= (BITS_PER_LONG - 1); if (offset) { tmp = *(p++); - tmp |= ~0UL >> (32-offset); - if (size < 32) + tmp |= ~0UL >> (BITS_PER_LONG - offset); + if (size < BITS_PER_LONG) goto found_first; if (~tmp) goto found_middle; - size -= 32; - result += 32; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; } - while (size & ~31UL) { + while (size & ~(BITS_PER_LONG - 1)) { tmp = *(p++); if (~tmp) goto found_middle; - result += 32; - size -= 32; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; } if (!size) return result; @@ -191,7 +177,6 @@ found_middle: #endif /* __KERNEL__ */ #include <asm-generic/bitops/__fls.h> -#include <asm-generic/bitops/__ffs.h> #include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/fls64.h> -- 2.10.5

2 1

[U-Boot] [PATCH u-boot] boards: amlogic: Fix boards README
by Neil Armstrong 20 Jul '18

20 Jul '18

Fix typos and update the supported devices for all Amlogic boards. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- arch/arm/mach-meson/Kconfig | 2 +- board/amlogic/khadas-vim/README | 8 +++++++- board/amlogic/libretech-cc/README | 12 +++++++++--- board/amlogic/odroid-c2/README | 5 +++++ board/amlogic/p212/README | 7 +++++++ 5 files changed, 29 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 9a06ccc..5364e9d 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -17,7 +17,7 @@ config MESON_GXL select DM select DM_SERIAL help - The Amlogic Meson GXL (S905X and S905X) is an ARM SoC with a + The Amlogic Meson GXL (S905X and S905D) is an ARM SoC with a quad-core Cortex-A53 CPU and a Mali-450 GPU. if MESON_GXBB diff --git a/board/amlogic/khadas-vim/README b/board/amlogic/khadas-vim/README index 7eaca72..0ccd8f5 100644 --- a/board/amlogic/khadas-vim/README +++ b/board/amlogic/khadas-vim/README @@ -4,7 +4,7 @@ U-Boot for Khadas VIM Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion Technology Co., Ltd with the following specifications: - - Amlogic S905x ARM Cortex-A53 quad-core SoC @ 2GHz + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - ARM Mali 450 GPU - 2GB DDR3 SDRAM - 10/100 Ethernet @@ -20,6 +20,12 @@ Currently the u-boot port supports the following devices: - serial - eMMC, microSD - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC U-Boot compilation ================== diff --git a/board/amlogic/libretech-cc/README b/board/amlogic/libretech-cc/README index c06a392..d007f58 100644 --- a/board/amlogic/libretech-cc/README +++ b/board/amlogic/libretech-cc/README @@ -4,13 +4,13 @@ U-Boot for LibreTech CC LibreTech CC is a single board computer manufactured by Libre Technology with the following specifications: - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 2GHz + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - ARM Mali 450 GPU - 2GB DDR3 SDRAM - - Gigabit Ethernet + - 10/100 Ethernet - HDMI 2.0 4K/60Hz display - 40-pin GPIO header - - 4 x USB 2.0 Host, 1 x USB OTG + - 4 x USB 2.0 Host - eMMC, microSD - Infrared receiver @@ -20,6 +20,12 @@ Currently the U-Boot port supports the following devices: - serial - eMMC, microSD - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC U-Boot compilation ================== diff --git a/board/amlogic/odroid-c2/README b/board/amlogic/odroid-c2/README index b407c04..bed48c5 100644 --- a/board/amlogic/odroid-c2/README +++ b/board/amlogic/odroid-c2/README @@ -20,6 +20,11 @@ Currently the u-boot port supports the following devices: - serial - eMMC, microSD - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - ADC u-boot compilation ================== diff --git a/board/amlogic/p212/README b/board/amlogic/p212/README index 979502d..ef5370c 100644 --- a/board/amlogic/p212/README +++ b/board/amlogic/p212/README @@ -20,6 +20,13 @@ Schematics are available from Amlogic on demand. Currently the u-boot port supports the following devices: - serial - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC u-boot compilation ================== -- 2.7.4

2 1

[U-Boot] [PATCH] power: regulator: stpmu1: add power off delay
by Patrice Chotard 20 Jul '18

20 Jul '18

From: Christophe Kerello <christophe.kerello(a)st.com> This patch adds a delay when regulators are disabled. This delay is set to 5 ms to cover all use cases. The worst use case actually seen is during a SD card power cycle. Signed-off-by: Christophe Kerello <christophe.kerello(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- drivers/power/regulator/stpmu1.c | 20 ++++++++++++-------- include/power/stpmu1.h | 1 + 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/power/regulator/stpmu1.c b/drivers/power/regulator/stpmu1.c index 2dedb80acc42..6eb2420b6bcb 100644 --- a/drivers/power/regulator/stpmu1.c +++ b/drivers/power/regulator/stpmu1.c @@ -183,6 +183,8 @@ static int stpmu1_buck_get_enable(struct udevice *dev) static int stpmu1_buck_set_enable(struct udevice *dev, bool enable) { struct dm_regulator_uclass_platdata *uc_pdata; + int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS : + STPMU1_DEFAULT_STOP_DELAY_MS; int ret, uv; /* if regulator is already in the wanted state, nothing to do */ @@ -199,8 +201,7 @@ static int stpmu1_buck_set_enable(struct udevice *dev, bool enable) ret = pmic_clrsetbits(dev->parent, STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1), STPMU1_BUCK_EN, enable ? STPMU1_BUCK_EN : 0); - if (enable) - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(delay); return ret; } @@ -361,6 +362,8 @@ static int stpmu1_ldo_get_enable(struct udevice *dev) static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable) { struct dm_regulator_uclass_platdata *uc_pdata; + int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS : + STPMU1_DEFAULT_STOP_DELAY_MS; int ret, uv; /* if regulator is already in the wanted state, nothing to do */ @@ -377,8 +380,7 @@ static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable) ret = pmic_clrsetbits(dev->parent, STPMU1_LDOX_CTRL_REG(dev->driver_data - 1), STPMU1_LDO_EN, enable ? STPMU1_LDO_EN : 0); - if (enable) - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(delay); return ret; } @@ -489,6 +491,8 @@ static int stpmu1_vref_ddr_get_enable(struct udevice *dev) static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable) { + int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS : + STPMU1_DEFAULT_STOP_DELAY_MS; int ret; /* if regulator is already in the wanted state, nothing to do */ @@ -497,8 +501,7 @@ static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable) ret = pmic_clrsetbits(dev->parent, STPMU1_VREF_CTRL_REG, STPMU1_VREF_EN, enable ? STPMU1_VREF_EN : 0); - if (enable) - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(delay); return ret; } @@ -610,6 +613,8 @@ static int stpmu1_pwr_sw_get_enable(struct udevice *dev) static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable) { uint mask = 1 << dev->driver_data; + int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS : + STPMU1_DEFAULT_STOP_DELAY_MS; int ret; ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG); @@ -633,8 +638,7 @@ static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable) ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, mask, enable ? mask : 0); - if (enable) - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(delay); return ret; } diff --git a/include/power/stpmu1.h b/include/power/stpmu1.h index 61c58f3b7009..5906fbf832bf 100644 --- a/include/power/stpmu1.h +++ b/include/power/stpmu1.h @@ -44,6 +44,7 @@ #define STPMU1_NVM_USER_STATUS_ERROR BIT(1) #define STPMU1_DEFAULT_START_UP_DELAY_MS 1 +#define STPMU1_DEFAULT_STOP_DELAY_MS 5 #define STPMU1_USB_BOOST_START_UP_DELAY_MS 10 enum { -- 1.9.1

2 1

[U-Boot] [PATCH] phy: Be able to get phy from PHY provider
by Patrice Chotard 20 Jul '18

20 Jul '18

In case of phy are provided from a PHY provider nodes as following: usbphyc: usb-phy@5a006000 { compatible = "st,stm32mp1-usbphyc"; reg = <0x5a006000 0x1000>; clocks = <&rcc_clk USBPHY_K>; resets = <&rcc_rst USBPHY_R>; #address-cells = <1>; #size-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; vdda1v1-supply = <&reg11>; vdda1v8-supply = <&reg18> #phy-cells = <0>; }; usbphyc_port1: usb-phy@1 { reg = <1>; phy-supply = <&vdd_usb>; vdda1v1-supply = <&reg11>; vdda1v8-supply = <&reg18> #phy-cells = <1>; }; }; and PHY are called as following: usbh_ehci: usbh-ehci@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; clocks = <&rcc_clk USBH>; resets = <&rcc_rst USBH_R>; interrupts = <GIC_SPI 75 IRQ_TYPE_NONE>; companion = <&usbh_ohci>; phys = <&usbphyc_port0>; phy-names = "usb"; status = "okay"; }; generic_phy_get_by_index() must be updated to first look for PHY phandle as previously and in case of error looks for PHY provider by finding the parent's current node which is the PHY provider. args (ofnode_phandle_args struct) must also be updated by inserting the phy index into the PHY provider as args[0]. Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- drivers/phy/phy-uclass.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index c4b3e409b3e0..6162395e758b 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -36,8 +36,8 @@ int generic_phy_get_by_index(struct udevice *dev, int index, { struct ofnode_phandle_args args; struct phy_ops *ops; - int ret; struct udevice *phydev; + int i, ret; debug("%s(dev=%p, index=%d, phy=%p)\n", __func__, dev, index, phy); @@ -55,7 +55,20 @@ int generic_phy_get_by_index(struct udevice *dev, int index, if (ret) { debug("%s: uclass_get_device_by_ofnode failed: err=%d\n", __func__, ret); - return ret; + + /* Check if args.node's parent is a PHY provider */ + ret = uclass_get_device_by_ofnode(UCLASS_PHY, + ofnode_get_parent(args.node), + &phydev); + if (ret) + return ret; + + /* insert phy idx at first position into args array */ + for (i = args.args_count; i > 1 ; i--) + args.args[i] = args.args[i - 1]; + + args.args_count++; + args.args[0] = ofnode_read_u32_default(args.node, "reg", -1); } phy->dev = phydev; -- 1.9.1

2 1

[U-Boot] [PATCH] mmc: stm32_sdmmc2: update pwron management
by Patrice Chotard 20 Jul '18

20 Jul '18

From: Patrick Delaunay <patrick.delaunay(a)st.com> Correctly manage the SDMMC reset and card cycle power to fully handle the power cycle added in the MMC uclass and avoid issue with level-shifter with some uSDCARD. 3 states managed in driver: 1/ reset: SDMMC disable, signal HiZ 2/ power-cycle: SDMMC disable, signals drive to 0 3/ power-on: SDMMC enabled Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- drivers/mmc/stm32_sdmmc2.c | 78 +++++++++++++++++++++++++++++++++++++++------- 1 file changed, 67 insertions(+), 11 deletions(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index e8292c438d9f..a36612dd937e 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -56,7 +56,10 @@ struct stm32_sdmmc2_ctx { #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */ /* SDMMC_POWER register */ -#define SDMMC_POWER_PWRCTRL GENMASK(1, 0) +#define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0) +#define SDMMC_POWER_PWRCTRL_OFF 0 +#define SDMMC_POWER_PWRCTRL_CYCLE 2 +#define SDMMC_POWER_PWRCTRL_ON 3 #define SDMMC_POWER_VSWITCH BIT(2) #define SDMMC_POWER_VSWITCHEN BIT(3) #define SDMMC_POWER_DIRPOL BIT(4) @@ -440,23 +443,74 @@ retry_cmd: return ret; } -static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv) +/* + * Reset the SDMMC with the RCC.SDMMCxRST register bit. + * This will reset the SDMMC to the reset state and the CPSM and DPSM + * to the Idle state. SDMMC is disabled, Signals Hiz. + */ +static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv) { /* Reset */ reset_assert(&priv->reset_ctl); udelay(2); reset_deassert(&priv->reset_ctl); - udelay(1000); + /* init the needed SDMMC register after reset */ + writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER); +} + +/* + * Set the SDMMC in power-cycle state. + * This will make that the SDMMC_D[7:0], + * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being + * supplied through the signal lines. + */ +static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv) +{ + if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) == + SDMMC_POWER_PWRCTRL_CYCLE) + return; - /* Set Power State to ON */ - writel(SDMMC_POWER_PWRCTRL | priv->pwr_reg_msk, priv->base + SDMMC_POWER); + stm32_sdmmc2_reset(priv); + writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk, + priv->base + SDMMC_POWER); +} + +/* + * set the SDMMC state Power-on: the card is clocked + * manage the SDMMC state control: + * Reset => Power-Cycle => Power-Off => Power + * PWRCTRL=10 PWCTRL=00 PWCTRL=11 + */ +static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv) +{ + u32 pwrctrl = + readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK; + + if (pwrctrl == SDMMC_POWER_PWRCTRL_ON) + return; + + /* warning: same PWRCTRL value after reset and for power-off state + * it is the reset state here = the only managed by the driver + */ + if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) { + writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk, + priv->base + SDMMC_POWER); + } /* - * 1ms: required power up waiting time before starting the - * SD initialization sequence + * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE + * switch to Power-Off state: SDMCC disable, signals drive 1 */ - udelay(1000); + writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk, + priv->base + SDMMC_POWER); + + /* After the 1ms delay set the SDMMC to power-on */ + mdelay(1); + writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk, + priv->base + SDMMC_POWER); + + /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */ } #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1) @@ -464,8 +518,6 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) { struct mmc *mmc = mmc_get_mmc_dev(dev); struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); - struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev); - struct mmc_config *cfg = &plat->cfg; u32 desired = mmc->clock; u32 sys_clock = clk_get_rate(&priv->clk); u32 clk = 0; @@ -473,7 +525,9 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) debug("%s: bus_with = %d, clock = %d\n", __func__, mmc->bus_width, mmc->clock); - if ((mmc->bus_width == 1) && (desired == cfg->f_min)) + if (mmc->clk_disable) + stm32_sdmmc2_pwrcycle(priv); + else stm32_sdmmc2_pwron(priv); /* @@ -577,6 +631,8 @@ static int stm32_sdmmc2_probe(struct udevice *dev) upriv->mmc = &plat->mmc; + /* SDMMC init */ + stm32_sdmmc2_reset(priv); return 0; clk_disable: -- 1.9.1

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[U-Boot] [PATCH 1/2] spl: nor: Add FIT support
by York Sun 20 Jul '18

20 Jul '18

Add support of loading FIT image from NOR flash. Signed-off-by: York Sun <york.sun(a)nxp.com> --- common/spl/spl_nor.c | 42 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index bb6194f..b919fff 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -6,10 +6,25 @@ #include <common.h> #include <spl.h> +#ifdef CONFIG_SPL_LOAD_FIT +static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + debug("%s: sector %lx, count %lx, buf %p\n", + __func__, sector, count, buf); + memcpy(buf, (void *)sector, count); + + return count; +} +#endif + static int spl_nor_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { int ret; + __maybe_unused const struct image_header *header; + __maybe_unused struct spl_load_info load; + /* * Loading of the payload to SDRAM is done with skipping of * the mkimage header in this SPL NOR driver @@ -18,14 +33,24 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_OS_BOOT if (!spl_start_uboot()) { - const struct image_header *header; - /* * Load Linux from its location in NOR flash to its defined * location in SDRAM */ header = (const struct image_header *)CONFIG_SYS_OS_BASE; +#ifdef CONFIG_SPL_LOAD_FIT + if (image_get_magic(header) == FDT_MAGIC) { + debug("Found FIT\n"); + load.bl_len = 1; + load.read = spl_nor_load_read; + ret = spl_load_simple_fit(spl_image, &load, + CONFIG_SYS_OS_BASE, + (void *)header); + + return ret; + } +#endif if (image_get_os(header) == IH_OS_LINUX) { /* happy - was a Linux */ @@ -53,6 +78,19 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, * Load real U-Boot from its location in NOR flash to its * defined location in SDRAM */ +#ifdef CONFIG_SPL_LOAD_FIT + header = (const struct image_header *)CONFIG_SYS_UBOOT_BASE; + if (image_get_magic(header) == FDT_MAGIC) { + debug("Found FIT format U-Boot\n"); + load.bl_len = 1; + load.read = spl_nor_load_read; + ret = spl_load_simple_fit(spl_image, &load, + CONFIG_SYS_UBOOT_BASE, + (void *)header); + + return ret; + } +#endif ret = spl_parse_image_header(spl_image, (const struct image_header *)CONFIG_SYS_UBOOT_BASE); if (ret) -- 2.7.4

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[U-Boot] [PATCH] gpio: omap_gpio: Convert to auto-alloc feature when DT is supported
by Adam Ford 20 Jul '18

20 Jul '18

The omap_gpio driver has a TODO that says when every board is converted to DM and DT, the omap_gpio_bind can stop using calloc and switch to auto-alloc. This patch converts this driver to auto-calloc when DT is enabled. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index 79a975ce71..651f6994e4 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -302,6 +302,7 @@ static int omap_gpio_probe(struct udevice *dev) return 0; } +#if !CONFIG_IS_ENABLED(OF_CONTROL) static int omap_gpio_bind(struct udevice *dev) { struct omap_gpio_platdata *plat = dev_get_platdata(dev); @@ -334,6 +335,7 @@ static int omap_gpio_bind(struct udevice *dev) return 0; } +#endif static const struct udevice_id omap_gpio_ids[] = { { .compatible = "ti,omap3-gpio" }, @@ -342,12 +344,33 @@ static const struct udevice_id omap_gpio_ids[] = { { } }; +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int omap_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct omap_gpio_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = addr; + return 0; +} +#endif + U_BOOT_DRIVER(gpio_omap) = { .name = "gpio_omap", .id = UCLASS_GPIO, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .ofdata_to_platdata = of_match_ptr(omap_gpio_ofdata_to_platdata), + .bind = dm_scan_fdt_dev, + .platdata_auto_alloc_size = sizeof(struct omap_gpio_platdata), +#else + .bind = omap_gpio_bind, +#endif .ops = &gpio_omap_ops, .of_match = omap_gpio_ids, - .bind = omap_gpio_bind, .probe = omap_gpio_probe, .priv_auto_alloc_size = sizeof(struct gpio_bank), .flags = DM_FLAG_PRE_RELOC, -- 2.17.1

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