May 2018 - U-Boot

[U-Boot] [PATCH] driver: net: fsl-mc: updated copyright info
by Yogesh Gaur 09 May '18

09 May '18

Updated copyright info for the issues reported after running check-legal test. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur(a)nxp.com> --- Legally NXP and Freescale Semiconductor are same entity. drivers/net/fsl-mc/dpbp.c | 2 +- drivers/net/fsl-mc/dpio/dpio.c | 2 +- drivers/net/fsl-mc/dpmac.c | 2 +- drivers/net/fsl-mc/dpni.c | 2 +- drivers/net/fsl-mc/dprc.c | 2 +- drivers/net/fsl-mc/fsl_dpmng_cmd.h | 2 +- drivers/net/fsl-mc/mc.c | 4 ++-- drivers/net/ldpaa_eth/ldpaa_eth.c | 2 +- drivers/net/ldpaa_eth/ldpaa_eth.h | 2 +- include/fsl-mc/fsl_dpbp.h | 2 +- include/fsl-mc/fsl_dpio.h | 2 +- include/fsl-mc/fsl_dpmac.h | 2 +- include/fsl-mc/fsl_dpni.h | 2 +- include/fsl-mc/fsl_dprc.h | 2 +- include/fsl-mc/fsl_mc_cmd.h | 2 +- include/fsl-mc/fsl_mc_private.h | 2 +- 16 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/net/fsl-mc/dpbp.c b/drivers/net/fsl-mc/dpbp.c index a0552f4..a69eacb 100644 --- a/drivers/net/fsl-mc/dpbp.c +++ b/drivers/net/fsl-mc/dpbp.c @@ -1,7 +1,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/drivers/net/fsl-mc/dpio/dpio.c b/drivers/net/fsl-mc/dpio/dpio.c index ccac506..351d5b3 100644 --- a/drivers/net/fsl-mc/dpio/dpio.c +++ b/drivers/net/fsl-mc/dpio/dpio.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/drivers/net/fsl-mc/dpmac.c b/drivers/net/fsl-mc/dpmac.c index a719ac1..3a6306f 100644 --- a/drivers/net/fsl-mc/dpmac.c +++ b/drivers/net/fsl-mc/dpmac.c @@ -1,7 +1,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * Author: Prabhakar Kushwaha <prabhakar(a)freescale.com> * diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index 481f9d8..a8d8e18 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/drivers/net/fsl-mc/dprc.c b/drivers/net/fsl-mc/dprc.c index be02057..e7bb893 100644 --- a/drivers/net/fsl-mc/dprc.c +++ b/drivers/net/fsl-mc/dprc.c @@ -1,7 +1,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/drivers/net/fsl-mc/fsl_dpmng_cmd.h index a91da2b..6c4db04 100644 --- a/drivers/net/fsl-mc/fsl_dpmng_cmd.h +++ b/drivers/net/fsl-mc/fsl_dpmng_cmd.h @@ -1,4 +1,4 @@ -/* Copyright 2013-2016 Freescale Semiconductor Inc. +/* Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index ea9ae5b..ae1daa4 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1,6 +1,6 @@ /* - * Copyright (C) 2017 NXP Semiconductors - * Copyright (C) 2014 Freescale Semiconductor + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 109aba2..da2fdcc 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2016 Freescale Semiconductor + * Copyright 2014-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index 1e26630..4cfb11e 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2016 Freescale Semiconductor + * Copyright 2014-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 5401e86..2166098 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -1,7 +1,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 86251e2..d86ca54 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 36a5cca..f5ca5f7 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -1,7 +1,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * Author: Prabhakar Kushwaha <prabhakar(a)freescale.com> * diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index 5b80b6f..093a6da 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index 8ad01d4..67b40b3 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -1,7 +1,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index 1ec67b5..b3af425 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -1,4 +1,4 @@ -/* Copyright 2013-2016 Freescale Semiconductor Inc. +/* Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ diff --git a/include/fsl-mc/fsl_mc_private.h b/include/fsl-mc/fsl_mc_private.h index 2932d9d..6e2207a 100644 --- a/include/fsl-mc/fsl_mc_private.h +++ b/include/fsl-mc/fsl_mc_private.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2016 Freescale Semiconductor + * Copyright 2014-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ -- 1.9.1

3 3

[U-Boot] SYS_HAVE_*CACHE_MAINTENANCE
by AKASHI Takahiro 09 May '18

09 May '18

Emmanuel, # Since I haven't subscribed the ML, I can't reply to your post directly. You haven't enabled those configs on armv8/ARM64 (and other arch's as well). So if your patch is merged "as it is," I'm afraid that it will break some functions/commands on such architectures that already have cache maintenance operations without knowing those new configs. Thanks, -Takahiro AKASHI

1 0

[U-Boot] [PATCH] bootm.c: Correct the flush_len used in bootm_load_os()
by Tom Rini 09 May '18

09 May '18

In do_bootm_states when doing BOOTM_STATE_LOADOS we use load_end uninitialized and Coverity notes this now. This however leads down another interesting path. We pass this pointer to bootm_load_os and that in turn uses this uninitialized value immediately to calculate the flush length, and is wrong. We do not know what load_end will be until after bootm_decomp_image is called, so we must only set flush_len after that. All of this also makes it clear that the only reason we pass a pointer for load_end to bootm_load_os is so that we can call lmb_reserve on success. Rather than initialize load_end to 0 in do_bootm_states we can just call lmb_reserve ourself. Reported-by: Coverity (CID: 175572) Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- common/bootm.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/common/bootm.c b/common/bootm.c index 36162917a1b7..7bdfc4b2b20e 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -425,17 +425,17 @@ int bootm_decomp_image(int comp, ulong load, ulong image_start, int type, } #ifndef USE_HOSTCC -static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, - int boot_progress) +static int bootm_load_os(bootm_headers_t *images, int boot_progress) { image_info_t os = images->os; ulong load = os.load; + ulong load_end; ulong blob_start = os.start; ulong blob_end = os.end; ulong image_start = os.image_start; ulong image_len = os.image_len; ulong flush_start = ALIGN_DOWN(load, ARCH_DMA_MINALIGN); - ulong flush_len = *load_end - load; + ulong flush_len; bool no_overlap; void *load_buf, *image_buf; int err; @@ -444,27 +444,28 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, image_buf = map_sysmem(os.image_start, image_len); err = bootm_decomp_image(os.comp, load, os.image_start, os.type, load_buf, image_buf, image_len, - CONFIG_SYS_BOOTM_LEN, load_end); + CONFIG_SYS_BOOTM_LEN, &load_end); if (err) { bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); return err; } + flush_len = load_end - load; if (flush_start < load) flush_len += load - flush_start; flush_cache(flush_start, ALIGN(flush_len, ARCH_DMA_MINALIGN)); - debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end); + debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, load_end); bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED); no_overlap = (os.comp == IH_COMP_NONE && load == image_start); - if (!no_overlap && (load < blob_end) && (*load_end > blob_start)) { + if (!no_overlap && (load < blob_end) && (load_end > blob_start)) { debug("images.os.start = 0x%lX, images.os.end = 0x%lx\n", blob_start, blob_end); debug("images.os.load = 0x%lx, load_end = 0x%lx\n", load, - *load_end); + load_end); /* Check what type of image this is. */ if (images->legacy_hdr_valid) { @@ -479,6 +480,8 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, } } + lmb_reserve(&images->lmb, images->os.load, (load_end - + images->os.load)); return 0; } @@ -630,14 +633,9 @@ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], /* Load the OS */ if (!ret && (states & BOOTM_STATE_LOADOS)) { - ulong load_end; - iflag = bootm_disable_interrupts(); - ret = bootm_load_os(images, &load_end, 0); - if (ret == 0) - lmb_reserve(&images->lmb, images->os.load, - (load_end - images->os.load)); - else if (ret && ret != BOOTM_ERR_OVERLAP) + ret = bootm_load_os(images, 0); + if (ret && ret != BOOTM_ERR_OVERLAP) goto err; else if (ret == BOOTM_ERR_OVERLAP) ret = 0; -- 2.7.4

2 2

[U-Boot] [PATCH] image: fit: Show signatures and hashes for configurations
by Clément Péron 09 May '18

09 May '18

The signature/hash information are displayed for images but nor for configurations. Add subnodes printing in fit_conf_print() like it's done in fit_image_print() Signed-off-by: Clément Péron <peron.clem(a)gmail.com> --- common/image-fit.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/common/image-fit.c b/common/image-fit.c index 030a3e579f..16e7858254 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1590,6 +1590,7 @@ void fit_conf_print(const void *fit, int noffset, const char *p) const char *uname; int ret; int fdt_index, loadables_index; + int ndepth; /* Mandatory properties */ ret = fit_get_desc(fit, noffset, &desc); @@ -1643,6 +1644,16 @@ void fit_conf_print(const void *fit, int noffset, const char *p) } printf("%s\n", uname); } + + /* Process all hash subnodes of the component configuration node */ + for (ndepth = 0, noffset = fdt_next_node(fit, noffset, &ndepth); + (noffset >= 0) && (ndepth > 0); + noffset = fdt_next_node(fit, noffset, &ndepth)) { + if (ndepth == 1) { + /* Direct child node of the component configuration node */ + fit_image_print_verification_data(fit, noffset, p); + } + } } static int fit_image_select(const void *fit, int rd_noffset, int verify) -- 2.17.0

2 1

[U-Boot] [PATCH] arm: bitops: fix find_next_zero_bit() for case size < 32
by Grygorii Strashko 09 May '18

09 May '18

find_next_zero_bit() incorrectly handles cases when: - total bitmap size < 32 - rest of bits to process static inline int find_next_zero_bit(void *addr, int size, int offset) { unsigned long *p = ((unsigned long *)addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; if (offset >= size) return size; size -= result; offset &= 31UL; if (offset) { tmp = *(p++); tmp |= ~0UL >> (32-offset); if (size < 32) [1] goto found_first; if (~tmp) goto found_middle; size -= 32; result += 32; } while (size & ~31UL) { tmp = *(p++); if (~tmp) goto found_middle; result += 32; size -= 32; } [2] if (!size) return result; tmp = *p; found_first: [3] tmp |= ~0UL >> size; ^^^ algo can reach above line from from points: [1] offset > 0 and size < 32, tmp[offset-1..0] bits set to 1 [2] size < 32 - rest of bits to process in both cases bits to search are tmp[size-1..0], but line [3] will simply set all tmp[31-size..0] bits to 1 and ffz(tmp) below will fail. example: bitmap size = 16, offset = 0, bitmap is empty. code will go through the point [2], tmp = 0x0 after line [3] => tmp = 0xFFFF and ffz(tmp) will return 16. found_middle: return result + ffz(tmp); } Fix it by correctly seting tmp[31..size] bits to 1 in the above case [3]. Fixes: 81e9fe5a2988 ("arm: implement find_next_zero_bit function") Signed-off-by: Grygorii Strashko <grygorii.strashko(a)ti.com> --- arch/arm/include/asm/bitops.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index f33efeb..2750d9b 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -158,7 +158,7 @@ static inline int find_next_zero_bit(void *addr, int size, int offset) tmp = *p; found_first: - tmp |= ~0UL >> size; + tmp |= ~0UL << size; found_middle: return result + ffz(tmp); } -- 2.10.5

2 1

[U-Boot] [PATCH v2] cmd: add ADC cli commands
by Neil Armstrong 09 May '18

09 May '18

Add an 'adc' cli command to get adc devices informations and read single shots datas. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- cmd/Kconfig | 8 ++++ cmd/Makefile | 1 + cmd/adc.c | 121 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 cmd/adc.c diff --git a/cmd/Kconfig b/cmd/Kconfig index bc1d2f3..495c634 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -601,6 +601,14 @@ config CMD_ARMFLASH help ARM Ltd reference designs flash partition access +config CMD_ADC + bool "adc - Access Analog to Digital Converters info and data" + select ADC + select DM_REGULATOR + help + Shows ADC device info and permit printing one-shot analog converted + data from a named Analog to Digital Converter. + config CMD_CLK bool "clk - Show clock frequencies" help diff --git a/cmd/Makefile b/cmd/Makefile index c4269ac..4c66353 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -14,6 +14,7 @@ obj-y += version.o # command obj-$(CONFIG_CMD_AES) += aes.o +obj-$(CONFIG_CMD_ADC) += adc.o obj-$(CONFIG_CMD_ARMFLASH) += armflash.o obj-y += blk_common.o obj-$(CONFIG_SOURCE) += source.o diff --git a/cmd/adc.c b/cmd/adc.c new file mode 100644 index 0000000..66d4a4a --- /dev/null +++ b/cmd/adc.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstrong(a)baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <command.h> +#include <dm.h> +#include <adc.h> + +static int do_adc_list(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_ADC, &dev); + if (ret) { + printf("No available ADC device\n"); + return CMD_RET_FAILURE; + } + + do { + printf("- %s\n", dev->name); + + ret = uclass_next_device(&dev); + if (ret) + return CMD_RET_FAILURE; + } while (dev); + + return CMD_RET_SUCCESS; +} + +static int do_adc_info(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + unsigned int data_mask; + int ret, vss, vdd; + + if (argc < 2) + return CMD_RET_USAGE; + + ret = uclass_get_device_by_name(UCLASS_ADC, argv[1], &dev); + if (ret) { + printf("Unknown ADC device %s\n", argv[1]); + return CMD_RET_FAILURE; + } + + printf("ADC Device '%s' :\n", argv[1]); + + ret = adc_data_mask(dev, &data_mask); + if (!ret) + printf("data mask: %x\n", data_mask); + + ret = adc_vdd_value(dev, &vdd); + if (!ret) + printf("vdd: %duV\n", vdd); + + ret = adc_vss_value(dev, &vss); + if (!ret) + printf("vss: %duV\n", vss); + + return CMD_RET_SUCCESS; +} + +static int do_adc_single(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + unsigned int data; + int ret; + + if (argc < 3) + return CMD_RET_USAGE; + + ret = adc_channel_single_shot(argv[1], simple_strtol(argv[2], NULL, 0), + &data); + if (ret) { + printf("Error getting single shot for device %s channel %s\n", + argv[1], argv[2]); + return CMD_RET_FAILURE; + } + + printf("%u\n", data); + + return CMD_RET_SUCCESS; +} + +static cmd_tbl_t cmd_adc_sub[] = { + U_BOOT_CMD_MKENT(list, 1, 1, do_adc_list, "", ""), + U_BOOT_CMD_MKENT(info, 2, 1, do_adc_info, "", ""), + U_BOOT_CMD_MKENT(single, 3, 1, do_adc_single, "", ""), +}; + +static int do_adc(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return CMD_RET_USAGE; + + /* Strip off leading 'adc' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_adc_sub[0], ARRAY_SIZE(cmd_adc_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +static char adc_help_text[] = + "list - list ADC devices\n" + "adc info <name> - Get ADC device info\n" + "adc single <name> <channel> - Get Single data of ADC device channel"; + +U_BOOT_CMD(adc, 4, 1, do_adc, "ADC sub-system", adc_help_text); -- 2.7.4

2 1

[U-Boot] [PATCH v2] gdsys: drivers: Add gdsys_rxaui_ctrl driver
by Mario Six 09 May '18

09 May '18

Add a driver for RXAUI control on IHS FPGAs. Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- v1 -> v2: * Switched to regmap usage (instead of fpgamap) --- drivers/misc/Kconfig | 6 +++- drivers/misc/Makefile | 1 + drivers/misc/gdsys_rxaui_ctrl.c | 77 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 drivers/misc/gdsys_rxaui_ctrl.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d774569cbc..be900cf4d6 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -263,5 +263,9 @@ config SYS_I2C_EEPROM_ADDR_OVERFLOW endif - +config GDSYS_RXAUI_CTRL + bool "Enable gdsys RXAUI control driver" + depends on MISC + help + Support gdsys FPGA's RXAUI control. endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index e8d598cd47..4ab17129b1 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_QFW) += qfw.o obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o obj-$(CONFIG_STM32_RCC) += stm32_rcc.o obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o +obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o diff --git a/drivers/misc/gdsys_rxaui_ctrl.c b/drivers/misc/gdsys_rxaui_ctrl.c new file mode 100644 index 0000000000..8438951a74 --- /dev/null +++ b/drivers/misc/gdsys_rxaui_ctrl.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <regmap.h> +#include <misc.h> + +struct gdsys_rxaui_ctrl_regs { + u16 gen_cnt; + u16 err_cnt; + u16 succ_cnt; + u16 status; + u16 ctrl_0; + u16 ctrl_1; +}; + +#define rxaui_ctrl_set(map, member, val) \ + regmap_set(map, struct gdsys_rxaui_ctrl_regs, member, val) + +#define rxaui_ctrl_get(map, member, valp) \ + regmap_get(map, struct gdsys_rxaui_ctrl_regs, member, valp) + +struct gdsys_rxaui_ctrl_priv { + struct regmap *map; +}; + +int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val) +{ + struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev); + u16 state; + + rxaui_ctrl_get(priv->map, ctrl_1, &state); + + if (val) + state |= ~0x7800; + else + state &= ~0x7800; + + rxaui_ctrl_set(priv->map, ctrl_1, state); + + return 0; +} + +static const struct misc_ops gdsys_rxaui_ctrl_ops = { + .set_enabled = gdsys_rxaui_set_polarity_inversion, +}; + +int gdsys_rxaui_ctrl_probe(struct udevice *dev) +{ + struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev); + + regmap_init_mem(dev, &priv->map); + + return 0; +} + +static const struct udevice_id gdsys_rxaui_ctrl_ids[] = { + { .compatible = "gdsys,rxaui_ctrl" }, + { } +}; + +U_BOOT_DRIVER(gdsys_rxaui_ctrl) = { + .name = "gdsys_rxaui_ctrl", + .id = UCLASS_MISC, + .ops = &gdsys_rxaui_ctrl_ops, + .of_match = gdsys_rxaui_ctrl_ids, + .probe = gdsys_rxaui_ctrl_probe, + .priv_auto_alloc_size = sizeof(struct gdsys_rxaui_ctrl_priv), +}; -- 2.16.1

3 2

[U-Boot] [PATCH v2] clk: Add ICS8N3QV01 driver
by Mario Six 09 May '18

09 May '18

Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO. Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- v1 -> v2: * Expanded documentation * Switched to u8 for I2C register reading --- drivers/clk/Kconfig | 8 ++ drivers/clk/Makefile | 1 + drivers/clk/ics8n3qv01.c | 231 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 240 insertions(+) create mode 100644 drivers/clk/ics8n3qv01.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c382e8865f..60a6859c24 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -89,4 +89,12 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/renesas/Kconfig" +config ICS8N3QV01 + bool "Enable ICS8N3QV01 VCXO driver" + depends on CLK + help + Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled + Crystal Oscillator). The output frequency can be programmed via an + I2C interface. + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e05c607223..0b4f38527a 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o +obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o diff --git a/drivers/clk/ics8n3qv01.c b/drivers/clk/ics8n3qv01.c new file mode 100644 index 0000000000..045218bc83 --- /dev/null +++ b/drivers/clk/ics8n3qv01.c @@ -0,0 +1,231 @@ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc + * + * based on the gdsys osd driver, which is + * + * (C) Copyright 2010 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <clk-uclass.h> +#include <i2c.h> + +const long long ICS8N3QV01_FREF = 114285000; +const long long ICS8N3QV01_FREF_LL = 114285000LL; +const long long ICS8N3QV01_F_DEFAULT_0 = 156250000LL; +const long long ICS8N3QV01_F_DEFAULT_1 = 125000000LL; +const long long ICS8N3QV01_F_DEFAULT_2 = 100000000LL; +const long long ICS8N3QV01_F_DEFAULT_3 = 25175000LL; + +const uint MAX_FREQ_INDEX = 3; + +struct ics8n3qv01_priv { + ulong rate; +}; + +static int ics8n3qv01_get_fout_calc(struct udevice *dev, uint index, + uint *fout_calc) +{ + u64 n, mint, mfrac; + u8 reg_a, reg_b, reg_c, reg_d, reg_f; + int val[6]; + int i; + + if (index > MAX_FREQ_INDEX) + return -EINVAL; + + for (i = 0; i <= 5; ++i) { + u8 tmp = dm_i2c_reg_read(dev, 4 * i + index); + + if (tmp < 0) { + debug("%s: Error while reading i2c register %d.\n", + dev->name, 4 * i + index); + return tmp; + } + + val[i] = tmp; + } + + reg_a = val[0]; /* Register 0 + index */ + reg_b = val[1]; /* Register 4 + index */ + reg_c = val[2]; /* Register 8 + index */ + reg_d = val[3]; /* Register 12 + index */ + reg_f = val[5]; /* Register 20 + index */ + + mint = ((reg_a >> 1) & 0x1f) | /* MINTi[4-0]*/ + (reg_f & 0x20); /* MINTi[5] */ + mfrac = ((reg_a & 0x01) << 17) | /* MFRACi[17] */ + (reg_b << 9) | /* MFRACi[16-9] */ + (reg_c << 1) | /* MFRACi[8-1] */ + (reg_d >> 7); /* MFRACi[0] */ + n = reg_d & 0x7f; /* Ni[6-0] */ + + *fout_calc = (mint * ICS8N3QV01_FREF_LL + + mfrac * ICS8N3QV01_FREF_LL / 262144LL + + ICS8N3QV01_FREF_LL / 524288LL + + n / 2) + / n + * 1000000 + / (1000000 - 100); + + return 0; +} + +static int ics8n3qv01_calc_parameters(uint fout, uint *_mint, uint *_mfrac, + uint *_n) +{ + uint n, foutiic, fvcoiic, mint; + u64 mfrac; + + n = (2215000000U + fout / 2) / fout; + if (fout < 417000000U) + n = 2 * ((2215000000U / 2 + fout / 2) / fout); + else + n = (2215000000U + fout / 2) / fout; + + if ((n & 1) && n > 5) + n -= 1; + + foutiic = fout - (fout / 10000); + fvcoiic = foutiic * n; + + mint = fvcoiic / 114285000; + if (mint < 17 || mint > 63) + return -EINVAL; + + mfrac = ((u64)fvcoiic % 114285000LL) * 262144LL + / 114285000LL; + + *_mint = mint; + *_mfrac = mfrac; + *_n = n; + + return 0; +} + +static ulong ics8n3qv01_set_rate(struct clk *clk, ulong fout) +{ + struct ics8n3qv01_priv *priv = dev_get_priv(clk->dev); + uint n, mint, mfrac; + uint fout_calc = 0; + u64 fout_prog; + long long off_ppm; + int res, i; + u8 reg[6]; + int tmp; + int addr[] = {0, 4, 8, 12, 18, 20}; + + priv->rate = fout; + + res = ics8n3qv01_get_fout_calc(clk->dev, 1, &fout_calc); + + if (res) { + debug("%s: Error during output frequency calculation.\n", + clk->dev->name); + return res; + } + + off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000 + / ICS8N3QV01_F_DEFAULT_1; + printf("%s: PLL is off by %lld ppm\n", clk->dev->name, off_ppm); + fout_prog = (u64)fout * (u64)fout_calc + / ICS8N3QV01_F_DEFAULT_1; + res = ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n); + + if (res) { + debug("%s: Cannot determine mint parameter.\n", + clk->dev->name); + return res; + } + + /* Register 0 */ + tmp = dm_i2c_reg_read(clk->dev, 0) & 0xc0; + if (tmp < 0) + return tmp; + reg[0] = tmp | (mint & 0x1f) << 1; + reg[0] |= (mfrac >> 17) & 0x01; + + /* Register 4 */ + reg[1] = mfrac >> 9; + + /* Register 8 */ + reg[2] = mfrac >> 1; + + /* Register 12 */ + reg[3] = mfrac << 7; + reg[3] |= n & 0x7f; + + /* Register 18 */ + tmp = dm_i2c_reg_read(clk->dev, 18) & 0x03; + if (tmp < 0) + return tmp; + reg[4] = tmp | 0x20; + + /* Register 20 */ + tmp = dm_i2c_reg_read(clk->dev, 20) & 0x1f; + if (tmp < 0) + return tmp; + reg[5] = tmp | (mint & (1 << 5)); + + for (i = 0; i <= 5; ++i) { + res = dm_i2c_reg_write(clk->dev, addr[i], reg[i]); + if (res < 0) + return res; + } + + return 0; +} + +static int ics8n3qv01_request(struct clk *clock) +{ + return 0; +} + +static ulong ics8n3qv01_get_rate(struct clk *clk) +{ + struct ics8n3qv01_priv *priv = dev_get_priv(clk->dev); + + return priv->rate; +} + +static int ics8n3qv01_enable(struct clk *clk) +{ + return 0; +} + +static int ics8n3qv01_disable(struct clk *clk) +{ + return 0; +} + +static const struct clk_ops ics8n3qv01_ops = { + .request = ics8n3qv01_request, + .get_rate = ics8n3qv01_get_rate, + .set_rate = ics8n3qv01_set_rate, + .enable = ics8n3qv01_enable, + .disable = ics8n3qv01_disable, +}; + +static const struct udevice_id ics8n3qv01_ids[] = { + { .compatible = "idt,ics8n3qv01" }, + { /* sentinel */ } +}; + +int ics8n3qv01_probe(struct udevice *dev) +{ + return 0; +} + +U_BOOT_DRIVER(ics8n3qv01) = { + .name = "ics8n3qv01", + .id = UCLASS_CLK, + .ops = &ics8n3qv01_ops, + .of_match = ics8n3qv01_ids, + .probe = ics8n3qv01_probe, + .priv_auto_alloc_size = sizeof(struct ics8n3qv01_priv), +}; -- 2.16.1

2 1

[U-Boot] [PATCH v2 1/2] ihs_mdio: Encapsulate register access
by Mario Six 09 May '18

09 May '18

To prepare for DM conversion, encapsulate all register accesses in function calls. Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- v1 -> v2: No changes --- board/gdsys/common/ihs_mdio.c | 41 ++++++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c index 822517d4b2..b5fe3dbbdc 100644 --- a/board/gdsys/common/ihs_mdio.c +++ b/board/gdsys/common/ihs_mdio.c @@ -12,6 +12,34 @@ #include "ihs_mdio.h" +static inline u16 read_control(struct ihs_mdio_info *info) +{ + u16 val; + + FPGA_GET_REG(info->fpga, mdio.control, &val); + + return val; +} + +static inline void write_control(struct ihs_mdio_info *info, u16 val) +{ + FPGA_SET_REG(info->fpga, mdio.control, val); +} + +static inline void write_addr_data(struct ihs_mdio_info *info, u16 val) +{ + FPGA_SET_REG(info->fpga, mdio.address_data, val); +} + +static inline u16 read_rx_data(struct ihs_mdio_info *info) +{ + u16 val; + + FPGA_GET_REG(info->fpga, mdio.rx_data, &val); + + return val; +} + static int ihs_mdio_idle(struct mii_dev *bus) { struct ihs_mdio_info *info = bus->priv; @@ -19,7 +47,7 @@ static int ihs_mdio_idle(struct mii_dev *bus) unsigned int ctr = 0; do { - FPGA_GET_REG(info->fpga, mdio.control, &val); + val = read_control(info); udelay(100); if (ctr++ > 10) return -1; @@ -43,13 +71,13 @@ static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr, ihs_mdio_idle(bus); - FPGA_SET_REG(info->fpga, mdio.control, - ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10)); + write_control(info, + ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10)); /* wait for rx data available */ udelay(100); - FPGA_GET_REG(info->fpga, mdio.rx_data, &val); + val = read_rx_data(info); return val; } @@ -61,9 +89,8 @@ static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr, ihs_mdio_idle(bus); - FPGA_SET_REG(info->fpga, mdio.address_data, value); - FPGA_SET_REG(info->fpga, mdio.control, - ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10)); + write_addr_data(info, value); + write_control(info, ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10)); return 0; } -- 2.16.1

2 3

[U-Boot] [PATCH v3] db410c: set clk node to be probed before relocation
by Ramon Fried 09 May '18

09 May '18

The clock node is used by the serial driver and it's needed before relocation. This patch ensures that the msm-serial driver can actually use the clock node. Signed-off-by: Ramon Fried <ramon.fried(a)linaro.org> --- v2: Moved the u-boot,dm-pre-reloc attribute to the -uboot.dtsi file v3: Moved the forgotten u-boot,dm-pre-reloc also to -uboot.dtsi file arch/arm/dts/dragonboard410c-uboot.dtsi | 12 ++++++++++++ arch/arm/dts/dragonboard410c.dts | 1 - 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi b/arch/arm/dts/dragonboard410c-uboot.dtsi index c3475c4227..1de1419edc 100644 --- a/arch/arm/dts/dragonboard410c-uboot.dtsi +++ b/arch/arm/dts/dragonboard410c-uboot.dtsi @@ -10,6 +10,18 @@ config { u-boot,mmc-env-partition = "boot"; }; + + soc { + u-boot,dm-pre-reloc; + + qcom,gcc@1800000 { + u-boot,dm-pre-reloc; + }; + + serial@78b0000 { + u-boot,dm-pre-reloc; + }; + }; }; diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index 5ccfe7f8c8..aa9b0a138b 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -49,7 +49,6 @@ serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4"; reg = <0x78b0000 0x200>; - u-boot,dm-pre-reloc; clock = <&clkc 4>; }; -- 2.14.1

2 1