May 2018 - U-Boot

[U-Boot] [PATCH v4 0/6] Iotrace improvements
by Ramon Fried 08 Jun '18

08 Jun '18

These set of patches add few improvements to iotrace. * Region limiting - allows setting an address and size where only io operations that falls into that address are logged. * Timestamping - Timestamp every iotrace record with current timestamp * dumping - iotrace dump command for dumping all records from buffer in a readable fashion. In terms of backwards compatibility, the timestamp is not backward compatible as it changes the iotrace record. so if one developed an offline parsing tool it will be broken. I though of adding #ifdef specific for that, but eventually I didn't. Changes in v4: - Resend complete patchset with patman Changes in v3: - fixed wrong usage of WARN_ONCE Changes in v2: - introduced needed_size to notify the user about the needed buffer size. Changes in v1: - Change timestamp function to get_ticks() Ramon Fried (6): cmd: iotrace: add set region command iotrace: add IO region limit common: iotrace: add timestamp to iotrace records iotrace: move record definitons to header file cmd: iotrace: add dump trace command iotrace: fix behaviour when buffer is full cmd/iotrace.c | 63 ++++++++++++++++++++++++++++++++++++++++++--- common/iotrace.c | 65 +++++++++++++++++++++++++++-------------------- include/iotrace.h | 57 +++++++++++++++++++++++++++++++++++++++-- 3 files changed, 153 insertions(+), 32 deletions(-) -- 2.17.0

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[U-Boot] [PATCH] mtd: ubi: Add missing newlines in ubi_init()
by Stefan Roese 08 Jun '18

08 Jun '18

I just stumbled over some cluttered UBI messages. It seems some newline chars are missing in the current U-Boot UBI source. Lets fix this in U-Boot as well (Linux has those fixes already). Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> --- drivers/mtd/ubi/build.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 0198d8bfa8..42c5270c7f 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -1250,7 +1250,7 @@ int ubi_init(void) BUILD_BUG_ON(sizeof(struct ubi_vid_hdr) != 64); if (mtd_devs > UBI_MAX_DEVICES) { - pr_err("UBI error: too many MTD devices, maximum is %d", + pr_err("UBI error: too many MTD devices, maximum is %d\n", UBI_MAX_DEVICES); return -EINVAL; } @@ -1262,7 +1262,7 @@ int ubi_init(void) err = misc_register(&ubi_ctrl_cdev); if (err) { - pr_err("UBI error: cannot register device"); + pr_err("UBI error: cannot register device\n"); goto out; } @@ -1289,7 +1289,7 @@ int ubi_init(void) mtd = open_mtd_device(p->name); if (IS_ERR(mtd)) { err = PTR_ERR(mtd); - pr_err("UBI error: cannot open mtd %s, error %d", + pr_err("UBI error: cannot open mtd %s, error %d\n", p->name, err); /* See comment below re-ubi_is_module(). */ if (ubi_is_module()) @@ -1302,7 +1302,7 @@ int ubi_init(void) p->vid_hdr_offs, p->max_beb_per1024); mutex_unlock(&ubi_devices_mutex); if (err < 0) { - pr_err("UBI error: cannot attach mtd%d", + pr_err("UBI error: cannot attach mtd%d\n", mtd->index); put_mtd_device(mtd); @@ -1326,7 +1326,7 @@ int ubi_init(void) err = ubiblock_init(); if (err) { - pr_err("UBI error: block: cannot initialize, error %d", err); + pr_err("UBI error: block: cannot initialize, error %d\n", err); /* See comment above re-ubi_is_module(). */ if (ubi_is_module()) @@ -1353,7 +1353,7 @@ out: mtd_devs = 0; #endif class_unregister(&ubi_class); - pr_err("UBI error: cannot initialize UBI, error %d", err); + pr_err("UBI error: cannot initialize UBI, error %d\n", err); return err; } late_initcall(ubi_init); -- 2.17.0

2 1

[U-Boot] [UNTESTED PATCH] ARM: orion5x: fix use of callee-saved registers in lowloevel_init
by Mans Rullgard 08 Jun '18

08 Jun '18

The lowlevel_init function uses r4 and r6 without preserving their values as required by the AAPCS. Use r0 and r2 instead as these are call-clobbered. Signed-off-by: Mans Rullgard <mans(a)mansr.com> --- arch/arm/mach-orion5x/lowlevel_init.S | 168 +++++++++++++------------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index 3f38f36ff294..a4e113601013 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -72,67 +72,67 @@ lowlevel_init: #ifdef CONFIG_SPL_BUILD - /* Use 'r4 as the base for internal register accesses */ - ldr r4, =ORION5X_REGS_PHY_BASE + /* Use 'r2 as the base for internal register accesses */ + ldr r2, =ORION5X_REGS_PHY_BASE /* move internal registers from the default 0xD0000000 * to their intended location, defined by SoC */ ldr r3, =0xD0000000 add r3, r3, #0x20000 - str r4, [r3, #0x80] + str r2, [r3, #0x80] /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r2, #0x01000 /*DDR SDRAM Initialization Control */ - ldr r6, =0x00000001 - str r6, [r3, #0x480] + ldr r0, =0x00000001 + str r0, [r3, #0x480] /* Use R3 as the base for PCI registers */ - add r3, r4, #0x31000 + add r3, r2, #0x31000 /* Disable arbiter */ - ldr r6, =0x00000030 - str r6, [r3, #0xd00] + ldr r0, =0x00000030 + str r0, [r3, #0xd00] /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r2, #0x01000 /* set all dram windows to 0 */ - mov r6, #0 - str r6, [r3, #0x504] - str r6, [r3, #0x50C] - str r6, [r3, #0x514] - str r6, [r3, #0x51C] + mov r0, #0 + str r0, [r3, #0x504] + str r0, [r3, #0x50C] + str r0, [r3, #0x514] + str r0, [r3, #0x51C] /* 1) Configure SDRAM */ - ldr r6, =SDRAM_CONFIG - str r6, [r3, #0x400] + ldr r0, =SDRAM_CONFIG + str r0, [r3, #0x400] /* 2) Set SDRAM Control reg */ - ldr r6, =SDRAM_CONTROL - str r6, [r3, #0x404] + ldr r0, =SDRAM_CONTROL + str r0, [r3, #0x404] /* 3) Write SDRAM address control register */ - ldr r6, =SDRAM_ADDR_CTRL - str r6, [r3, #0x410] + ldr r0, =SDRAM_ADDR_CTRL + str r0, [r3, #0x410] /* 4) Write SDRAM bank 0 size register */ - ldr r6, =SDRAM_BANK0_SIZE - str r6, [r3, #0x504] + ldr r0, =SDRAM_BANK0_SIZE + str r0, [r3, #0x504] /* keep other banks disabled */ /* 5) Write SDRAM open pages control register */ - ldr r6, =SDRAM_OPEN_PAGE_EN - str r6, [r3, #0x414] + ldr r0, =SDRAM_OPEN_PAGE_EN + str r0, [r3, #0x414] /* 6) Write SDRAM timing Low register */ - ldr r6, =SDRAM_TIME_CTRL_LOW - str r6, [r3, #0x408] + ldr r0, =SDRAM_TIME_CTRL_LOW + str r0, [r3, #0x408] /* 7) Write SDRAM timing High register */ - ldr r6, =SDRAM_TIME_CTRL_HI - str r6, [r3, #0x40C] + ldr r0, =SDRAM_TIME_CTRL_HI + str r0, [r3, #0x40C] /* 8) Write SDRAM mode register */ /* The CPU must not attempt to change the SDRAM Mode register setting */ @@ -143,73 +143,73 @@ lowlevel_init: /* and then sets SDRAM Mode register to its new value. */ /* 8.1 write 'nop' to SDRAM operation */ - ldr r6, =SDRAM_OP_NOP - str r6, [r3, #0x418] + ldr r0, =SDRAM_OP_NOP + str r0, [r3, #0x418] /* 8.2 poll SDRAM operation until back in 'normal' mode. */ 1: - ldr r6, [r3, #0x418] - cmp r6, #0 + ldr r0, [r3, #0x418] + cmp r0, #0 bne 1b /* 8.3 Now its safe to write new value to SDRAM Mode register */ - ldr r6, =SDRAM_MODE - str r6, [r3, #0x41C] + ldr r0, =SDRAM_MODE + str r0, [r3, #0x41C] /* 8.4 Set new mode */ - ldr r6, =SDRAM_OP_SETMODE - str r6, [r3, #0x418] + ldr r0, =SDRAM_OP_SETMODE + str r0, [r3, #0x418] /* 8.5 poll SDRAM operation until back in 'normal' mode. */ 2: - ldr r6, [r3, #0x418] - cmp r6, #0 + ldr r0, [r3, #0x418] + cmp r0, #0 bne 2b /* DDR SDRAM Address/Control Pads Calibration */ - ldr r6, [r3, #0x4C0] + ldr r0, [r3, #0x4C0] /* Set Bit [31] to make the register writable */ - orr r6, r6, #SDRAM_PAD_CTRL_WR_EN - str r6, [r3, #0x4C0] + orr r0, r0, #SDRAM_PAD_CTRL_WR_EN + str r0, [r3, #0x4C0] - bic r6, r6, #SDRAM_PAD_CTRL_WR_EN - bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN - bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK - bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK + bic r0, r0, #SDRAM_PAD_CTRL_WR_EN + bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN + bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK + bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK /* Get the final N locked value of driving strength [22:17] */ - mov r1, r6 + mov r1, r0 mov r1, r1, LSL #9 mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ - orr r6, r6, r1 - str r6, [r3, #0x4C0] + orr r0, r0, r1 + str r0, [r3, #0x4C0] /* DDR SDRAM Data Pads Calibration */ - ldr r6, [r3, #0x4C4] + ldr r0, [r3, #0x4C4] /* Set Bit [31] to make the register writable */ - orr r6, r6, #SDRAM_PAD_CTRL_WR_EN - str r6, [r3, #0x4C4] + orr r0, r0, #SDRAM_PAD_CTRL_WR_EN + str r0, [r3, #0x4C4] - bic r6, r6, #SDRAM_PAD_CTRL_WR_EN - bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN - bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK - bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK + bic r0, r0, #SDRAM_PAD_CTRL_WR_EN + bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN + bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK + bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK /* Get the final N locked value of driving strength [22:17] */ - mov r1, r6 + mov r1, r0 mov r1, r1, LSL #9 mov r1, r1, LSR #26 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ - orr r6, r6, r1 + orr r0, r0, r1 - str r6, [r3, #0x4C4] + str r0, [r3, #0x4C4] /* Implement Guideline (GL# MEM-3) Drive Strength Value */ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ @@ -217,37 +217,37 @@ lowlevel_init: ldr r1, =DDR1_PAD_STRENGTH_DEFAULT /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */ - ldr r6, [r3, #0x4C0] - orr r6, r6, #SDRAM_PAD_CTRL_WR_EN - str r6, [r3, #0x4C0] + ldr r0, [r3, #0x4C0] + orr r0, r0, #SDRAM_PAD_CTRL_WR_EN + str r0, [r3, #0x4C0] /* Correct strength and disable writes again */ - bic r6, r6, #SDRAM_PAD_CTRL_WR_EN - bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK - orr r6, r6, r1 - str r6, [r3, #0x4C0] + bic r0, r0, #SDRAM_PAD_CTRL_WR_EN + bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK + orr r0, r0, r1 + str r0, [r3, #0x4C0] /* Enable writes to DDR SDRAM Data Pads Calibration register */ - ldr r6, [r3, #0x4C4] - orr r6, r6, #SDRAM_PAD_CTRL_WR_EN - str r6, [r3, #0x4C4] + ldr r0, [r3, #0x4C4] + orr r0, r0, #SDRAM_PAD_CTRL_WR_EN + str r0, [r3, #0x4C4] /* Correct strength and disable writes again */ - bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK - bic r6, r6, #SDRAM_PAD_CTRL_WR_EN - orr r6, r6, r1 - str r6, [r3, #0x4C4] + bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK + bic r0, r0, #SDRAM_PAD_CTRL_WR_EN + orr r0, r0, r1 + str r0, [r3, #0x4C4] /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ /* Get the "sample on reset" register for the DDR frequancy */ ldr r3, =0x10000 - ldr r6, [r3, #0x010] + ldr r0, [r3, #0x010] ldr r1, =MSAR_ARMDDRCLCK_MASK - and r1, r6, r1 + and r1, r0, r1 - ldr r6, =FTDLL_DDR1_166MHZ + ldr r0, =FTDLL_DDR1_166MHZ cmp r1, #MSAR_ARMDDRCLCK_333_167 beq 3f cmp r1, #MSAR_ARMDDRCLCK_500_167 @@ -255,7 +255,7 @@ lowlevel_init: cmp r1, #MSAR_ARMDDRCLCK_667_167 beq 3f - ldr r6, =FTDLL_DDR1_200MHZ + ldr r0, =FTDLL_DDR1_200MHZ cmp r1, #MSAR_ARMDDRCLCK_400_200_1 beq 3f cmp r1, #MSAR_ARMDDRCLCK_400_200 @@ -265,21 +265,21 @@ lowlevel_init: cmp r1, #MSAR_ARMDDRCLCK_800_200 beq 3f - ldr r6, =0 + ldr r0, =0 3: /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r2, #0x01000 ldr r2, [r3, #0x484] - orr r2, r2, r6 + orr r2, r2, r0 str r2, [r3, #0x484] /* enable for 2 GB DDR; detection should find out real amount */ - sub r6, r6, r6 - str r6, [r3, #0x500] - ldr r6, =0x7fff0001 - str r6, [r3, #0x504] + sub r0, r0, r0 + str r0, [r3, #0x500] + ldr r0, =0x7fff0001 + str r0, [r3, #0x504] #endif /* CONFIG_SPL_BUILD */ -- 2.17.0

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[U-Boot] [PATCH] patman: Fix unit tests for SPDX
by Simon Glass 08 Jun '18

08 Jun '18

The format of this line has changed. Update the patman test to suit. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- tools/patman/test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/test.py b/tools/patman/test.py index 343efc99bd8..c7ba4e6bb47 100644 --- a/tools/patman/test.py +++ b/tools/patman/test.py @@ -148,7 +148,7 @@ index 0000000..2234c87 --- /dev/null +++ b/common/bootstage.c @@ -0,0 +1,37 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ ++// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2011, Google Inc. All rights reserved. + * -- 2.17.0.441.gb46fe60e1d-goog

2 2

[U-Boot] [PATCH v3 1/2] buildman: Extract environment as part of each build
by Alex Kiernan 08 Jun '18

08 Jun '18

As we're building the boards, extract the default U-Boot environment to uboot.env so we can interrogate it later. Signed-off-by: Alex Kiernan <alex.kiernan(a)gmail.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - update tests for our usage of objcopy Changes in v2: - capture stderr/stdout so when the build fails we don't produce spurious output as part of the build tools/buildman/builderthread.py | 10 ++++++++++ tools/buildman/func_test.py | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index 0efe80d945..c84ba6acf1 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -351,6 +351,16 @@ class BuilderThread(threading.Thread): lines.append(size_result.stdout.splitlines()[1] + ' ' + rodata_size) + # Extract the environment from U-Boot and dump it out + cmd = ['%sobjcopy' % self.toolchain.cross, '-O', 'binary', + '-j', '.rodata.default_environment', + 'env/built-in.o', 'uboot.env'] + command.RunPipe([cmd], capture=True, + capture_stderr=True, cwd=result.out_dir, + raise_on_error=False, env=env) + ubootenv = os.path.join(result.out_dir, 'uboot.env') + self.CopyFiles(result.out_dir, build_dir, '', ['uboot.env']) + # Write out the image sizes file. This is similar to the output # of binutil's 'size' utility, but it omits the header line and # adds an additional hex value at the end of each line for the diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py index 9206fb299d..363db9d8ce 100644 --- a/tools/buildman/func_test.py +++ b/tools/buildman/func_test.py @@ -327,6 +327,9 @@ class TestFunctional(unittest.TestCase): def _HandleCommandObjdump(self, args): return command.CommandResult(return_code=0) + def _HandleCommandObjcopy(self, args): + return command.CommandResult(return_code=0) + def _HandleCommandSize(self, args): return command.CommandResult(return_code=0) @@ -359,6 +362,8 @@ class TestFunctional(unittest.TestCase): return self._HandleCommandNm(args) elif cmd.endswith('objdump'): return self._HandleCommandObjdump(args) + elif cmd.endswith('objcopy'): + return self._HandleCommandObjcopy(args) elif cmd.endswith( 'size'): return self._HandleCommandSize(args) -- 2.17.0

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[U-Boot] [RFC][DO NOT APPLY] binman: Switch to 'python-coverage'
by Tom Rini 07 Jun '18

07 Jun '18

The most portable way to get access to coverage is to invoke it as 'python-coverage'. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- So, here's the set of problems I have. First, running 'pip install coverage' doesn't get me a 'coverage' binary, so I've just never made good use of 'make tests' and so never have these run. It also means they aren't strictly in travis-ci, so they're never run automatically. With this patch, make tests executes for me, and now fails noting that a lot of things don't have coverage. I'm honestly not sure what the best path forward here is. --- tools/binman/README | 3 +-- tools/binman/binman.py | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tools/binman/README b/tools/binman/README index b20098177ee9..5d55ed68e3da 100644 --- a/tools/binman/README +++ b/tools/binman/README @@ -506,8 +506,7 @@ implementations target 100% test coverage. Run 'binman -T' to check this. To enable Python test coverage on Debian-type distributions (e.g. Ubuntu): - $ sudo apt-get install python-pip python-pytest - $ sudo pip install coverage + $ sudo apt-get install python-coverage python-pytest Advanced Features / Technical docs diff --git a/tools/binman/binman.py b/tools/binman/binman.py index fa2f551f5542..447062dca167 100755 --- a/tools/binman/binman.py +++ b/tools/binman/binman.py @@ -71,11 +71,11 @@ def RunTests(debug): def RunTestCoverage(): """Run the tests and check that we get 100% coverage""" # This uses the build output from sandbox_spl to get _libfdt.so - cmd = ('PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools coverage run ' + cmd = ('PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools python-coverage run ' '--include "tools/binman/*.py" --omit "*test*,*binman.py" ' 'tools/binman/binman.py -t' % options.build_dir) os.system(cmd) - stdout = command.Output('coverage', 'report') + stdout = command.Output('python-coverage', 'report') lines = stdout.splitlines() test_set= set([os.path.basename(line.split()[0]) -- 2.7.4

2 3

[U-Boot] NDS32 toolchain?
by Tom Rini 07 Jun '18

07 Jun '18

Hey, So I'm looking over my setups again at what we do and do not have build testing and run-time testing, and I see that for nds32 I just cannot find a good toolchain. If I try for example https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/7.3.0/… it first fails on the -G0 flag that we have set in and then it complains about a lack of position independent code support. Is the kernel.org toolchain perhaps configured incorrectly? Related, is there a QEMU target for nds32 that we could leverage so that once the toolchain issue is resolved we can update .travis.yml to run tests on it? Thanks! -- Tom

3 9

[U-Boot] [PATCH v2] patman: add option for limiting the Cc list
by Chris Packham 07 Jun '18

07 Jun '18

Many mailing-lists consider a long Cc list a sign of spam and will either drop the message or mark it for moderation. Because patman automatically invokes get_maintainer.pl the Cc list can expand unexpectedly. Allow the user to specify a limit for the Cc list. This limit is applied after removing any known bouncing addresses. By default no limit is applied. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- I've fallen foul of the u-boot ML Cc limit a few times recently. I'm not sure what the actual limit is so I've left patman's default behaviour unlimited. Changes in v2: - make default None to allow limit 0 to suppress the list completely tools/patman/patman.py | 4 +++- tools/patman/series.py | 5 ++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/tools/patman/patman.py b/tools/patman/patman.py index 8d2c78235a7e..e01510df9c0f 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -38,6 +38,8 @@ parser.add_option('-i', '--ignore-errors', action='store_true', parser.add_option('-m', '--no-maintainers', action='store_false', dest='add_maintainers', default=True, help="Don't cc the file maintainers automatically") +parser.add_option('-l', '--limit-cc', dest='limit', type='int', + default=None, help='Limit the cc list to LIMIT entries [default: %default]') parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run', default=False, help="Do a dry run (create but don't email patches)") parser.add_option('-p', '--project', default=project.DetectProject(), @@ -157,7 +159,7 @@ else: cc_file = series.MakeCcFile(options.process_tags, cover_fname, not options.ignore_bad_tags, - options.add_maintainers) + options.add_maintainers, options.limit) # Email the patches out (giving the user time to check / cancel) cmd = '' diff --git a/tools/patman/series.py b/tools/patman/series.py index d526d4ee91d3..2735afaf88fe 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -202,7 +202,7 @@ class Series(dict): print(col.Color(col.RED, str)) def MakeCcFile(self, process_tags, cover_fname, raise_on_error, - add_maintainers): + add_maintainers, limit): """Make a cc file for us to use for per-commit Cc automation Also stores in self._generated_cc to make ShowActions() faster. @@ -215,6 +215,7 @@ class Series(dict): add_maintainers: Either: True/False to call the get_maintainers to CC maintainers List of maintainers to include (for testing) + limit: Limit the length of the Cc list Return: Filename of temp file created """ @@ -238,6 +239,8 @@ class Series(dict): print(col.Color(col.YELLOW, 'Skipping "%s"' % x)) cc = set(cc) - set(settings.bounces) cc = [m.encode('utf-8') if type(m) != str else m for m in cc] + if limit is not None: + cc = cc[:limit] all_ccs += cc print(commit.patch, ', '.join(set(cc)), file=fd) self._generated_cc[commit.patch] = cc -- 2.17.0

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[U-Boot] [PATCH 1/2] dm: pci: make ranges dt property optional
by Christian Gmeiner 06 Jun '18

06 Jun '18

If we use u-boot as coreboot payload with a generic dts without any ranges specified we fail in pci pre_probe and our pci bus is not usable. So convert decode_regions(..) into a void function and do the simple error handling there. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- drivers/pci/pci-uclass.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 49be1ebdd7..416444a230 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -810,7 +810,7 @@ error: return ret; } -static int decode_regions(struct pci_controller *hose, ofnode parent_node, +static void decode_regions(struct pci_controller *hose, ofnode parent_node, ofnode node) { int pci_addr_cells, addr_cells, size_cells; @@ -820,8 +820,11 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, int i; prop = ofnode_get_property(node, "ranges", &len); - if (!prop) - return -EINVAL; + if (!prop) { + debug("%s: Cannot decode regions\n", __func__); + return; + } + pci_addr_cells = ofnode_read_simple_addr_cells(node); addr_cells = ofnode_read_simple_addr_cells(parent_node); size_cells = ofnode_read_simple_size_cells(node); @@ -876,7 +879,7 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, bd_t *bd = gd->bd; if (!bd) - return 0; + return; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { if (bd->bi_dram[i].size) { @@ -901,13 +904,12 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); #endif - return 0; + return; } static int pci_uclass_pre_probe(struct udevice *bus) { struct pci_controller *hose; - int ret; debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name, bus->parent->name); @@ -916,12 +918,7 @@ static int pci_uclass_pre_probe(struct udevice *bus) /* For bridges, use the top-level PCI controller */ if (!device_is_on_pci_bus(bus)) { hose->ctlr = bus; - ret = decode_regions(hose, dev_ofnode(bus->parent), - dev_ofnode(bus)); - if (ret) { - debug("%s: Cannot decode regions\n", __func__); - return ret; - } + decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus)); } else { struct pci_controller *parent_hose; -- 2.17.0

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[U-Boot] [PATCH 1/2] fit: allow fit to call hardware accelerated hash
by Ben Whitten 06 Jun '18

06 Jun '18

Move to calling the abstraction which allows for hardware acceleration. Signed-off-by: Ben Whitten <ben.whitten(a)lairdtech.com> --- common/image-fit.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/common/image-fit.c b/common/image-fit.c index 8c15ed1..01ea864 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1082,19 +1082,25 @@ int fit_set_timestamp(void *fit, int noffset, time_t timestamp) int calculate_hash(const void *data, int data_len, const char *algo, uint8_t *value, int *value_len) { + struct hash_algo *hash_algo; + int ret; + + ret = hash_lookup_algo(algo, &hash_algo); + if (ret) + return ret; + if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) { - *((uint32_t *)value) = crc32_wd(0, data, data_len, - CHUNKSZ_CRC32); - *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value)); - *value_len = 4; + hash_algo->hash_func_ws((unsigned char *)data, data_len, + (unsigned char *)value, hash_algo->chunk_size); + *value_len = hash_algo->digest_size; } else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) { - sha1_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA1); - *value_len = 20; + hash_algo->hash_func_ws((unsigned char *)data, data_len, + (unsigned char *)value, hash_algo->chunk_size); + *value_len = hash_algo->digest_size; } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) { - sha256_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA256); - *value_len = SHA256_SUM_LEN; + hash_algo->hash_func_ws((unsigned char *)data, data_len, + (unsigned char *)value, hash_algo->chunk_size); + *value_len = hash_algo->digest_size; } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) { md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5); *value_len = 16; -- 2.7.4

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