May 2018 - U-Boot

[U-Boot] [PATCH v3 0/5] mtd: nand: mxs_nand: improve ECC support
by Stefan Agner 22 Jun '18

22 Jun '18

From: Stefan Agner <stefan.agner(a)toradex.com> This patchset reworks the drivers ECC calculation to align more with the Linux driver gpmi-nand.c. It aims to implements minimal ECC support as supported by the NAND chip. This is the rebased version after moving MXS NAND to Kconfig. -- Stefan Changes in v3: - Fix indentation - Rebased and removed already applied Kconfig change Changes in v2: - Extend the patchset with "report correct ECC parameters" patch Stefan Agner (5): mtd: nand: mxs_nand: use self init mtd: nand: mxs_nand: allow to enable BBT support mtd: nand: mxs_nand: use structure for BCH geometry mtd: nand: mxs_nand: report correct ECC parameters mtd: nand: mxs_nand: add minimal ECC support drivers/mtd/nand/Kconfig | 9 ++ drivers/mtd/nand/mxs_nand.c | 282 ++++++++++++++++++++++-------------- 2 files changed, 180 insertions(+), 111 deletions(-) -- 2.17.0

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[U-Boot] [PATCH v6 0/7] sunxi: sync H3, H5, A64 DTs from mainline Linux
by Andre Przywara 19 Jun '18

19 Jun '18

This is an updated version of the series which brings the exact mainline Linux device tree files for various Allwinner boards into U-Boot. Apart from using the usually more correct reference DT files, this offers the big benefit of being able to use U-Boot's DT copy for directly passing it to the kernel. This avoids to actually load a .dtb file from somewhere, and allows seamless and automatic UEFI booting, so distribution installer images should just work (TM). This cover the ARMv8 SoCs (H5, A64), but also all boards with the H3, as this is somewhat married to the H5 and can only be updated together. The H3 and H5 DT files have diverged quite a bit, but as U-Boot's own usage of the DT is (yet) quite limited, there should be no regressions. The patches are split to first update the SoC .dtsi file, then the board .dts files in a second patch. They are grouped to handle the A64 first, then the H5 and H3. I put the respective kernel commit IDs in the commit messages. Patch 6 brings in the mainline DT for the SoPine baseboard, for which we didn't have a separate .dts in U-Boot so far. Patch 7 adds a separate .dts file for the Pine64-LTS board, which is virtually identical to the SoPine baseboard, but, due to the SoC being named differently, deserves a separate file. This is based on origin/master (ca70cbabdcd1). Maxime, I kept you Acked-by: from the previous posts, as I literally just updated to the latest Linux master, which went through your review anyway. Hope that's OK for you. Cheers, Andre. Changelog v5 .. v6: - bring back DT update patches - update to Linux v4.17-rc5 Changelog v4 .. v5: - drop Linux DT update patches for now - fix minor checkpatch complaints Changelog v3 .. v4: - remove MMC environment for all Allwinner boards (including 32 bit ones) - keep MMC environment offset to the old values - drop DT adjustments to use fixed MMC regulator Changelog v2 .. v3: 01: added, was on the list before 02: drop redundant H5 line 03-08: unchanged 09-20: added Changelog v1 .. v2: 01, 02, 03: unchanged 04, 05, 06, 07: added Andre Przywara (7): sunxi: DT: A64: update device tree file for Allwinner A64 SoC sunxi: DT: A64: update board .dts files from Linux sunxi: DT: update device tree files for Allwinner H3 and H5 SoCs sunxi: DT: H5: update board .dts files from Linux sunxi: DT: H3: update board .dts files from Linux sunxi: DT: A64: add proper SoPine baseboard device tree sunxi: DT: A64: add Pine64-LTS support arch/arm/dts/Makefile | 4 +- arch/arm/dts/axp803.dtsi | 150 +++++ arch/arm/dts/sun50i-a64-bananapi-m64.dts | 200 +++++- arch/arm/dts/sun50i-a64-nanopi-a64.dts | 111 +++- arch/arm/dts/sun50i-a64-olinuxino.dts | 153 ++++- arch/arm/dts/sun50i-a64-orangepi-win.dts | 135 +++- arch/arm/dts/sun50i-a64-pine64-lts.dts | 13 + arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 59 -- arch/arm/dts/sun50i-a64-pine64-plus.dts | 17 +- arch/arm/dts/sun50i-a64-pine64.dts | 186 +++++- arch/arm/dts/sun50i-a64-sopine-baseboard.dts | 150 +++++ arch/arm/dts/sun50i-a64-sopine.dtsi | 142 ++++ arch/arm/dts/sun50i-a64.dtsi | 303 ++++++++- arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts | 122 +++- arch/arm/dts/sun50i-h5-nanopi-neo2.dts | 91 ++- arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 186 +++++- arch/arm/dts/sun50i-h5-orangepi-prime.dts | 189 +++++- arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts | 64 +- arch/arm/dts/sun50i-h5.dtsi | 36 +- arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 55 +- arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 109 ++- arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts | 78 +++ arch/arm/dts/sun8i-h3-nanopi-m1.dts | 42 ++ arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 28 +- arch/arm/dts/sun8i-h3-nanopi-neo.dts | 17 + arch/arm/dts/sun8i-h3-nanopi.dtsi | 13 +- arch/arm/dts/sun8i-h3-orangepi-2.dts | 92 ++- arch/arm/dts/sun8i-h3-orangepi-lite.dts | 57 +- arch/arm/dts/sun8i-h3-orangepi-one.dts | 94 ++- arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts | 11 +- arch/arm/dts/sun8i-h3-orangepi-pc.dts | 113 +++- arch/arm/dts/sun8i-h3-orangepi-plus.dts | 29 +- arch/arm/dts/sun8i-h3-orangepi-plus2e.dts | 15 +- arch/arm/dts/sun8i-h3.dtsi | 544 ++------------- arch/arm/dts/sunxi-h3-h5.dtsi | 842 ++++++++++++++++++++++++ arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi | 2 - configs/sopine_baseboard_defconfig | 3 +- include/dt-bindings/clock/sun8i-de2.h | 18 + include/dt-bindings/clock/sun8i-r-ccu.h | 59 ++ include/dt-bindings/reset/sun8i-de2.h | 14 + include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++ 41 files changed, 3703 insertions(+), 896 deletions(-) create mode 100644 arch/arm/dts/axp803.dtsi create mode 100644 arch/arm/dts/sun50i-a64-pine64-lts.dts delete mode 100644 arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi create mode 100644 arch/arm/dts/sun50i-a64-sopine-baseboard.dts create mode 100644 arch/arm/dts/sun50i-a64-sopine.dtsi create mode 100644 arch/arm/dts/sunxi-h3-h5.dtsi create mode 100644 include/dt-bindings/clock/sun8i-de2.h create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-de2.h create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h -- 2.14.1

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[U-Boot] [PATCH] ARM: mxs: let boards override entire dram parameter table
by Mans Rullgard 18 Jun '18

18 Jun '18

If many values differ from the defaults, overriding the full table is simpler and more space efficient than tweaking it through mxs_adjust_memory_params(). Signed-off-by: Mans Rullgard <mans(a)mansr.com> --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index a744e5d4990a..a19cfc50449f 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -16,7 +16,7 @@ #include "mxs_init.h" -static uint32_t dram_vals[] = { +__weak uint32_t mxs_dram_vals[] = { /* * i.MX28 DDR2 at 200MHz */ @@ -101,11 +101,11 @@ static void initialize_dram_values(void) int i; debug("SPL: Setting mx28 board specific SDRAM parameters\n"); - mxs_adjust_memory_params(dram_vals); + mxs_adjust_memory_params(mxs_dram_vals); debug("SPL: Applying SDRAM parameters\n"); - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) + writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i)); } #else static void initialize_dram_values(void) @@ -113,7 +113,7 @@ static void initialize_dram_values(void) int i; debug("SPL: Setting mx23 board specific SDRAM parameters\n"); - mxs_adjust_memory_params(dram_vals); + mxs_adjust_memory_params(mxs_dram_vals); /* * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as @@ -125,10 +125,10 @@ static void initialize_dram_values(void) * So skip the initialization of these HW_DRAM_CTL registers. */ debug("SPL: Applying SDRAM parameters\n"); - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { + for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) { if (i == 8 || i == 27 || i == 28 || i == 35) continue; - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i)); } /* -- 2.17.0

2 1

[U-Boot] [PATCH] imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platforms
by Fabio Estevam 18 Jun '18

18 Jun '18

From: Ye Li <ye.li(a)nxp.com> According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed". ROM sets this bit in normal boot flow, but when in serial download mode, it is not set. Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. Signed-off-by: Ye Li <ye.li(a)nxp.com> [fabio: adapted to U-Boot mainline codebase and make checkpatch happy] Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- arch/arm/mach-imx/cache.c | 42 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx7/soc.c | 7 ------- 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index c5279a7..86205cf 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -10,6 +10,34 @@ #include <asm/io.h> #include <asm/mach-imx/sys_proto.h> +static void enable_ca7_smp(void) +{ + u32 val; + + /* Read MIDR */ + asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val)); + val = (val >> 4); + val &= 0xf; + + /* Only set the SMP for Cortex A7 */ + if (val == 0x7) { + /* Read auxiliary control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); + + if (val & (1 << 6)) + return; + + /* Enable SMP */ + val |= (1 << 6); + + /* Write auxiliary control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val)); + + DSB; + ISB; + } +} + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { @@ -21,6 +49,9 @@ void enable_caches(void) /* Avoid random hang when download by usb */ invalidate_dcache_all(); + /* Set ACTLR.SMP bit for Cortex-A7 */ + enable_ca7_smp(); + /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); @@ -32,6 +63,17 @@ void enable_caches(void) IRAM_SIZE, option); } +#else +void enable_caches(void) +{ + /* + * Set ACTLR.SMP bit for Cortex-A7, even if the caches are + * disabled by u-boot + */ + enable_ca7_smp(); + + puts("WARNING: Caches not enabled\n"); +} #endif #ifndef CONFIG_SYS_L2CACHE_OFF diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 3ceeeff..83bcd2d 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -281,13 +281,6 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { -#if !defined CONFIG_SPL_BUILD - /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #1 << 6\n" - "mcr p15, 0, r0, c1, c0, 1\n"); -#endif /* clock configuration. */ clock_init(); -- 2.7.4

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[U-Boot] [PATCH v4 00/16] efi: Enable basic sandbox support for EFI loader
by Simon Glass 15 Jun '18

15 Jun '18

A limitation of the EFI loader at present is that it does not build with sandbox. This makes it hard to write tests, since sandbox is used for most testing in U-Boot. This series enables the EFI loader feature. It allows sandbox to build and run a trivial function which calls the EFI API to output a message. This series is at u-boot-dm/efi-working Changes in v4: - Fix up the sizeof() operations on jmp_buf - Move the fix to query_console_serial() - Rebase to master - Remove code already applied - Update SPDX tags - Update subject Changes in v3: - Add comments on aligment - Add new patch to init the 'rows' and 'cols' variables - Add new patch to rename bootefi_test_finish() to bootefi_run_finish() - Add new patch to split out test init/uninit into functions - Add patch to create a function to set up for running EFI code - Drop incorrect map_sysmem() in write_smbios_table() - Init the 'rows' and 'cols' vars to avoid a compiler error (gcc 4.8.4) - Rebase to master - Return error value of efi_allocate_pages() - Update function comment for write_smbios_table() Changes in v2: - Rebase to master - Update return type of efi_smbios_register() to efi_status_t - Update to use mapmem instead of a cast - Use return value of efi_install_configuration_table Simon Glass (16): efi: Init the 'rows' and 'cols' variables efi: Update some comments related to smbios tables efi: sandbox: Adjust memory usage for sandbox sandbox: smbios: Update to support sandbox sandbox: Add a setjmp() implementation efi: sandbox: Add required linker sections efi: sandbox: Add distroboot support Define board_quiesce_devices() in a shared location Add a comment for board_quiesce_devices() efi: sandbox: Add relocation constants efi: Add a comment about duplicated ELF constants efi: sandbox: Enable EFI loader builder for sandbox efi: Split out test init/uninit into functions efi: sandbox: Add a simple 'bootefi test' command efi: Create a function to set up for running EFI code efi: Rename bootefi_test_finish() to bootefi_run_finish() arch/arm/include/asm/u-boot-arm.h | 1 - arch/sandbox/cpu/cpu.c | 13 +++ arch/sandbox/cpu/os.c | 23 +++++ arch/sandbox/cpu/u-boot.lds | 29 ++++++ arch/sandbox/include/asm/setjmp.h | 30 ++++++ arch/sandbox/lib/Makefile | 2 +- arch/sandbox/lib/sections.c | 12 +++ arch/x86/include/asm/u-boot-x86.h | 1 - arch/x86/lib/bootm.c | 4 - cmd/bootefi.c | 158 +++++++++++++++++++++--------- common/bootm.c | 4 + include/bootm.h | 8 ++ include/config_distro_bootcmd.h | 2 +- include/efi_loader.h | 10 ++ include/os.h | 21 ++++ include/smbios.h | 5 +- lib/efi_loader/Kconfig | 12 ++- lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_console.c | 5 +- lib/efi_loader/efi_memory.c | 31 +++--- lib/efi_loader/efi_runtime.c | 7 ++ lib/efi_loader/efi_smbios.c | 7 +- lib/efi_loader/efi_test.c | 16 +++ lib/smbios.c | 32 ++++-- 24 files changed, 351 insertions(+), 83 deletions(-) create mode 100644 arch/sandbox/include/asm/setjmp.h create mode 100644 arch/sandbox/lib/sections.c create mode 100644 lib/efi_loader/efi_test.c -- 2.17.0.441.gb46fe60e1d-goog

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[U-Boot] [PATCH v2 1/2] mvebu: neta: align DMA buffers
by Baruch Siach 13 Jun '18

13 Jun '18

From: Jon Nettleton <jon(a)solid-run.com> This makes sure the DMA buffers are properly aligned for the hardware. Reviewed-by: Stefan Roese <sr(a)denx.de> Signed-off-by: Jon Nettleton <jon(a)solid-run.com> Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- v2: * Change BUG_ON to WARN_ON (Stefan Roese) * Add Stefan's review tag --- drivers/net/mvneta.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 7036b517b445..45e5eda95522 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -1025,6 +1025,8 @@ static int mvneta_rxq_init(struct mvneta_port *pp, if (rxq->descs == NULL) return -ENOMEM; + WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN)); + rxq->last_desc = rxq->size - 1; /* Set Rx descriptors queue starting address */ @@ -1061,6 +1063,8 @@ static int mvneta_txq_init(struct mvneta_port *pp, if (txq->descs == NULL) return -ENOMEM; + WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN)); + txq->last_desc = txq->size - 1; /* Set maximum bandwidth for enabled TXQs */ @@ -1694,18 +1698,20 @@ static int mvneta_probe(struct udevice *dev) * be active. Make this area DMA safe by disabling the D-cache */ if (!buffer_loc.tx_descs) { + u32 size; + /* Align buffer area for descs and rx_buffers to 1MiB */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, DCACHE_OFF); buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; + size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc), + ARCH_DMA_MINALIGN); buffer_loc.rx_descs = (struct mvneta_rx_desc *) - ((phys_addr_t)bd_space + - MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc)); - buffer_loc.rx_buffers = (phys_addr_t) - (bd_space + - MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) + - MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); + ((phys_addr_t)bd_space + size); + size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc), + ARCH_DMA_MINALIGN); + buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size); } pp->base = (void __iomem *)pdata->iobase; -- 2.17.0

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[U-Boot] [PATCH] net: add Socionext AVE ethernet driver support
by Kunihiko Hayashi 13 Jun '18

13 Jun '18

Add driver for Socionext AVE ethernet controller that includes MAC and MDIO bus supporting RGMII/RMII modes. The driver behaves the ethernet driver model (DM_ETH) with devicetree. This patch requires the internal phy definition [1]. [1] http://patchwork.ozlabs.org/patch/915965/ Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko(a)socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/net/Kconfig | 10 + drivers/net/Makefile | 1 + drivers/net/sni_ave.c | 995 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1006 insertions(+) create mode 100644 drivers/net/sni_ave.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f2cc75f..e88f056 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -362,6 +362,16 @@ config MPC8XX_FEC This driver implements support for the Fast Ethernet Controller on MPC8XX +config SNI_AVE + bool "Socionext AVE Ethernet support" + depends on DM_ETH && ARCH_UNIPHIER + select PHYLIB + select SYSCON + select REGMAP + help + This driver implements support for the Socionext AVE Ethernet + controller, as found on the Socionext UniPhier family. + config ETHER_ON_FEC1 bool "FEC1" depends on MPC8XX_FEC diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 851f82f..5b40ccc 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -71,3 +71,4 @@ obj-$(CONFIG_VSC9953) += vsc9953.o obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ +obj-$(CONFIG_SNI_AVE) += sni_ave.o diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c new file mode 100644 index 0000000..ba51ea5 --- /dev/null +++ b/drivers/net/sni_ave.c @@ -0,0 +1,995 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * sni_ave.c - Socionext UniPhier AVE ethernet driver + * Copyright 2016-2018 Socionext inc. + */ + +#include <clk.h> +#include <dm.h> +#include <fdt_support.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <miiphy.h> +#include <net.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> + +#define AVE_GRST_DELAY_MSEC 40 +#define AVE_MIN_XMITSIZE 60 +#define AVE_SEND_TIMEOUT_COUNT 1000 +#define AVE_MDIO_TIMEOUT_USEC 10000 +#define AVE_HALT_TIMEOUT_USEC 10000 + +/* General Register Group */ +#define AVE_IDR 0x000 /* ID */ +#define AVE_VR 0x004 /* Version */ +#define AVE_GRR 0x008 /* Global Reset */ +#define AVE_CFGR 0x00c /* Configuration */ + +/* Interrupt Register Group */ +#define AVE_GIMR 0x100 /* Global Interrupt Mask */ +#define AVE_GISR 0x104 /* Global Interrupt Status */ + +/* MAC Register Group */ +#define AVE_TXCR 0x200 /* TX Setup */ +#define AVE_RXCR 0x204 /* RX Setup */ +#define AVE_RXMAC1R 0x208 /* MAC address (lower) */ +#define AVE_RXMAC2R 0x20c /* MAC address (upper) */ +#define AVE_MDIOCTR 0x214 /* MDIO Control */ +#define AVE_MDIOAR 0x218 /* MDIO Address */ +#define AVE_MDIOWDR 0x21c /* MDIO Data */ +#define AVE_MDIOSR 0x220 /* MDIO Status */ +#define AVE_MDIORDR 0x224 /* MDIO Rd Data */ + +/* Descriptor Control Register Group */ +#define AVE_DESCC 0x300 /* Descriptor Control */ +#define AVE_TXDC 0x304 /* TX Descriptor Configuration */ +#define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */ +#define AVE_IIRQC 0x34c /* Interval IRQ Control */ + +/* 64bit descriptor memory */ +#define AVE_DESC_SIZE_64 12 /* Descriptor Size */ +#define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */ +#define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */ + +/* 32bit descriptor memory */ +#define AVE_DESC_SIZE_32 8 /* Descriptor Size */ +#define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */ +#define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */ + +/* RMII Bridge Register Group */ +#define AVE_RSTCTRL 0x8028 /* Reset control */ +#define AVE_RSTCTRL_RMIIRST BIT(16) +#define AVE_LINKSEL 0x8034 /* Link speed setting */ +#define AVE_LINKSEL_100M BIT(0) + +/* AVE_GRR */ +#define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ +#define AVE_GRR_GRST BIT(0) /* Reset all MAC */ + +/* AVE_CFGR */ +#define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ + +/* AVE_GISR (common with GIMR) */ +#define AVE_GIMR_CLR 0 +#define AVE_GISR_CLR GENMASK(31, 0) + +/* AVE_TXCR */ +#define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ +#define AVE_TXCR_TXSPD_1G BIT(17) +#define AVE_TXCR_TXSPD_100 BIT(16) + +/* AVE_RXCR */ +#define AVE_RXCR_RXEN BIT(30) /* Rx enable */ +#define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ +#define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ + +/* AVE_MDIOCTR */ +#define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ +#define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ + +/* AVE_MDIOSR */ +#define AVE_MDIOSR_STS BIT(0) /* access status */ + +/* AVE_DESCC */ +#define AVE_DESCC_RXDSTPSTS BIT(20) +#define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ +#define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */ +#define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ + +/* AVE_TXDC/RXDC */ +#define AVE_DESC_SIZE(priv, num) \ + ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \ + AVE_DESC_SIZE_32)) + +/* Command status for descriptor */ +#define AVE_STS_OWN BIT(31) /* Descriptor ownership */ +#define AVE_STS_OK BIT(27) /* Normal transmit */ +#define AVE_STS_1ST BIT(26) /* Head of buffer chain */ +#define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ +#define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0) +#define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0) + +#define AVE_DESC_OFS_CMDSTS 0 +#define AVE_DESC_OFS_ADDRL 4 +#define AVE_DESC_OFS_ADDRU 8 + +/* Parameter for ethernet frame */ +#define AVE_RXCR_MTU 1518 + +/* SG */ +#define SG_ETPINMODE 0x540 +#define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ +#define SG_ETPINMODE_RMII(ins) BIT(ins) + +#define AVE_MAX_CLKS 4 +#define AVE_MAX_RSTS 2 + +enum desc_id { + AVE_DESCID_TX, + AVE_DESCID_RX, +}; + +struct ave_private { + phys_addr_t iobase; + unsigned int nclks; + struct clk clk[AVE_MAX_CLKS]; + unsigned int nrsts; + struct reset_ctl rst[AVE_MAX_RSTS]; + struct regmap *regmap; + unsigned int regmap_arg; + + struct mii_dev *bus; + struct phy_device *phydev; + int phy_mode; + int max_speed; + + int rx_pos; + int rx_siz; + int rx_off; + int tx_num; + + u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN]; + void *tx_adj_buf; + + const struct ave_soc_data *data; +}; + +struct ave_soc_data { + bool is_desc_64bit; + const char *clock_names[AVE_MAX_CLKS]; + const char *reset_names[AVE_MAX_RSTS]; + int (*get_pinmode)(struct ave_private *priv); +}; + +static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry, + int offset) +{ + int desc_size; + u32 addr; + + if (priv->data->is_desc_64bit) { + desc_size = AVE_DESC_SIZE_64; + addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; + } else { + desc_size = AVE_DESC_SIZE_32; + addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; + } + + addr += entry * desc_size + offset; + + return readl(priv->iobase + addr); +} + +static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id, + int entry) +{ + return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS); +} + +static void ave_desc_write(struct ave_private *priv, enum desc_id id, + int entry, int offset, u32 val) +{ + int desc_size; + u32 addr; + + if (priv->data->is_desc_64bit) { + desc_size = AVE_DESC_SIZE_64; + addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; + } else { + desc_size = AVE_DESC_SIZE_32; + addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; + } + + addr += entry * desc_size + offset; + writel(val, priv->iobase + addr); +} + +static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id, + int entry, u32 val) +{ + ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val); +} + +static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id, + int entry, uintptr_t paddr) +{ + ave_desc_write(priv, id, entry, + AVE_DESC_OFS_ADDRL, lower_32_bits(paddr)); + if (priv->data->is_desc_64bit) + ave_desc_write(priv, id, entry, + AVE_DESC_OFS_ADDRU, upper_32_bits(paddr)); +} + +static void ave_cache_invalidate(uintptr_t vaddr, int len) +{ + invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), + roundup(vaddr + len, ARCH_DMA_MINALIGN)); +} + +static void ave_cache_flush(uintptr_t vaddr, int len) +{ + flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), + roundup(vaddr + len, ARCH_DMA_MINALIGN)); +} + +static int ave_mdiobus_read(struct mii_dev *bus, + int phyid, int devad, int regnum) +{ + struct ave_private *priv = bus->priv; + u32 mdioctl, mdiosr; + int ret; + + /* write address */ + writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); + + /* read request */ + mdioctl = readl(priv->iobase + AVE_MDIOCTR); + writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR); + + ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, + !(mdiosr & AVE_MDIOSR_STS), + AVE_MDIO_TIMEOUT_USEC); + if (ret) { + pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n", + priv->phydev->dev->name, phyid, regnum); + return ret; + } + + return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0); +} + +static int ave_mdiobus_write(struct mii_dev *bus, + int phyid, int devad, int regnum, u16 val) +{ + struct ave_private *priv = bus->priv; + u32 mdioctl, mdiosr; + int ret; + + /* write address */ + writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); + + /* write data */ + writel(val, priv->iobase + AVE_MDIOWDR); + + /* write request */ + mdioctl = readl(priv->iobase + AVE_MDIOCTR); + writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ, + priv->iobase + AVE_MDIOCTR); + + ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, + !(mdiosr & AVE_MDIOSR_STS), + AVE_MDIO_TIMEOUT_USEC); + if (ret) + pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n", + priv->phydev->dev->name, phyid, regnum); + + return ret; +} + +static int ave_adjust_link(struct ave_private *priv) +{ + struct phy_device *phydev = priv->phydev; + struct eth_pdata *pdata = dev_get_platdata(phydev->dev); + u32 val, txcr, rxcr, rxcr_org; + u16 rmt_adv = 0, lcl_adv = 0; + u8 cap; + + /* set RGMII speed */ + val = readl(priv->iobase + AVE_TXCR); + val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); + + if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) + val |= AVE_TXCR_TXSPD_1G; + else if (phydev->speed == SPEED_100) + val |= AVE_TXCR_TXSPD_100; + + writel(val, priv->iobase + AVE_TXCR); + + /* set RMII speed (100M/10M only) */ + if (!phy_interface_is_rgmii(phydev)) { + val = readl(priv->iobase + AVE_LINKSEL); + if (phydev->speed == SPEED_10) + val &= ~AVE_LINKSEL_100M; + else + val |= AVE_LINKSEL_100M; + writel(val, priv->iobase + AVE_LINKSEL); + } + + /* check current RXCR/TXCR */ + rxcr = readl(priv->iobase + AVE_RXCR); + txcr = readl(priv->iobase + AVE_TXCR); + rxcr_org = rxcr; + + if (phydev->duplex) { + rxcr |= AVE_RXCR_FDUPEN; + + if (phydev->pause) + rmt_adv |= LPA_PAUSE_CAP; + if (phydev->asym_pause) + rmt_adv |= LPA_PAUSE_ASYM; + if (phydev->advertising & ADVERTISED_Pause) + lcl_adv |= ADVERTISE_PAUSE_CAP; + if (phydev->advertising & ADVERTISED_Asym_Pause) + lcl_adv |= ADVERTISE_PAUSE_ASYM; + + cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); + if (cap & FLOW_CTRL_TX) + txcr |= AVE_TXCR_FLOCTR; + else + txcr &= ~AVE_TXCR_FLOCTR; + if (cap & FLOW_CTRL_RX) + rxcr |= AVE_RXCR_FLOCTR; + else + rxcr &= ~AVE_RXCR_FLOCTR; + } else { + rxcr &= ~AVE_RXCR_FDUPEN; + rxcr &= ~AVE_RXCR_FLOCTR; + txcr &= ~AVE_TXCR_FLOCTR; + } + + if (rxcr_org != rxcr) { + /* disable Rx mac */ + writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR); + /* change and enable TX/Rx mac */ + writel(txcr, priv->iobase + AVE_TXCR); + writel(rxcr, priv->iobase + AVE_RXCR); + } + + pr_notice("%s: phy:%s speed:%d mac:%pM\n", + phydev->dev->name, phydev->drv->name, phydev->speed, + pdata->enetaddr); + + return phydev->link; +} + +static int ave_mdiobus_init(struct ave_private *priv, const char *name) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) + return -ENOMEM; + + bus->read = ave_mdiobus_read; + bus->write = ave_mdiobus_write; + snprintf(bus->name, sizeof(bus->name), "%s", name); + bus->priv = priv; + + return mdio_register(bus); +} + +static int ave_phy_init(struct ave_private *priv, void *dev) +{ + struct phy_device *phydev; + int mask = GENMASK(31, 0), ret; + + phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + phydev->supported &= PHY_GBIT_FEATURES; + if (priv->max_speed) { + ret = phy_set_supported(phydev, priv->max_speed); + if (ret) + return ret; + } + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +static void ave_stop(struct udevice *dev) +{ + struct ave_private *priv = dev_get_priv(dev); + u32 val; + int ret; + + val = readl(priv->iobase + AVE_GRR); + if (val) + return; + + val = readl(priv->iobase + AVE_RXCR); + val &= ~AVE_RXCR_RXEN; + writel(val, priv->iobase + AVE_RXCR); + + writel(0, priv->iobase + AVE_DESCC); + ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val, + AVE_HALT_TIMEOUT_USEC); + if (ret) + pr_warn("%s: halt timeout\n", priv->phydev->dev->name); + + writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); + + phy_shutdown(priv->phydev); +} + +static void ave_reset(struct ave_private *priv) +{ + u32 val; + + /* reset RMII register */ + val = readl(priv->iobase + AVE_RSTCTRL); + val &= ~AVE_RSTCTRL_RMIIRST; + writel(val, priv->iobase + AVE_RSTCTRL); + + /* assert reset */ + writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR); + mdelay(AVE_GRST_DELAY_MSEC); + + /* 1st, negate PHY reset only */ + writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); + mdelay(AVE_GRST_DELAY_MSEC); + + /* negate reset */ + writel(0, priv->iobase + AVE_GRR); + mdelay(AVE_GRST_DELAY_MSEC); + + /* negate RMII register */ + val = readl(priv->iobase + AVE_RSTCTRL); + val |= AVE_RSTCTRL_RMIIRST; + writel(val, priv->iobase + AVE_RSTCTRL); +} + +static int ave_start(struct udevice *dev) +{ + struct ave_private *priv = dev_get_priv(dev); + uintptr_t paddr; + u32 val; + int i; + + ave_reset(priv); + + priv->rx_pos = 0; + priv->rx_off = 2; /* RX data has 2byte offsets */ + priv->tx_num = 0; + priv->tx_adj_buf = + (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0], + PKTALIGN); + priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off); + + val = 0; + if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII) + val |= AVE_CFGR_MII; + writel(val, priv->iobase + AVE_CFGR); + + /* use one descriptor for Tx */ + writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC); + ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0); + ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0); + + /* use PKTBUFSRX descriptors for Rx */ + writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC); + for (i = 0; i < PKTBUFSRX; i++) { + paddr = (uintptr_t)net_rx_packets[i]; + ave_cache_flush(paddr, priv->rx_siz + priv->rx_off); + ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr); + ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz); + } + + writel(AVE_GISR_CLR, priv->iobase + AVE_GISR); + writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR); + + writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU, + priv->iobase + AVE_RXCR); + writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC); + + phy_startup(priv->phydev); + ave_adjust_link(priv); + + return 0; +} + +static int ave_write_hwaddr(struct udevice *dev) +{ + struct ave_private *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + u8 *mac = pdata->enetaddr; + + writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, + priv->iobase + AVE_RXMAC1R); + writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R); + + return 0; +} + +static int ave_send(struct udevice *dev, void *packet, int length) +{ + struct ave_private *priv = dev_get_priv(dev); + u32 val; + void *ptr = packet; + int count; + + /* adjust alignment for descriptor */ + if ((uintptr_t)ptr & 0x3) { + memcpy(priv->tx_adj_buf, (const void *)ptr, length); + ptr = priv->tx_adj_buf; + } + + /* padding for minimum length */ + if (length < AVE_MIN_XMITSIZE) { + memset(ptr + length, 0, AVE_MIN_XMITSIZE - length); + length = AVE_MIN_XMITSIZE; + } + + /* check ownership and wait for previous xmit done */ + count = AVE_SEND_TIMEOUT_COUNT; + do { + val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); + } while ((val & AVE_STS_OWN) && --count); + if (!count) + return -ETIMEDOUT; + + ave_cache_flush((uintptr_t)ptr, length); + ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr); + + val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST | + (length & AVE_STS_PKTLEN_TX_MASK); + ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val); + priv->tx_num++; + + count = AVE_SEND_TIMEOUT_COUNT; + do { + val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); + } while ((val & AVE_STS_OWN) && --count); + if (!count) + return -ETIMEDOUT; + + if (!(val & AVE_STS_OK)) + pr_warn("%s: bad send packet status:%08x\n", + priv->phydev->dev->name, le32_to_cpu(val)); + + return 0; +} + +static int ave_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct ave_private *priv = dev_get_priv(dev); + uchar *ptr; + int length = 0; + u32 cmdsts; + + while (1) { + cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX, + priv->rx_pos); + if (!(cmdsts & AVE_STS_OWN)) + /* hardware ownership, no received packets */ + return -EAGAIN; + + ptr = net_rx_packets[priv->rx_pos] + priv->rx_off; + if (cmdsts & AVE_STS_OK) + break; + + pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n", + priv->phydev->dev->name, priv->rx_pos, + le32_to_cpu(cmdsts), ptr); + } + + length = cmdsts & AVE_STS_PKTLEN_RX_MASK; + + /* invalidate after DMA is done */ + ave_cache_invalidate((uintptr_t)ptr, length); + *packetp = ptr; + + return length; +} + +static int ave_free_packet(struct udevice *dev, uchar *packet, int length) +{ + struct ave_private *priv = dev_get_priv(dev); + + ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos], + priv->rx_siz + priv->rx_off); + + ave_desc_write_cmdsts(priv, AVE_DESCID_RX, + priv->rx_pos, priv->rx_siz); + + if (++priv->rx_pos >= PKTBUFSRX) + priv->rx_pos = 0; + + return 0; +} + +static int ave_pro4_get_pinmode(struct ave_private *priv) +{ + u32 reg, mask, val = 0; + + if (priv->regmap_arg > 0) + return -EINVAL; + + mask = SG_ETPINMODE_RMII(0); + + switch (priv->phy_mode) { + case PHY_INTERFACE_MODE_RMII: + val = SG_ETPINMODE_RMII(0); + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + break; + default: + return -EINVAL; + } + + regmap_read(priv->regmap, SG_ETPINMODE, &reg); + reg &= ~mask; + reg |= val; + regmap_write(priv->regmap, SG_ETPINMODE, reg); + + return 0; +} + +static int ave_ld11_get_pinmode(struct ave_private *priv) +{ + u32 reg, mask, val = 0; + + if (priv->regmap_arg > 0) + return -EINVAL; + + mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); + + switch (priv->phy_mode) { + case PHY_INTERFACE_MODE_INTERNAL: + break; + case PHY_INTERFACE_MODE_RMII: + val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); + break; + default: + return -EINVAL; + } + + regmap_read(priv->regmap, SG_ETPINMODE, &reg); + reg &= ~mask; + reg |= val; + regmap_write(priv->regmap, SG_ETPINMODE, reg); + + return 0; +} + +static int ave_ld20_get_pinmode(struct ave_private *priv) +{ + u32 reg, mask, val = 0; + + if (priv->regmap_arg > 0) + return -EINVAL; + + mask = SG_ETPINMODE_RMII(0); + + switch (priv->phy_mode) { + case PHY_INTERFACE_MODE_RMII: + val = SG_ETPINMODE_RMII(0); + break; + case PHY_INTERFACE_MODE_RGMII: + break; + default: + return -EINVAL; + } + + regmap_read(priv->regmap, SG_ETPINMODE, &reg); + reg &= ~mask; + reg |= val; + regmap_write(priv->regmap, SG_ETPINMODE, reg); + + return 0; +} + +static int ave_pxs3_get_pinmode(struct ave_private *priv) +{ + u32 reg, mask, val = 0; + + if (priv->regmap_arg > 1) + return -EINVAL; + + mask = SG_ETPINMODE_RMII(priv->regmap_arg); + + switch (priv->phy_mode) { + case PHY_INTERFACE_MODE_RMII: + val = SG_ETPINMODE_RMII(priv->regmap_arg); + break; + case PHY_INTERFACE_MODE_RGMII: + break; + default: + return -EINVAL; + } + + regmap_read(priv->regmap, SG_ETPINMODE, &reg); + reg &= ~mask; + reg |= val; + regmap_write(priv->regmap, SG_ETPINMODE, reg); + + return 0; +} + +static int ave_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ave_private *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + const char *phy_mode; + const u32 *valp; + int ret, nc, nr; + const char *name; + + priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); + if (!priv->data) + return -EINVAL; + + pdata->iobase = devfdt_get_addr(dev); + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", + NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); + return -EINVAL; + } + + pdata->max_speed = 0; + valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", + NULL); + if (valp) + pdata->max_speed = fdt32_to_cpu(*valp); + + for (nc = 0; nc < AVE_MAX_CLKS; nc++) { + name = priv->data->clock_names[nc]; + if (!name) + break; + ret = clk_get_by_name(dev, name, &priv->clk[nc]); + if (ret) { + dev_err(dev, "Failed to get clocks property: %d\n", + ret); + goto out_clk_free; + } + priv->nclks++; + } + + for (nr = 0; nr < AVE_MAX_RSTS; nr++) { + name = priv->data->reset_names[nr]; + if (!name) + break; + ret = reset_get_by_name(dev, name, &priv->rst[nr]); + if (ret) { + dev_err(dev, "Failed to get resets property: %d\n", + ret); + goto out_reset_free; + } + priv->nrsts++; + } + + ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode", + NULL, 1, 0, &args); + if (ret) { + dev_err(dev, "Failed to get syscon-phy-mode property: %d\n", + ret); + goto out_reset_free; + } + + priv->regmap = syscon_node_to_regmap(args.node); + if (IS_ERR(priv->regmap)) { + ret = PTR_ERR(priv->regmap); + dev_err(dev, "can't get syscon: %d\n", ret); + goto out_reset_free; + } + + if (args.args_count != 1) { + ret = -EINVAL; + dev_err(dev, "Invalid argument of syscon-phy-mode\n"); + goto out_reset_free; + } + + priv->regmap_arg = args.args[0]; + + return 0; + +out_reset_free: + while (--nr >= 0) + reset_free(&priv->rst[nr]); +out_clk_free: + while (--nc >= 0) + clk_free(&priv->clk[nc]); + + return ret; +} + +static int ave_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ave_private *priv = dev_get_priv(dev); + int ret, nc, nr; + + priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); + if (!priv->data) + return -EINVAL; + + priv->iobase = pdata->iobase; + priv->phy_mode = pdata->phy_interface; + priv->max_speed = pdata->max_speed; + + ret = priv->data->get_pinmode(priv); + if (ret) { + dev_err(dev, "Invalid phy-mode\n"); + return -EINVAL; + } + + for (nc = 0; nc < priv->nclks; nc++) { + ret = clk_enable(&priv->clk[nc]); + if (ret) { + dev_err(dev, "Failed to enable clk: %d\n", ret); + goto out_clk_release; + } + } + + for (nr = 0; nr < priv->nrsts; nr++) { + ret = reset_deassert(&priv->rst[nr]); + if (ret) { + dev_err(dev, "Failed to deassert reset: %d\n", ret); + goto out_reset_release; + } + } + + ave_reset(priv); + + ret = ave_mdiobus_init(priv, dev->name); + if (ret) { + dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); + goto out_reset_release; + } + + priv->bus = miiphy_get_dev_by_name(dev->name); + + ret = ave_phy_init(priv, dev); + if (ret) { + dev_err(dev, "Failed to initialize phy: %d\n", ret); + goto out_mdiobus_release; + } + + return 0; + +out_mdiobus_release: + mdio_unregister(priv->bus); + mdio_free(priv->bus); +out_reset_release: + reset_release_all(priv->rst, nr); +out_clk_release: + clk_release_all(priv->clk, nc); + + return ret; +} + +static int ave_remove(struct udevice *dev) +{ + struct ave_private *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + reset_release_all(priv->rst, priv->nrsts); + clk_release_all(priv->clk, priv->nclks); + + return 0; +} + +static const struct eth_ops ave_ops = { + .start = ave_start, + .stop = ave_stop, + .send = ave_send, + .recv = ave_recv, + .free_pkt = ave_free_packet, + .write_hwaddr = ave_write_hwaddr, +}; + +static const struct ave_soc_data ave_pro4_data = { + .is_desc_64bit = false, + .clock_names = { + "gio", "ether", "ether-gb", "ether-phy", + }, + .reset_names = { + "gio", "ether", + }, + .get_pinmode = ave_pro4_get_pinmode, +}; + +static const struct ave_soc_data ave_pxs2_data = { + .is_desc_64bit = false, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, + .get_pinmode = ave_pro4_get_pinmode, +}; + +static const struct ave_soc_data ave_ld11_data = { + .is_desc_64bit = false, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, + .get_pinmode = ave_ld11_get_pinmode, +}; + +static const struct ave_soc_data ave_ld20_data = { + .is_desc_64bit = true, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, + .get_pinmode = ave_ld20_get_pinmode, +}; + +static const struct ave_soc_data ave_pxs3_data = { + .is_desc_64bit = false, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, + .get_pinmode = ave_pxs3_get_pinmode, +}; + +static const struct udevice_id ave_ids[] = { + { + .compatible = "socionext,uniphier-pro4-ave4", + .data = (ulong)&ave_pro4_data, + }, + { + .compatible = "socionext,uniphier-pxs2-ave4", + .data = (ulong)&ave_pxs2_data, + }, + { + .compatible = "socionext,uniphier-ld11-ave4", + .data = (ulong)&ave_ld11_data, + }, + { + .compatible = "socionext,uniphier-ld20-ave4", + .data = (ulong)&ave_ld20_data, + }, + { + .compatible = "socionext,uniphier-pxs3-ave4", + .data = (ulong)&ave_pxs3_data, + }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(ave) = { + .name = "ave", + .id = UCLASS_ETH, + .of_match = ave_ids, + .probe = ave_probe, + .remove = ave_remove, + .ofdata_to_platdata = ave_ofdata_to_platdata, + .ops = &ave_ops, + .priv_auto_alloc_size = sizeof(struct ave_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; -- 2.7.4

3 3

[U-Boot] [PATCH] drivers/net/vsc9953: Initialize action RAM in VCAP complex
by radu-andrei.bulie＠nxp.com 13 Jun '18

13 Jun '18

From: Radu Bulie <radu-andrei.bulie(a)nxp.com> VCAP tables must be initialized even if no advanced classification is used. If no initialization is performed, then ECC error will be observed by the user when the first packet enters the l2switch. The error is marked in MPIC_EISR0 -bit 29 which means - Internal RAM multi-bit ECC error. This patch fixes the aforementioned ECC error by performing the initialization of VCAP tables. Signed-off-by: Radu Bulie <radu-andrei.bulie(a)nxp.com> --- drivers/net/vsc9953.c | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/vsc9953.h | 58 ++++++++++++++++++++++ 2 files changed, 192 insertions(+) diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 2388438..f90181d 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -2469,6 +2469,139 @@ void vsc9953_default_configuration(void) debug("VSC9953: failed to set default aggregation code mode\n"); } +static void vcap_entry2cache_init(u32 target, u32 entry_words) +{ + int i; + + for (i = 0; i < entry_words; i++) { + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_ENTRY_DAT(target, i)), 0x00); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_MASK_DAT(target, i)), 0xFF); + } + + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_TG_DAT(target)), 0x00); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_MV_CFG(target)), + VSC9953_VCAP_CFG_MV_CFG_SIZE(entry_words)); +} + +static void vcap_action2cache_init(u32 target, u32 action_words, + u32 counter_words) +{ + int i; + + for (i = 0; i < action_words; i++) + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_ACTION_DAT(target, i)), 0x00); + + for (i = 0; i < counter_words; i++) + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_CNT_DAT(target, i)), 0x00); +} + +static int vcap_cmd(u32 target, u16 ix, int cmd, int sel, int entry_count) +{ + u32 tgt = target; + u32 value = (VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(cmd) | + VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(ix) | + VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT); + + if ((sel & TCAM_SEL_ENTRY) && ix >= entry_count) + return CMD_RET_FAILURE; + + if (!(sel & TCAM_SEL_ENTRY)) + value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS; + + if (!(sel & TCAM_SEL_ACTION)) + value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS; + + if (!(sel & TCAM_SEL_COUNTER)) + value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS; + + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_UPDATE_CTRL(tgt)), value); + + do { + value = in_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_UPDATE_CTRL(tgt))); + + } while (value & VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT); + + return CMD_RET_SUCCESS; +} + +static void vsc9953_vcap_init(void) +{ + u32 tgt = VSC9953_ES0; + int cmd_ret; + + /* write entries */ + vcap_entry2cache_init(tgt, ENTRY_WORDS_ES0); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY, + ENTRY_WORDS_ES0); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n", + __LINE__); + + /* write actions and counters */ + vcap_action2cache_init(tgt, BITS_TO_DWORD(91), BITS_TO_DWORD(1)); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_MV_CFG(tgt)), + VSC9953_VCAP_CFG_MV_CFG_SIZE(VSC9953_ES0_CNT + VSC9953_PORTS)); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, + TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_ES0); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n", + __LINE__); + + tgt = VSC9953_IS1; + + /* write entries */ + vcap_entry2cache_init(tgt, ENTRY_WORDS_IS1); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY, + ENTRY_WORDS_IS1); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n", + __LINE__); + + /* write actions and counters */ + vcap_action2cache_init(tgt, BITS_TO_DWORD(320), BITS_TO_DWORD(4)); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_MV_CFG(tgt)), + VSC9953_VCAP_CFG_MV_CFG_SIZE(VSC9953_IS1_CNT + 1)); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, + TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS1); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n", + __LINE__); + + tgt = VSC9953_IS2; + + /* write entries */ + vcap_entry2cache_init(tgt, ENTRY_WORDS_IS2); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY, + ENTRY_WORDS_IS2); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid selection: TCAM_SEL_ENTRY\n", + __LINE__); + + /* write actions and counters */ + vcap_action2cache_init(tgt, BITS_TO_DWORD(103 - 2 * + VSC9953_PORT_OFFSET), + BITS_TO_DWORD(4 * 32)); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_MV_CFG(tgt)), + VSC9953_VCAP_CFG_MV_CFG_SIZE(VSC9953_IS2_CNT + + VSC9953_PORTS + 2)); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, + TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS2); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n", + __LINE__); +} + void vsc9953_init(bd_t *bis) { u32 i; @@ -2605,6 +2738,7 @@ void vsc9953_init(bd_t *bis) } } + vsc9953_vcap_init(); vsc9953_default_configuration(); #ifdef CONFIG_CMD_ETHSW diff --git a/include/vsc9953.h b/include/vsc9953.h index a2d4554..a1c31ce 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -187,6 +187,64 @@ #define MIIMIND_OPR_PEND 0x00000004 +#define VSC9953_BIT(x) (1U << (x)) +#define VSC9953_IO_BASE_OFFSET 0x00000000 +#define VSC9953_IO_OFFSET(offset) (VSC9953_IO_BASE_OFFSET + offset) +#define VSC9953_BITMASK(x) ((1U << (x)) - 1) +#define VSC9953_ENC_BITFIELD(x, o, w) (((x) & VSC9953_BITMASK(w)) << (o)) +#define VSC9953_IO_ADDR(t, o) ((((t) - VSC9953_IO_BASE_OFFSET)) + \ + (o << 2)) + +#define VSC9953_IO_REG(t, o) (VSC9953_IO_ADDR(t, o)) +#define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri) \ + VSC9953_IO_REG(target, (0x2 + (ri))) + +#define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \ + VSC9953_IO_REG(target, (0x42 + (ri))) + +#define VSC9953_VCAP_CACHE_TG_DAT(target) VSC9953_IO_REG(target, 0xe2) +#define VSC9953_VCAP_CFG_MV_CFG(target) VSC9953_IO_REG(target, 0x1) +#define VSC9953_VCAP_CFG_MV_CFG_SIZE(x) VSC9953_ENC_BITFIELD(x, 0, 16) +#define VSC9953_VCAP_CFG_UPDATE_CTRL(target) VSC9953_IO_REG(target, 0x0) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(x) VSC9953_ENC_BITFIELD(x, 22, 3) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(x) VSC9953_ENC_BITFIELD(x, 3, 16) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT VSC9953_BIT(2) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS VSC9953_BIT(21) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS VSC9953_BIT(20) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS VSC9953_BIT(19) +#define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \ + VSC9953_IO_REG(target, (0x82 + (ri))) + +#define VSC9953_VCAP_CACHE_CNT_DAT(target, ri) \ + VSC9953_IO_REG(target, (0xc2 + (ri))) + +#define VSC9953_PORT_OFFSET 1 +#define VSC9953_IS1_CNT 256 +#define VSC9953_IS2_CNT 1024 +#define VSC9953_ES0_CNT 1024 + +#define BITS_TO_DWORD(x) (1 + (((x) - 1) / 32)) +#define ENTRY_WORDS_ES0 BITS_TO_DWORD(29) +#define ENTRY_WORDS_IS1 BITS_TO_DWORD(376) +#define ENTRY_WORDS_IS2 BITS_TO_DWORD(376) +#define VSC9953_PORTS VSC9953_MAX_PORTS + +/* TCAM entries */ +enum tcam_sel { + TCAM_SEL_ENTRY = VSC9953_BIT(0), + TCAM_SEL_ACTION = VSC9953_BIT(1), + TCAM_SEL_COUNTER = VSC9953_BIT(2), + TCAM_SEL_ALL = VSC9953_BITMASK(3), +}; + +enum tcam_cmd { + TCAM_CMD_WRITE = 0, + TCAM_CMD_READ = 1, + TCAM_CMD_MOVE_UP = 2, + TCAM_CMD_MOVE_DOWN = 3, + TCAM_CMD_INITIALIZE = 4, +}; + struct vsc9953_mdio_info { struct vsc9953_mii_mng *regs; char *name; -- 1.9.1

2 6

[U-Boot] [PATCH v2] net: include/phy.h: add new mode for internal phy
by Kunihiko Hayashi 13 Jun '18

13 Jun '18

Add the new mode to indicate a built-in PHY. This will be used by UniPhier AVE ethernet driver. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko(a)socionext.com> Reviewed-by: Marek Vasut <marek.vasut(a)gmail.com> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> --- Changes since v1: - add Reviewed-by and Acked-by tags include/phy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/phy.h b/include/phy.h index 52bf997..3b34504 100644 --- a/include/phy.h +++ b/include/phy.h @@ -65,6 +65,7 @@ typedef enum { PHY_INTERFACE_MODE_XAUI, PHY_INTERFACE_MODE_RXAUI, PHY_INTERFACE_MODE_SFI, + PHY_INTERFACE_MODE_INTERNAL, PHY_INTERFACE_MODE_NONE, /* Must be last */ PHY_INTERFACE_MODE_COUNT, @@ -87,6 +88,7 @@ static const char *phy_interface_strings[] = { [PHY_INTERFACE_MODE_XAUI] = "xaui", [PHY_INTERFACE_MODE_RXAUI] = "rxaui", [PHY_INTERFACE_MODE_SFI] = "sfi", + [PHY_INTERFACE_MODE_INTERNAL] = "internal", [PHY_INTERFACE_MODE_NONE] = "", }; -- 2.7.4

2 1

[U-Boot] [PATCH] net: nfs: don't fail when nfs_read_reply returns -NFS_RPC_DROP
by Vasily Khoruzhick 13 Jun '18

13 Jun '18

That can happen if duplicate UDP packet arrived, and that's not uncommon. Anyway, we ignore packets with rpc_id lower than last we sent for other requests, so it makes sense to do that for read request as well. Signed-off-by: Vasily Khoruzhick <anarsoul(a)gmail.com> --- net/nfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/nfs.c b/net/nfs.c index 83ed0a7c37..9a16765ba1 100644 --- a/net/nfs.c +++ b/net/nfs.c @@ -822,6 +822,8 @@ static void nfs_handler(uchar *pkt, unsigned dest, struct in_addr sip, case STATE_READ_REQ: rlen = nfs_read_reply(pkt, len); + if (rlen == -NFS_RPC_DROP) + break; net_set_timeout_handler(nfs_timeout, nfs_timeout_handler); if (rlen > 0) { nfs_offset += rlen; -- 2.17.0

2 4