February 2018 - U-Boot

[U-Boot] [PATCH v1 0/4] DRA7x: add support for HS200 in SPL
by Jean-Jacques Hiblot 14 Mar '18

14 Mar '18

HS200 support in SPL, while not mandatory, is a desirable feature if falcon mode is enabled as it will speed up the loading of big images. All code is in place to support high speed mmc modes in the SPL, but a bit of configuration is required to use it. This is done 3 steps: - enable HS200 in mmc core - enable multi-dtb in SPL. This is required because some information is available only in the dtb and vary across SOCs - make sure that the information is available in the SPL version of the dtbs that are stripped-down versions to reduce their size. dra7xx_hs_evm_config hasn't been updated on purpose because it doesn't enable OS_BOOT and HS200 support makes sense mostly in this use case. This series also provides the missing pinctrl/IOdelay properties for the dra76-evm platform. The DTSI file has been copied from linux 4.14 The whole series adds about 2.1kB to the SPL. This series has been tested on: - dra76-evm - dra7-evm - dra72-evm rev C - dra71-evm Jean-Jacques Hiblot (4): ARM: dts: dra76x: create a common file with MMC/SD IOdelay data ARM: dts: dra76-evm: shift to using common IOdelay data configs: dra7xx_evm: Enable support for the HS200 mmc mode in the SPL ARM: dts: dra7x: Make pinctrl and IOdelays for MMC2 available in SPL arch/arm/dts/dra7-evm-u-boot.dtsi | 20 +++ arch/arm/dts/dra71-evm-u-boot.dtsi | 24 +++ arch/arm/dts/dra72-evm-revc-u-boot.dtsi | 24 +++ arch/arm/dts/dra76-evm-u-boot.dtsi | 12 ++ arch/arm/dts/dra76-evm.dts | 51 +----- arch/arm/dts/dra76x-mmc-iodelay.dtsi | 285 ++++++++++++++++++++++++++++++++ configs/dra7xx_evm_defconfig | 3 + 7 files changed, 376 insertions(+), 43 deletions(-) create mode 100644 arch/arm/dts/dra76x-mmc-iodelay.dtsi -- 1.9.1

2 8

[U-Boot] [RFC PATCH 0/3] ARM: omap3: beagle, evm: synchronize common setup
by Derald D. Woods 14 Mar '18

14 Mar '18

This short series is an attempt to make this set of boards use the same default configuration items where possible. This was prompted by an investigation into enabling SERIAL_SEARCH_ALL on omap3_evm. This feature now works for omap3_evm after this series. The 'RFC' is because of changes in the default NAND layout of MTDPARTS_DEFAULT and using ENV_IS_IN_FAT. More detail is provided with the patches. As most things are configurable now, this should not be an issue. I am trying to get simple defaults that just boot and expose the common core features. Derald D. Woods (3): ARM: omap3: beagle: Set 'mtdids' and 'mtdparts' in board file ARM: omap3: beagle: Enable DM_SERIAL, update distro usage and NAND layout ARM: omap3: evm: Sync with omap3_beagle configuration board/ti/beagle/beagle.c | 8 ++ configs/omap3_beagle_defconfig | 29 ++++- configs/omap3_evm_defconfig | 25 +++-- include/configs/omap3_beagle.h | 241 +++++++++++++++++++++++------------------ include/configs/omap3_evm.h | 71 +++++++----- 5 files changed, 220 insertions(+), 154 deletions(-) -- 2.16.1

3 20

[U-Boot] [PATCH 0/3] Provide partition names to commands in environment
by Sam Protsenko 14 Mar '18

14 Mar '18

This patch series makes it possible to pass partition name to "part start" and "part size" commands, and fixes corresponding magic numbers (partition numbers) in TI boot environment. Sam Protsenko (3): cmd: part: Allow passing partition name to start and size cmd: part: Extract common code to separate function env: ti: boot: Get rid of magic numbers cmd/part.c | 75 +++++++++++++++++++++---------------------- include/environment/ti/boot.h | 10 +++--- 2 files changed, 41 insertions(+), 44 deletions(-) -- 2.16.1

3 8

[U-Boot] [PATCH 1/2] test/py: add MMC/SD block read test
by Stephen Warren 14 Mar '18

14 Mar '18

From: Stephen Warren <swarren(a)nvidia.com> Add a standalone MMC block read test. This allows direct testing of MMC access rather than relying on doing so as a side-effect of e.g. DFU or UMS testing, which may not be enabled on all platforms. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- test/py/tests/test_mmc_rd.py | 129 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 test/py/tests/test_mmc_rd.py diff --git a/test/py/tests/test_mmc_rd.py b/test/py/tests/test_mmc_rd.py new file mode 100644 index 000000000000..7ff76228e2e9 --- /dev/null +++ b/test/py/tests/test_mmc_rd.py @@ -0,0 +1,129 @@ +# Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0 + +# Test U-Boot's "mmc read" command. The test reads data from the eMMC or SD +# card, and validates the no errors occurred, and that the expected data was +# read if the test configuration contains a CRC of the expected data. + +import pytest +import u_boot_utils + +""" +This test relies on boardenv_* to containing configuration values to define +which MMC devices should be tested. For example: + +env__mmc_rd_configs = ( + { + "fixture_id": "emmc-boot0", + "is_emmc": True, + "devid": 0, + "partid": 1, + "sector": 0x10, + "count": 1, + }, + { + "fixture_id": "emmc-boot1", + "is_emmc": True, + "devid": 0, + "partid": 2, + "sector": 0x10, + "count": 1, + }, + { + "fixture_id": "emmc-data", + "is_emmc": True, + "devid": 0, + "partid": 0, + "sector": 0x10, + "count": 0x1000, + }, + { + "fixture_id": "sd-mbr", + "is_emmc": False, + "devid": 1, + "partid": None, + "sector": 0, + "count": 1, + "crc32": "8f6ecf0d", + }, + { + "fixture_id": "sd-large", + "is_emmc": False, + "devid": 1, + "partid": None, + "sector": 0x10, + "count": 0x1000, + }, +) +""" + +(a)pytest.mark.buildconfigspec('cmd_mmc') +def test_mmc_rd(u_boot_console, env__mmc_rd_config): + """Test the "mmc read" command. + + Args: + u_boot_console: A U-Boot console connection. + env__mmc_rd_config: The single MMC configuration on which + to run the test. See the file-level comment above for details + of the format. + + Returns: + Nothing. + """ + + is_emmc = env__mmc_rd_config['is_emmc'] + devid = env__mmc_rd_config['devid'] + partid = env__mmc_rd_config.get('partid', 0) + sector = env__mmc_rd_config.get('sector', 0) + count_sectors = env__mmc_rd_config.get('count', 1) + expected_crc32 = env__mmc_rd_config.get('crc32', None) + + count_bytes = count_sectors * 512 + bcfg = u_boot_console.config.buildconfig + has_cmd_memory = bcfg.get('config_cmd_memory', 'n') == 'y' + has_cmd_crc32 = bcfg.get('config_cmd_crc32', 'n') == 'y' + ram_base = u_boot_utils.find_ram_base(u_boot_console) + addr = '0x%08x' % ram_base + + # Select MMC device + cmd = 'mmc dev %d' % devid + if is_emmc: + cmd += ' %d' % partid + response = u_boot_console.run_command(cmd) + assert 'no card present' not in response + if is_emmc: + partid_response = "(part %d)" % partid + else: + partid_response = "" + good_response = 'mmc%d%s is current device' % (devid, partid_response) + assert good_response in response + + # Clear target RAM + if expected_crc32: + if has_cmd_memory and has_cmd_crc32: + cmd = 'mw.b %s 0 0x%x' % (addr, count_bytes) + u_boot_console.run_command(cmd) + + cmd = 'crc32 %s 0x%x' % (addr, count_bytes) + response = u_boot_console.run_command(cmd) + assert expected_crc32 not in response + else: + u_boot_console.log.warning( + 'CONFIG_CMD_MEMORY or CONFIG_CMD_CRC32 != y: Skipping RAM clear') + + # Read data + cmd = 'mmc read %s %x %x' % (addr, sector, count_sectors) + response = u_boot_console.run_command(cmd) + good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % ( + devid, sector, count_sectors, count_sectors) + assert good_response in response + + # Check target RAM + if expected_crc32: + if has_cmd_crc32: + cmd = 'crc32 %s 0x%x' % (addr, count_bytes) + response = u_boot_console.run_command(cmd) + assert expected_crc32 in response + else: + u_boot_console.log.warning('CONFIG_CMD_CRC32 != y: Skipping check') -- 2.16.1

2 5

[U-Boot] [PATCH] ARM: dts: Add support for stm32f746-evaluation board support
by patrice.chotard＠st.com 14 Mar '18

14 Mar '18

From: Patrice Chotard <patrice.chotard(a)st.com> This board offers: _ STM32F746NGH6 microcontroller with 1 Mbyte Flash and 320+4 Kbytes RAM _ Six 5 V power supply options: Power jack ST-LINK/V2-1 USB connector User USB HS connector User USB FS1 connector User USB FS2 connector Daughterboard _ SAI Audio DAC, stereo audio jack which supports headset with microphone _ Stereo digital microphone, audio jack connector used to connect external speakers _ 2 Gbytes (or more) SDMMC interface microSD card _ RF-EEPROM on I2C compatible serial interface _ RS-232 communication _ IrDA transceiver _ JTAG/SWD and ETM trace debug support, ST-LINK/V2-1 embedded _ IEEE-802.3-2002 compliant Ethernet connector _ Camera module _ 8Mx32 bit SDRAM, 1Mx16 bit SRAM & 8Mx16 bit Nor Flash _ 512 Mbits QuadSPI Nor Flash _ 5.7 inch 640x480 pixel TFT color LCD with capacitive touch panel _ Joystick with 4-direction control and selector _ Reset, WakeUp/Tamper or key button _ 4 color user LEDs _ Extension connectors & memory connectors for daughterboard or wrapping board _ USB OTG HS and FS with Micro-AB connectors _ RTC with backup battery _ CAN 2.0A/B compliant connection _ Potentiometer _ Motor control connector More detailed information are available here : http://www.st.com/en/evaluation-tools/stm32746g-eval.html To compile stm32f746-eval board, use same defconfig as stm32f746-disco, the only difference is to pass "DEVICE_TREE=stm32746g-eval". Signed-off-by: Christophe Priouzeau <christophe.priouzeau(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32746g-eval.dts | 240 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 242 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32746g-eval.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c7695aa1f1dc..a2f6a10ae39d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -224,7 +224,8 @@ dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ stm32f469-disco.dtb dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ - stm32f769-disco.dtb + stm32f769-disco.dtb \ + stm32746g-eval.dtb dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ stm32h743i-eval.dtb diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts new file mode 100644 index 000000000000..4f6d38acccd7 --- /dev/null +++ b/arch/arm/dts/stm32746g-eval.dts @@ -0,0 +1,240 @@ +/* + * Copyright 2018 - Christophe Priouzeau <christophe.priouzeau(a)st.com> + * + * Based on: + * stm32f746-disco.dts from U-boot 2018.01 + * Copyright 2016 - Lee Jones <lee.jones(a)linaro.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include <dt-bindings/memory/stm32-sdram.h> + +/ { + model = "STMicroelectronics STM32F746G-EVAL board"; + compatible = "st,stm32f746g-eval", "st,stm32f746"; + + chosen { + bootargs = "root=/dev/mmcblk0p1 rw rootwait"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xC0000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + spi0 = &qspi; + mmc0 = &sdio; + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpiof 10 0>; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioc 13 0>; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&pinctrl { + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32F746_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; + + ethernet_mii: mii@0 { + pins { + pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, + <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F746_PA2_FUNC_ETH_MDIO>, + <STM32F746_PC1_FUNC_ETH_MDC>, + <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */ + <STM32F746_PI9_FUNC_FMC_D30>, /* FMC_D30*/ + <STM32F746_PI7_FUNC_FMC_D29>, /* FMC_D29 */ + <STM32F746_PI6_FUNC_FMC_D28>, /* FMC_D28 */ + <STM32F746_PI3_FUNC_FMC_D27>, /* FMC_D27 */ + <STM32F746_PI2_FUNC_FMC_D26>, /* FMC_D26 */ + <STM32F746_PI1_FUNC_FMC_D25>, /* FMC_D25 */ + <STM32F746_PI0_FUNC_FMC_D24>, /* FMC_D24 */ + <STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */ + <STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */ + <STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */ + <STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */ + <STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */ + <STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */ + <STM32F746_PH9_FUNC_FMC_D17>, /* FMC_D17 */ + <STM32F746_PH8_FUNC_FMC_D16>, /* FMC_D16 */ + + <STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */ + <STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/ + <STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */ + <STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */ + <STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */ + <STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */ + <STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */ + <STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */ + <STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */ + <STM32F746_PE9_FUNC_FMC_D6>, /* FMC_D6 */ + <STM32F746_PE8_FUNC_FMC_D5>, /* FMC_D5*/ + <STM32F746_PE7_FUNC_FMC_D4>, /* FMC_D4 */ + <STM32F746_PD1_FUNC_FMC_D3>, /* FMC_D3 */ + <STM32F746_PD0_FUNC_FMC_D2>, /* FMC_D2 */ + <STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */ + <STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */ + + <STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */ + <STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */ + <STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */ + <STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */ + + <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */ + <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/ + + <STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */ + <STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */ + <STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */ + <STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */ + <STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */ + <STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */ + <STM32F746_PF5_FUNC_FMC_A5>, /* FUNC_FMC_A5 */ + <STM32F746_PF4_FUNC_FMC_A4>, /* FMC_A4 */ + <STM32F746_PF3_FUNC_FMC_A3>, /* FMC_A3 */ + <STM32F746_PF2_FUNC_FMC_A2>, /* FMC_A2 */ + <STM32F746_PF1_FUNC_FMC_A1>, /* FMC_A1 */ + <STM32F746_PF0_FUNC_FMC_A0>, /* FMC_A0 */ + + <STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */ + <STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */ + <STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */ + <STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */ + <STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */ + <STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */ + slew-rate = <2>; + }; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mac { + status = "okay"; + pinctrl-0 = <&ethernet_mii>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4 + CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2 + TWR_1 TRCD_1>; + st,sdram-refcount = <1539>; + }; +}; + +&sdio { + status = "okay"; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + bus-width = <4>; + max-frequency = <25000000>; +}; -- 1.9.1

4 4

[U-Boot] [PATCH v2 1/2] disk: part: scan the disk if the part_type is unknown
by Kever Yang 14 Mar '18

14 Mar '18

If a DUT do not have partition table, and we write one with 'gpt write' cmd, we should able to list the partition with 'part list' cmd. It's reasonable to scan the disk again if the initial part_type is unknown in case we just write a new one into disk. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2: - update commit message to make it more clear why we need this patch disk/part.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/disk/part.c b/disk/part.c index 66b8101..df0d50d 100644 --- a/disk/part.c +++ b/disk/part.c @@ -27,16 +27,28 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef HAVE_BLOCK_DEVICE -static struct part_driver *part_driver_lookup_type(int part_type) +static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc) { struct part_driver *drv = ll_entry_start(struct part_driver, part_driver); const int n_ents = ll_entry_count(struct part_driver, part_driver); struct part_driver *entry; - for (entry = drv; entry != drv + n_ents; entry++) { - if (part_type == entry->part_type) - return entry; + if (dev_desc->part_type == PART_TYPE_UNKNOWN) { + for (entry = drv; entry != drv + n_ents; entry++) { + int ret; + + ret = entry->test(dev_desc); + if (!ret) { + dev_desc->part_type = entry->part_type; + return entry; + } + } + } else { + for (entry = drv; entry != drv + n_ents; entry++) { + if (dev_desc->part_type == entry->part_type) + return entry; + } } /* Not found */ @@ -285,7 +297,7 @@ void part_print(struct blk_desc *dev_desc) { struct part_driver *drv; - drv = part_driver_lookup_type(dev_desc->part_type); + drv = part_driver_lookup_type(dev_desc); if (!drv) { printf("## Unknown partition table type %x\n", dev_desc->part_type); @@ -314,7 +326,7 @@ int part_get_info(struct blk_desc *dev_desc, int part, info->type_guid[0] = 0; #endif - drv = part_driver_lookup_type(dev_desc->part_type); + drv = part_driver_lookup_type(dev_desc); if (!drv) { debug("## Unknown partition table type %x\n", dev_desc->part_type); -- 1.9.1

2 3

[U-Boot] [PATCH v2 0/5] STM32: Clean unused and factorize .h files in arch-stm32
by patrice.chotard＠st.com 14 Mar '18

14 Mar '18

From: Patrice Chotard <patrice.chotard(a)st.com> Removes unused .h files in arch/arm/include/asm/arch-stm32xx Factorize and clean some .h files to avoid to duplicate defines in separate .h files V2: _ create arch/arm/include/asm/arch-stm32 directory and move gpio.h and stm32f.h in it. Patrice Chotard (5): arch-stm32f4: Remove fmc.h file arch-stm32: Move gpio.h for STM32 SoCs in include/asm/ arch-stm32: Factorize stm32.h for STM32F4 and F7 arch-stm32: Remove stm32_periph.h arch-stm32: Clean arch-stm32f7/syscfg.h arch/arm/include/asm/arch-stm32/gpio.h | 115 ++++++++++++++++++ arch/arm/include/asm/arch-stm32/stm32f.h | 22 ++++ arch/arm/include/asm/arch-stm32f4/fmc.h | 75 ------------ arch/arm/include/asm/arch-stm32f4/gpio.h | 146 +---------------------- arch/arm/include/asm/arch-stm32f4/stm32.h | 14 +-- arch/arm/include/asm/arch-stm32f4/stm32_periph.h | 38 ------ arch/arm/include/asm/arch-stm32f7/gpio.h | 115 +----------------- arch/arm/include/asm/arch-stm32f7/stm32.h | 45 +------ arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 23 ---- arch/arm/include/asm/arch-stm32f7/syscfg.h | 9 -- arch/arm/include/asm/arch-stm32h7/gpio.h | 115 +----------------- board/st/stm32f746-disco/stm32f746-disco.c | 1 - drivers/mtd/stm32_flash.c | 2 +- 13 files changed, 144 insertions(+), 576 deletions(-) create mode 100644 arch/arm/include/asm/arch-stm32/gpio.h create mode 100644 arch/arm/include/asm/arch-stm32/stm32f.h delete mode 100644 arch/arm/include/asm/arch-stm32f4/fmc.h delete mode 100644 arch/arm/include/asm/arch-stm32f4/stm32_periph.h delete mode 100644 arch/arm/include/asm/arch-stm32f7/stm32_periph.h -- 1.9.1

3 11

[U-Boot] [PATCH] ARM: dts: stm32: limit sdio frequency to 14Mhz for stm32f429i-eval
by patrice.chotard＠st.com 14 Mar '18

14 Mar '18

From: Patrice Chotard <patrice.chotard(a)st.com> This avoids the following errors while reading on mmc: Read data bytes CRC error: 0x2 switch to partitions #0, OK mmc0 is current device Read data bytes CRC error: 0x82002 ** Unrecognized filesystem type ** Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- arch/arm/dts/stm32429i-eval.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/stm32429i-eval.dts b/arch/arm/dts/stm32429i-eval.dts index 362ea4245e5b..4bf53a717d92 100644 --- a/arch/arm/dts/stm32429i-eval.dts +++ b/arch/arm/dts/stm32429i-eval.dts @@ -230,6 +230,7 @@ pinctrl-0 = <&sdio_pins>; pinctrl-1 = <&sdio_pins_od>; bus-width = <4>; + max-frequency = <14000000>; }; &timers1 { -- 1.9.1

2 1

[U-Boot] [PATCH 0/7] clk: clk_stm32f: update and fixes
by patrice.chotard＠st.com 14 Mar '18

14 Mar '18

From: Patrice Chotard <patrice.chotard(a)st.com> This series : _ Fixes one issue stm32_clk_get_rate() _ Update the SDMMC clock generation across all STM32F SoCs _ Adds LTDC clock generation from PLLSAI _ Adds set_rate() for LTDC clock _ Adds DSI clock support Patrice Chotard (7): clk: clk_stm32f: Fix stm32_clk_get_rate() clk: clk_stm32f: Fix RCC_PLLSAICFGR mask defines clk: clk_stm32f: No more need of 48Mhz from PLL_SAI clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() part clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock clk: clk_stm32f: Add set_rate for LTDC clock clk: clk_stm32f: Add DSI clock support drivers/clk/clk_stm32f.c | 279 +++++++++++++++++++++++++++------- include/dt-bindings/mfd/stm32f7-rcc.h | 1 + 2 files changed, 224 insertions(+), 56 deletions(-) -- 1.9.1

2 14

[U-Boot] [PATCH 0/2] stm32_sdmmc2 driver update
by patrice.chotard＠st.com 14 Mar '18

14 Mar '18

From: Patrice Chotard <patrice.chotard(a)st.com> This series adds the following stm32_sdmmc2 driver update : _ Enable hardware flow control _ Add support for st,pin-ckinsdmmc_ckin to select "ckin" clock input to sample received data. Patrick Delaunay (2): mmc: stm32: sdmmc2: add hardware flow control support mmc: stm32: sdmmc2: add support for st,pin-ckinsdmmc_ckin drivers/mmc/stm32_sdmmc2.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 1.9.1

2 4