February 2018 - U-Boot

[U-Boot] [PATCH 0/6] Add DM timer support for STM32 SoCs family
by patrice.chotard＠st.com 14 Mar '18

14 Mar '18

From: Patrice Chotard <patrice.chotard(a)st.com> Add DM timer support for all STM32F7/F4/H7 SoCs family. Clock driver for STM32F4/F7 and H7 need to updated to get timer clock rate. Remove all defines or files previously used for timer usage in arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx. Patrice Chotard (6): timer: stm32: Add timer support for STM32 SoCs family clk: clk_stm32f: Fix stm32_clk_get_rate() for timer clk: clk_stm32h7: Fix stm32_clk_get_rate() for timer clk: clk_stm32h7: Fix prescaler for Domain 3 ARM: dts: stm32: Add timer support for STM32F7 board: stm32: switch to DM STM32 timer arch/arm/dts/stm32f7-u-boot.dtsi | 8 ++ arch/arm/dts/stm32f746.dtsi | 7 ++ arch/arm/include/asm/arch-stm32f4/stm32.h | 3 - arch/arm/include/asm/arch-stm32f4/stm32_defs.h | 15 --- arch/arm/include/asm/arch-stm32f7/gpt.h | 53 --------- arch/arm/include/asm/arch-stm32f7/stm32.h | 5 - arch/arm/include/asm/arch-stm32f7/stm32_defs.h | 15 --- arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 4 - arch/arm/mach-stm32/Kconfig | 7 ++ arch/arm/mach-stm32/Makefile | 2 - arch/arm/mach-stm32/stm32f4/Makefile | 11 -- arch/arm/mach-stm32/stm32f4/timer.c | 115 ------------------- arch/arm/mach-stm32/stm32f7/Makefile | 8 -- arch/arm/mach-stm32/stm32f7/timer.c | 113 ------------------- board/st/stm32f746-disco/stm32f746-disco.c | 1 - drivers/clk/clk_stm32f.c | 131 +++++++++++++++------ drivers/clk/clk_stm32h7.c | 109 +++++++++++++++--- drivers/spi/stm32_qspi.c | 1 - drivers/timer/Kconfig | 7 ++ drivers/timer/Makefile | 1 + drivers/timer/stm32_timer.c | 138 +++++++++++++++++++++++ include/configs/stm32h743-disco.h | 3 +- include/configs/stm32h743-eval.h | 3 +- include/stm32_rcc.h | 5 + 24 files changed, 368 insertions(+), 397 deletions(-) delete mode 100644 arch/arm/include/asm/arch-stm32f4/stm32_defs.h delete mode 100644 arch/arm/include/asm/arch-stm32f7/gpt.h delete mode 100644 arch/arm/include/asm/arch-stm32f7/stm32_defs.h delete mode 100644 arch/arm/mach-stm32/stm32f4/Makefile delete mode 100644 arch/arm/mach-stm32/stm32f4/timer.c delete mode 100644 arch/arm/mach-stm32/stm32f7/Makefile delete mode 100644 arch/arm/mach-stm32/stm32f7/timer.c create mode 100644 drivers/timer/stm32_timer.c -- 1.9.1

2 12

[U-Boot] [PATCH v2 0/2] common/memsize.c: restore content of the base address
by Patrick Delaunay 14 Mar '18

14 Mar '18

I detect a issue in get_ram_size() function when maxsize is available; in this case, the base address is not restored. Please, check if these 2 patch don't introduce regression on your board because this code is really sensible. Issue detected on my board (not yet up-streamed) with - DDR base = 0xC0000000 - expected detected size = maxsize = 0x40000000 The loop is completely executed so the size is correctly detected, but content of memory at address 0xC0000000 is not restored: I sill have 0xC0000000 = 0x0 at the end of the function. In the correction (patch 2 of the serie), I restore this content when no error is detected (for the last return). NB: I also add a comment for the previous return to avoid regression for the case size<max_size because for this case, the higher bit of address are not used and the higher addresses are overlapped with the lower addresses (same physical content) => the original data at address 0x0 is already restore because *(base + size) and *base is physically the same physical address = ~(size-1) & logical address => address overlap detected with (val != ~cnt) *base was forced to 0 but content for *(base + size) already restore Test on Sandbox (v2018.01) -------------------------- I test the issue and the correction in sandbox by adding a debug command "test_ram_size" in cmd/mem.c which: 1/ fill memory buffer with random value 2/ use get_ram_size() on this buffer 3/ check buffer content modification static int do_test_ram_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned int seed = rand(); long *ptr = NULL; long size; unsigned int offset, expec, read; ptr = map_sysmem(MEM_TEST_BASE, MEM_TEST_SIZE); for (offset = 0; offset < MEM_TEST_SIZE / sizeof(long); offset ++) *(ptr + offset) = rand(); size = get_ram_size(ptr, MEM_TEST_SIZE); srand(seed); for (offset = 0; offset < MEM_TEST_SIZE / sizeof(long); offset ++) { expec = rand(); read = *(ptr + offset); if (read != expec) printf(" ERROR: %p <= %lx, %x, expected %x\n", ptr + offset, MEM_TEST_BASE + (offset * sizeof(long)), read, expec); } unmap_sysmem(ptr); printf("get_ram_size(%x,%x)=%lx\n", MEM_TEST_BASE, MEM_TEST_SIZE, size); return 0; } U_BOOT_CMD( test_ram_size, 1, 1, do_test_ram_size, "test memory", "" ); after the first patch: the error is detected at address 0x0, the value become 0x0 => test_ram_size ERROR: 00007f6b0018d008 <= 0, 0, expected 4080601 get_ram_size(0,100000)=100000 => test_ram_size ERROR: 00007f6b0018d008 <= 0, 0, expected 9a61a0f3 get_ram_size(0,100000)=100000 after the second patch, all the memory is correctly restored => test_ram_size get_ram_size(0,100000)=100000 Test on real ARM target ----------------------- My target is a ARMv7 Cortex A7 board not yet upstreamed with DDR. I also use the same test by patching SPL: + initialize the DDR controller + write random content in all the DDR + use get_ram_size(0xC0000000, 0x40000000) on all the possible DDR range + check content of the DDR Test 1, 1GB DDR (2 chipsx16bits => 32 bits access) @ 0xC0000000 => detected size is 0x40000000 (1GB) => test OK memory is restored (but test failed without patch 2) => the memory is correctly restored for last case (size=max_size) Test 2, I change the controller parameter to reduce the used bits for DDR (using one chip => 16 bits access and only 512MB) => detected size is 0x20000000 (overlap detected for 0xE0000000 address: same physical address 0x0 in DDR than 0xC0000000) => test OK memory is restored (test OK with or without patch 2) => the memory is already correctly restored for the overlap case (where I just add comment) Changes in v2: - Split patch in 2 part to more easily understood regression - Solve issue for overlap case: don't restore saved value (invalid) and add comment to avoid to have this issue again Patrick Delaunay (2): common/memsize.c: prepare get_ram_size update common/memsize.c: restore content of the base address common/memsize.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) -- 2.7.4

2 4

[U-Boot] [PATCH 0/3] add inital SF tests
by Liam Beguin 14 Mar '18

14 Mar '18

Hi all, This is the inital step to adding tests for the SF subsystem plus very minor fixes. It is based on work I found on the mailing list[1]. For now, it doesn't do much but I plan on adding code to reset the flash to its initial state (based on an env flag) and more code to test the `sf protect` subcommand (which is the main goal of this series). I'm sending it now to make sure it's headed in the right direction. Thanks, Liam Beguin [ 1 ] https://patchwork.ozlabs.org/patch/623061/ Liam Beguin (3): test/py: README: fix typo test/py: README: add HOSTNAME to PYTHONPATH test/py: add spi_flash tests test/py/README.md | 6 +- test/py/tests/test_sf.py | 233 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 236 insertions(+), 3 deletions(-) create mode 100644 test/py/tests/test_sf.py base-commit: 4bafceff0e9e5a36908031e41c69a6b37e82da58 Published-As: https://github.com/Liambeguin/u-boot/releases/tag/test_sf_v1 -- 2.16.1.72.g5be1f00a9a70

6 23

[U-Boot] [PATCH 0/2] SF: add support for sst26wf016, sst26wf032, sst26wf064
by Eugeniy Paltsev 13 Mar '18

13 Mar '18

Add support for the SST sst26wf016, sst26wf032 and sst26wf064 flash IC: sst26wf*** flash series block protection implementation differs from other SST series, so we add implementation for sst26wf*** lock/unlock/is_locked functions. Add sst26wf016, sst26wf032 and sst26wf064 flash IC info to spi_flash_ids list. Eugeniy Paltsev (2): SPI Flash: add support of sst26wf* flash series SF: add support for sst26wf016, sst26wf032, sst26wf064 drivers/mtd/spi/spi_flash.c | 188 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi_flash_ids.c | 3 + 2 files changed, 191 insertions(+) -- 2.9.3

2 5

[U-Boot] [PATCH v2 3/3] sunxi: Add A20-SOM204-EVB-eMMC board
by Stefan Mavrodiev 13 Mar '18

13 Mar '18

A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired to MMC2 slot. This patch adds defconfig and dts files for this board. The dts is same with mainline kernel. Signed-off-by: Stefan Mavrodiev <stefan(a)olimex.com> Acked-by: Maxime Ripard <maxime.ripard(a)free-electrons.com> --- Changes for v2: - Add missing MAINTAINERS entry - Reworked defconfig file arch/arm/dts/Makefile | 1 + arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts | 36 +++++++++++++++++++++++ board/sunxi/MAINTAINERS | 1 + configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 34 +++++++++++++++++++++ 4 files changed, 72 insertions(+) create mode 100644 arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts create mode 100644 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 97e8790..f9764a4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -304,6 +304,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-mk808c.dtb \ sun7i-a20-olimex-som-evb.dtb \ sun7i-a20-olimex-som204-evb.dtb \ + sun7i-a20-olimex-som204-evb-emmc.dtb \ sun7i-a20-olinuxino-lime.dtb \ sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-lime2-emmc.dtb \ diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts new file mode 100644 index 0000000..c56620a --- /dev/null +++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for A20-SOM204-EVB-eMMC Board + * + * Copyright (C) 2018 Olimex Ltd. + * Author: Stefan Mavrodiev <stefan(a)olimex.com> + */ + +/dts-v1/; +#include "sun7i-a20-olimex-som204-evb.dts" + +/ { + model = "Olimex A20-SOM204-EVB-eMMC"; + compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: mmc2_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <&reg_vcc3v3>; + mmc-pwrseq = <&mmc2_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 2298853..5aadb98 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -315,6 +315,7 @@ OLIMEX A20-SOM204 BOARD M: Stefan Mavrodiev <stefan(a)olimex.com> S: Maintained F: configs/A20-Olimex-SOM204-EVB_defconfig +F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig ORANGEPI WIN/WIN PLUS BOARD M: Jagan Teki <jagan(a)amarulasolutions.com> diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig new file mode 100644 index 0000000..11fe6bd --- /dev/null +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=384 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB0_VBUS_PIN="PC17" +CONFIG_USB0_VBUS_DET="PH5" +CONFIG_I2C1_ENABLE=y +CONFIG_SATAPWR="PC3" +CONFIG_GMAC_TX_DELAY=4 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc" +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_SCSI_AHCI=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY_ADDR=3 +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_RGMII=y +CONFIG_SUN7I_GMAC=y +CONFIG_AXP_ALDO3_VOLT=2800 +CONFIG_AXP_ALDO4_VOLT=2800 +CONFIG_SCSI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -- 2.7.4

2 1

[U-Boot] [PATCH v2 2/3] sunxi: Add A20-SOM204-EVB board
by Stefan Mavrodiev 13 Mar '18

13 Mar '18

This is new System-On-Module platform with universal dimm socket for easy insertation. The EVB board is designed to be universal with future modules. Base features of A20-SOM204 board includes: * 1GB DDR3 RAM * AXP209 PMU * KSZ9031 Gigabit PHY * AT24C16 EEPROM * Status LED * LCD connector * GPIO connector There will be variants with the following options: * Second LAN8710A Megabit PHY * 16MB SPI Flash memory * eMMC card * ATECC508 crypto device The EVB board has: * Debug UART * MicroSD card connector * USB-OTG connector * Two USB host * RTL8723BS WiFi/BT combo * IrDA transceiver/receiver * HDMI connector * VGA connector * Megabit ethernet transceiver * Gigabit ethernet transceiver * SATA connector * CAN driver * CSI camera * MIC and HP connectors * PCIe x4 connector * USB3 connector * Two UEXT connectors * Two user LEDs Some of the features are multiplexed and cannot be used the same time: CAN and Megabit PHY. Others are not usable with A20 SoC: PCIe and USB3. This patch adds defconfig and dts files for this board. The dts is same with mainline kernel, except some nodes are removed to make file compatible with existing dtsi file. Signed-off-by: Stefan Mavrodiev <stefan(a)olimex.com> Acked-by: Maxime Ripard <maxime.ripard(a)free-electrons.com> --- Changes for v2: - Add missing MAINTAINERS entry - Reworked defconfig file arch/arm/dts/Makefile | 1 + arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 296 +++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/A20-Olimex-SOM204-EVB_defconfig | 33 +++ 4 files changed, 335 insertions(+) create mode 100644 arch/arm/dts/sun7i-a20-olimex-som204-evb.dts create mode 100644 configs/A20-Olimex-SOM204-EVB_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebbc0ca..97e8790 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -303,6 +303,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-m5.dtb \ sun7i-a20-mk808c.dtb \ sun7i-a20-olimex-som-evb.dtb \ + sun7i-a20-olimex-som204-evb.dtb \ sun7i-a20-olinuxino-lime.dtb \ sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-lime2-emmc.dtb \ diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts new file mode 100644 index 0000000..c183920 --- /dev/null +++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for A20-SOM204-EVB Board + * + * Copyright (C) 2018 Olimex Ltd. + * Author: Stefan Mavrodiev <stefan(a)olimex.com> + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Olimex A20-SOM204-EVB"; + compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart4; + serial2 = &uart7; + spi0 = &spi1; + spi1 = &spi2; + ethernet1 = &rtl8723bs; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + stat { + label = "a20-som204-evb:green:stat"; + gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led1 { + label = "a20-som204-evb:green:led1"; + gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led2 { + label = "a20-som204-evb:yellow:led2"; + gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + rtl_pwrseq: rtl_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; + }; +}; + +&ahci { + target-supply = <&reg_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&reg_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy3>; + phy-mode = "rgmii"; + phy-supply = <&reg_vcc3v3>; + + snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* Exposed to UEXT1 */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Exposed to UEXT2 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; + cd-inverted; + status = "okay"; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <&reg_vcc3v3>; + mmc-pwrseq = <&rtl_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + bt_uart_pins: bt_uart_pins@0 { + pins = "PG6", "PG7", "PG8"; + function = "uart3"; + }; +}; + +#include "axp209.dtsi" + +&reg_ahci_5v { + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&reg_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +&reg_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +&reg_ldo1 { + regulator-always-on; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-rtc"; +}; + +&reg_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +&reg_ldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pg"; +}; + +&reg_usb0_vbus { + gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&reg_usb1_vbus { + status = "okay"; +}; + +&reg_usb2_vbus { + status = "okay"; +}; + +/* Exposed to UEXT1 */ +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>, + <&spi1_cs0_pins_a>; + status = "okay"; +}; + +/* Exposed to UEXT2 */ +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>, + <&spi2_cs0_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +/* Used for RTL8723BS bluetooth */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&bt_uart_pins>; + status = "okay"; +}; + +/* Exposed to UEXT1 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + +/* Exposed to UEXT2 */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <&reg_usb0_vbus>; + usb1_vbus-supply = <&reg_usb1_vbus>; + usb2_vbus-supply = <&reg_usb2_vbus>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 362edff..2298853 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -311,6 +311,11 @@ M: FUKAUMI Naoki <naobsd(a)gmail.com> S: Maintained F: configs/Nintendo_NES_Classic_Edition_defconfig +OLIMEX A20-SOM204 BOARD +M: Stefan Mavrodiev <stefan(a)olimex.com> +S: Maintained +F: configs/A20-Olimex-SOM204-EVB_defconfig + ORANGEPI WIN/WIN PLUS BOARD M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig new file mode 100644 index 0000000..8cabc96 --- /dev/null +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -0,0 +1,33 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=384 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_USB0_VBUS_PIN="PC17" +CONFIG_USB0_VBUS_DET="PH5" +CONFIG_I2C1_ENABLE=y +CONFIG_SATAPWR="PC3" +CONFIG_GMAC_TX_DELAY=4 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb" +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_SCSI_AHCI=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY_ADDR=3 +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_RGMII=y +CONFIG_SUN7I_GMAC=y +CONFIG_AXP_ALDO3_VOLT=2800 +CONFIG_AXP_ALDO4_VOLT=2800 +CONFIG_SCSI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -- 2.7.4

2 1

[U-Boot] [PATCH] net: sun8i_emac: Fix PHY initialization
by Samuel Holland 13 Mar '18

13 Mar '18

The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- drivers/net/sun8i_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 3ccc6b0bb6..be43472b1a 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -431,7 +431,7 @@ static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) tx_descs_init(priv); /* PHY Start Up */ - genphy_parse_link(priv->phydev); + phy_startup(priv->phydev); sun8i_adjust_link(priv, priv->phydev); -- 2.13.6

3 2

[U-Boot] [PATCH 1/1] mmc: sunxi: support cd-inverted
by Heinrich Schuchardt 13 Mar '18

13 Mar '18

With CONFIG_DM_MMC the BananaPi does not detect SD cards. The sunxi device trees use the cd-inverted property to indicate that the card detect is inverted. This property is documented in Linux kernel devicetree/bindings/mmc/mmc.txt The property is not marked as deprecated. A similar patch was posted by Tuomas but is in status "Changes Requested". https://patchwork.ozlabs.org/patch/850377/ This patch is a stripped down version of his patch. Suggested-by: Tuomas Tynkkynen <tuomas(a)tuxera.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/mmc/sunxi_mmc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 4edb4be46c8..e7666e315f2 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -30,6 +30,7 @@ struct sunxi_mmc_priv { uint32_t *mclkreg; unsigned fatal_err; struct gpio_desc cd_gpio; /* Change Detect GPIO */ + int cd_inverted; /* Inverted Card Detect */ struct sunxi_mmc *reg; struct mmc_config cfg; }; @@ -544,9 +545,11 @@ static int sunxi_mmc_getcd(struct udevice *dev) { struct sunxi_mmc_priv *priv = dev_get_priv(dev); - if (dm_gpio_is_valid(&priv->cd_gpio)) - return dm_gpio_get_value(&priv->cd_gpio); + if (dm_gpio_is_valid(&priv->cd_gpio)) { + int cd_state = dm_gpio_get_value(&priv->cd_gpio); + return cd_state ^ priv->cd_inverted; + } return 1; } @@ -610,6 +613,9 @@ static int sunxi_mmc_probe(struct udevice *dev) sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP); } + /* Check if card detect is inverted */ + priv->cd_inverted = dev_read_bool(dev, "cd-inverted"); + upriv->mmc = &plat->mmc; /* Reset controller */ -- 2.11.0

3 2

[U-Boot] [PATCH] arm: sunxi: Move spl spi sunxi code to mach-sunxi
by Jagan Teki 13 Mar '18

13 Mar '18

This SUNXI variant SPL SPI code doesn't use either SPI or SPL_FLASG subsystems due to size constraints and also placing this code in drivers/mtd/spi will unnecessary build SPI_FLASH code(if defined) which never required, hence moved to arch area. And also renamed the file according to kconfig which resembles proper name. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- arch/arm/mach-sunxi/Kconfig | 8 ++++++++ arch/arm/mach-sunxi/Makefile | 1 + .../sunxi_spi_spl.c => arch/arm/mach-sunxi/spl_spi_sunxi.c | 0 drivers/mtd/spi/Kconfig | 13 ------------- drivers/mtd/spi/Makefile | 1 - 5 files changed, 9 insertions(+), 14 deletions(-) rename drivers/mtd/spi/sunxi_spi_spl.c => arch/arm/mach-sunxi/spl_spi_sunxi.c (100%) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 1fededd..dc48eef 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -847,4 +847,12 @@ config SPL_STACK_R_ADDR default 0x2fe00000 if MACH_SUN9I default 0x4fe00000 if MACH_SUN50I +config SPL_SPI_SUNXI + bool "Support for SPI Flash on Allwinner SoCs in SPL" + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I + help + Enable support for SPI Flash. This option allows SPL to read from + sunxi SPI Flash. It uses the same method as the boot ROM, so does + not need any extra configuration. + endif diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 2a3c379..6ddf682 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o +obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c similarity index 100% rename from drivers/mtd/spi/sunxi_spi_spl.c rename to arch/arm/mach-sunxi/spl_spi_sunxi.c diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 6ba255d..4484cf8 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -135,17 +135,4 @@ config SPI_FLASH_MTD If unsure, say N -if SPL - -config SPL_SPI_SUNXI - bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I - select SPL_SPI_FLASH_SUPPORT - ---help--- - Enable support for SPI Flash. This option allows SPL to read from - sunxi SPI Flash. It uses the same method as the boot ROM, so does - not need any extra configuration. - -endif - endmenu # menu "SPI Flash Support" diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index fcda023..4be6e9b 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -9,7 +9,6 @@ obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o -obj-$(CONFIG_SPL_SPI_SUNXI) += sunxi_spi_spl.o endif obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o -- 2.7.4

1 1

[U-Boot] [PATCH 0/5] efi_loader: implement event groups
by Heinrich Schuchardt 12 Mar '18

12 Mar '18

The patch series provides support for event groups. If any event of the group is signaled all other events are signaled too. The events are managed in a linked list instead of an array. Some formatting errors are fixed. Heinrich Schuchardt (5): efi_loader: fix formatting errors efi_loader: manage events in a linked list efi_loader: define GUIDS for event groups efi_loader: implement event groups efi_selftest: unit test for event groups include/efi_api.h | 21 ++ include/efi_loader.h | 28 ++- lib/efi_loader/efi_boottime.c | 339 ++++++++++++++++----------- lib/efi_loader/efi_console.c | 6 +- lib/efi_loader/efi_net.c | 4 +- lib/efi_loader/efi_runtime.c | 11 + lib/efi_loader/efi_watchdog.c | 2 +- lib/efi_selftest/Makefile | 1 + lib/efi_selftest/efi_selftest_event_groups.c | 140 +++++++++++ 9 files changed, 400 insertions(+), 152 deletions(-) create mode 100644 lib/efi_selftest/efi_selftest_event_groups.c -- 2.14.2

2 7