December 2018 - U-Boot

[U-Boot] [PATCH v4 00/10] Changes for Turris Mox
by Marek Behún 21 Jan '19

21 Jan '19

This is the fourth version of patches for Turris Mox. Changes from previous version: - changed patch subject prefix from board: turris_mox to arm: mvebu: turris_mox as requested by Stefan - added Reviewed-by Stefan - add description of the changes for watchdog in patch 6 - patch 9 reworked to use get_ram_size instead of reading OTP Marek

2 11

[U-Boot] [PATCH v2] ARM: mvebu: sync Armada-38x dts with Linux 4.20
by Chris Packham 21 Jan '19

21 Jan '19

Sync the Armada-38x device tree files with Linux 4.20-rc5. The changes not taken are new compatible strings for the uart and nand flash controller. The nand binding is best updated if/when the mtd/nand infrastructure is updated. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> Reviewed-by: Stefan Roese <sr(a)denx.de> --- I've updated the clearfog and controlcenterdc boards enough for them to compile. In the case of clearfog there are a lot of changes in Linux so it's probably best if the board maintainer looks at what is needed. controlcenterdc isn't in linux so again I've just done enough for compilation. Changes in v2: - Correct comment for SPI CS1 for clearfog (thanks Baruch) arch/arm/dts/armada-380.dtsi | 44 +-- arch/arm/dts/armada-385.dtsi | 63 +---- arch/arm/dts/armada-388-clearfog.dts | 25 +- arch/arm/dts/armada-388.dtsi | 43 +-- arch/arm/dts/armada-38x-controlcenterdc.dts | 68 ++--- arch/arm/dts/armada-38x.dtsi | 283 ++++++++++++-------- 6 files changed, 237 insertions(+), 289 deletions(-) diff --git a/arch/arm/dts/armada-380.dtsi b/arch/arm/dts/armada-380.dtsi index 5102d19cc8f4..cff1269f3fbf 100644 --- a/arch/arm/dts/armada-380.dtsi +++ b/arch/arm/dts/armada-380.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 380 SoC. * @@ -6,44 +7,6 @@ * Lior Amsalem <alior(a)marvell.com> * Gregory CLEMENT <gregory.clement(a)free-electrons.com> * Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-38x.dtsi" @@ -71,7 +34,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; @@ -104,6 +67,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>; @@ -122,6 +86,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>; @@ -140,6 +105,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>; diff --git a/arch/arm/dts/armada-385.dtsi b/arch/arm/dts/armada-385.dtsi index 8e67d2c083dd..f0022d10c715 100644 --- a/arch/arm/dts/armada-385.dtsi +++ b/arch/arm/dts/armada-385.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 385 SoC. * @@ -6,44 +7,6 @@ * Lior Amsalem <alior(a)marvell.com> * Gregory CLEMENT <gregory.clement(a)free-electrons.com> * Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-38x.dtsi" @@ -70,13 +33,7 @@ }; soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6820-pinctrl"; - }; - }; - - pcie-controller { + pciec: pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; @@ -106,7 +63,7 @@ * configured in x4 by the bootloader, then * pcie@4,0 is not available. */ - pcie@1,0 { + pcie1: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -115,6 +72,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>; @@ -124,7 +82,7 @@ }; /* x1 port */ - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -133,6 +91,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>; @@ -142,7 +101,7 @@ }; /* x1 port */ - pcie@3,0 { + pcie3: pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x1800 0 0 0 0>; @@ -151,6 +110,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>; @@ -163,7 +123,7 @@ * x1 port only available when pcie@1,0 is * configured as a x1 port */ - pcie@4,0 { + pcie4: pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; reg = <0x2000 0 0 0 0>; @@ -172,6 +132,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>; @@ -182,3 +143,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv88f6820-pinctrl"; +}; diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts index 16a47d59e667..a3493ddd4d45 100644 --- a/arch/arm/dts/armada-388-clearfog.dts +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -118,18 +118,7 @@ status = "okay"; }; - spi1: spi@10680 { - /* - * CS0: W25Q32 - * CS1: - * CS2: mikrobus - */ - pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - usb0: usb3@f8000 { + usb3@f8000 { /* CON7, USB-A port on back of device */ status = "okay"; }; @@ -322,6 +311,18 @@ }; }; +&spi1 { + /* + * Add SPI CS pins for clearfog: + * CS0: W25Q32 + * CS1: + * CS2: mikrobus + */ + pinctrl-0 = <&spi1_pins &mikro_spi_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + /* +#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 MPP18: gpio ? (pca9655 int?) diff --git a/arch/arm/dts/armada-388.dtsi b/arch/arm/dts/armada-388.dtsi index 564fa5937e25..f3a020ff577e 100644 --- a/arch/arm/dts/armada-388.dtsi +++ b/arch/arm/dts/armada-388.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 388 SoC. * @@ -5,39 +6,6 @@ * * Gregory CLEMENT <gregory.clement(a)free-electrons.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * * The main difference with the Armada 385 is that the 388 can handle two more * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl * property and the name of the SoC, and add the second SATA host which control @@ -50,13 +18,8 @@ model = "Marvell Armada 388 family SoC"; compatible = "marvell,armada388", "marvell,armada385", "marvell,armada380"; - soc { internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6828-pinctrl"; - }; - sata@e0000 { compatible = "marvell,armada-380-ahci"; reg = <0xe0000 0x2000>; @@ -68,3 +31,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv88f6828-pinctrl"; +}; diff --git a/arch/arm/dts/armada-38x-controlcenterdc.dts b/arch/arm/dts/armada-38x-controlcenterdc.dts index 2cc996876a77..ffbd0dcaae47 100644 --- a/arch/arm/dts/armada-38x-controlcenterdc.dts +++ b/arch/arm/dts/armada-38x-controlcenterdc.dts @@ -72,40 +72,6 @@ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; internal-regs { - spi0: spi@10600 { - status = "okay"; - sc16is741: sc16is741@0 { - compatible = "nxp,sc16is741"; - reg = <0>; - clocks = <&sc16isclk>; - spi-max-frequency = <4000000>; - interrupt-parent = <&gpio0>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - spi1: spi@10680 { - status = "okay"; - u-boot,dm-pre-reloc; - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q016a", "spi-flash"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - spi-flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a11", "spi-flash"; - reg = <1>; /* Chip select 1 */ - spi-max-frequency = <108000000>; - u-boot,dm-pre-reloc; - }; - }; - I2C0: i2c@11000 { status = "okay"; clock-frequency = <1000000>; @@ -586,3 +552,37 @@ }; }; }; + +&spi0 { + status = "okay"; + sc16is741: sc16is741@0 { + compatible = "nxp,sc16is741"; + reg = <0>; + clocks = <&sc16isclk>; + spi-max-frequency = <4000000>; + interrupt-parent = <&gpio0>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&spi1 { + status = "okay"; + u-boot,dm-pre-reloc; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q016a", "spi-flash"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + spi-flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a11", "spi-flash"; + reg = <1>; /* Chip select 1 */ + spi-max-frequency = <108000000>; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index 5e5a15855189..72c49beb71a4 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 38x family of SoCs. * @@ -6,44 +7,6 @@ * Lior Amsalem <alior(a)marvell.com> * Gregory CLEMENT <gregory.clement(a)free-electrons.com> * Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" @@ -83,7 +46,7 @@ reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; }; - devbus-bootcs { + devbus_bootcs: devbus-bootcs { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; @@ -93,7 +56,7 @@ status = "disabled"; }; - devbus-cs0 { + devbus_cs0: devbus-cs0 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; @@ -103,7 +66,7 @@ status = "disabled"; }; - devbus-cs1 { + devbus_cs1: devbus-cs1 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; @@ -113,7 +76,7 @@ status = "disabled"; }; - devbus-cs2 { + devbus_cs2: devbus-cs2 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; @@ -123,7 +86,7 @@ status = "disabled"; }; - devbus-cs3 { + devbus_cs3: devbus-cs3 { compatible = "marvell,mvebu-devbus"; reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; @@ -145,6 +108,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <0>; + prefetch-data = <1>; }; scu@c000 { @@ -152,6 +119,13 @@ reg = <0xc000 0x58>; }; + timer@c200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xc200 0x20>; + interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; + clocks = <&coreclk 2>; + }; + timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; @@ -168,32 +142,8 @@ <0xc100 0x100>; }; - spi0: spi@10600 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = <0x10600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = <0x10680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; @@ -204,7 +154,7 @@ }; i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; @@ -258,19 +208,6 @@ marvell,function = "i2c0"; }; - nand_pins: nand-pins { - marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", - "mpp38", "mpp28", "mpp40", "mpp42", - "mpp35", "mpp36", "mpp25", "mpp30", - "mpp32"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp41"; - marvell,function = "nand"; - }; - mdio_pins: mdio-pins { marvell,pins = "mpp4", "mpp5"; marvell,function = "ge"; @@ -298,6 +235,20 @@ marvell,function = "spi1"; }; + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", + "mpp33", "mpp38", "mpp28", + "mpp40", "mpp42", "mpp35", + "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp41"; + marvell,function = "nand"; + }; + uart0_pins: uart-pins-0 { marvell,pins = "mpp0", "mpp1"; marvell,function = "ua0"; @@ -338,34 +289,42 @@ }; gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <28>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; }; - system-controller@18200 { + systemc: system-controller@18200 { compatible = "marvell,armada-380-system-controller", "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x100>; @@ -386,7 +345,8 @@ mbusc: mbus-controller@20000 { compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; + reg = <0x20000 0x100>, <0x20180 0x20>, + <0x20250 0x8>; }; mpic: interrupt-controller@20a00 { @@ -399,7 +359,7 @@ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; }; - timer@20300 { + timer: timer@20300 { compatible = "marvell,armada-380-timer", "marvell,armada-xp-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; @@ -413,14 +373,14 @@ clock-names = "nbclk", "fixed"; }; - watchdog@20300 { + watchdog: watchdog@20300 { compatible = "marvell,armada-380-wdt"; reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; }; - cpurst@20800 { + cpurst: cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x10>; }; @@ -430,16 +390,37 @@ reg = <0x20d20 0x6c>; }; - coherency-fabric@21010 { + coherencyfab: coherency-fabric@21010 { compatible = "marvell,armada-380-coherency-fabric"; reg = <0x21010 0x1c>; }; - pmsu@22000 { + pmsu: pmsu@22000 { compatible = "marvell,armada-380-pmsu"; reg = <0x22000 0x1000>; }; + /* + * As a special exception to the "order by + * register address" rule, the eth0 node is + * placed here to ensure that it gets + * registered as the first interface, since + * the network subsystem doesn't allow naming + * interfaces using DT aliases. Without this, + * the ordering of interfaces is different + * from the one used in U-Boot and the + * labeling of interfaces on the boards, which + * is very confusing for users. + */ + eth0: ethernet@70000 { + compatible = "marvell,armada-370-neta"; + reg = <0x70000 0x4000>; + interrupts-extended = <&mpic 8>; + clocks = <&gateclk 4>; + tx-csum-limit = <9800>; + status = "disabled"; + }; + eth1: ethernet@30000 { compatible = "marvell,armada-370-neta"; reg = <0x30000 0x4000>; @@ -456,7 +437,7 @@ status = "disabled"; }; - usb@58000 { + usb0: usb@58000 { compatible = "marvell,orion-ehci"; reg = <0x58000 0x500>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; @@ -464,8 +445,8 @@ status = "disabled"; }; - xor@60800 { - compatible = "marvell,orion-xor"; + xor0: xor@60800 { + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; reg = <0x60800 0x100 0x60a00 0x100>; clocks = <&gateclk 22>; @@ -484,8 +465,8 @@ }; }; - xor@60900 { - compatible = "marvell,orion-xor"; + xor1: xor@60900 { + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; clocks = <&gateclk 28>; @@ -504,14 +485,6 @@ }; }; - eth0: ethernet@70000 { - compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x4000>; - interrupts-extended = <&mpic 8>; - clocks = <&gateclk 4>; - status = "disabled"; - }; - mdio: mdio@72004 { #address-cells = <1>; #size-cells = <0>; @@ -520,14 +493,29 @@ clocks = <&gateclk 4>; }; - rtc@a3800 { + cesa: crypto@90000 { + compatible = "marvell,armada-38x-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 23>, <&gateclk 21>, + <&gateclk 14>, <&gateclk 16>; + clock-names = "cesa0", "cesa1", + "cesaz0", "cesaz1"; + marvell,crypto-srams = <&crypto_sram0>, + <&crypto_sram1>; + marvell,crypto-sram-size = <0x800>; + }; + + rtc: rtc@a3800 { compatible = "marvell,armada-380-rtc"; reg = <0xa3800 0x20>, <0x184a0 0x0c>; reg-names = "rtc", "rtc-soc"; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; }; - sata@a8000 { + ahci0: sata@a8000 { compatible = "marvell,armada-380-ahci"; reg = <0xa8000 0x2000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; @@ -535,7 +523,15 @@ status = "disabled"; }; - sata@e0000 { + bm: bm@c8000 { + compatible = "marvell,armada-380-neta-bm"; + reg = <0xc8000 0xac>; + clocks = <&gateclk 13>; + internal-mem = <&bm_bppi>; + status = "disabled"; + }; + + ahci1: sata@e0000 { compatible = "marvell,armada-380-ahci"; reg = <0xe0000 0x2000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; @@ -551,23 +547,23 @@ clock-output-names = "nand"; }; - thermal@e8078 { + thermal: thermal@e8078 { compatible = "marvell,armada380-thermal"; - reg = <0xe4078 0x4>, <0xe4074 0x4>; + reg = <0xe4078 0x4>, <0xe4070 0x8>; status = "okay"; }; - flash@d0000 { + nand_controller: nand-controller@d0000 { compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand"; reg = <0xd0000 0x54>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&coredivclk 0>; status = "disabled"; }; - sdhci@d8000 { + sdhci: sdhci@d8000 { compatible = "marvell,armada-380-sdhci"; reg-names = "sdhci", "mbus", "conf-sdio3"; reg = <0xd8000 0x1000>, @@ -579,7 +575,7 @@ status = "disabled"; }; - usb3@f0000 { + usb3_0: usb3@f0000 { compatible = "marvell,armada-380-xhci"; reg = <0xf0000 0x4000>,<0xf4000 0x4000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; @@ -587,7 +583,7 @@ status = "disabled"; }; - usb3@f8000 { + usb3_1: usb3@f8000 { compatible = "marvell,armada-380-xhci"; reg = <0xf8000 0x4000>,<0xfc000 0x4000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; @@ -595,10 +591,63 @@ status = "disabled"; }; }; + + crypto_sram0: sa-sram0 { + compatible = "mmio-sram"; + reg = <MBUS_ID(0x09, 0x19) 0 0x800>; + clocks = <&gateclk 23>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; + }; + + crypto_sram1: sa-sram1 { + compatible = "mmio-sram"; + reg = <MBUS_ID(0x09, 0x15) 0 0x800>; + clocks = <&gateclk 21>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; + }; + + bm_bppi: bm-bppi { + compatible = "mmio-sram"; + reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; + ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gateclk 13>; + no-memory-wc; + status = "disabled"; + }; + + spi0: spi@10600 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; -- 2.19.2

2 4

[U-Boot] re-use dm data for pre-relocate and post-relocate
by Kever Yang 21 Jan '19

21 Jan '19

Hi Simon, In order to make people easier to maintain a U-Boot for product, we want to re-use the dtb from kernel. Some peripheral like power/pmic and display panel, key, charger which need work in U-Boot and may different in different product, we want to make people only maintain kernel dts, but not one more U-Boot project for all these devices. I want to do this just around the relocate, need to read dtb from storage like emmc/nand/spi, and then use a new dtb for initr_dm after relocate. Here are issues I have met: - The kernel dts may not have a stdout in chosen, we may use earlycon, earlyprintk instead; this lead to U-Boot can not find a serial driver after relocate; - no alias for mmc device which is need by U-Boot but not used in kernel; - not able to init mmc driver twice with current driver; mmc driver not able to work before relocate, no bss for (static int initialized), and hang even if I skip this; mmc driver can init and read dtb before initr_dm, but not able to init again after initr_dm. In fact, I don't think we have to re-init serial driver and mmc driver, and most other driver which need pre-relocate like clock, the only driver I have seem have different use in pre-relocate and post-relocate is video driver(no idea why it have to be pre-relocate, we always have display very late), can we add a tag for re-use the dm driver data for those with pre-relocate ? Thanks, - Kever

2 2

[U-Boot] [PATCH v3 0/5] Migrate BOUNCE_BUFFER
by Philipp Tomsich 19 Jan '19

19 Jan '19

5 16

[U-Boot] [PATCH 0/9] Support 4GB of memory on 32bit systems
by Philipp Tomsich 19 Jan '19

19 Jan '19

Even on 32bit systems a full 4GB of DRAM may be installed and reported by the DRAM controller. Whether these 4GB are larger available depends on the size/configuration of address decoding windows and architectural features. This increases the fields holding the RAM size to have at least 33bits (i.e. we use a u64) and fixes the fallout from the change: some casts, the usage of min() and a few printf formats have to be adjusted. Philipp Tomsich (9): dm: allow 4GB of DRAM on 32bit systems rockchip: support 4GB DRAM on 32bit systems common: include <inttypes.h> always MIPS: use PRIx64 macros for printing ram size rockchip: rk3368: change type of ram-size field for a min()-calculation ram: stm32mp1: use PRIx64 macros for printing ram size board: keymile: add explicit cast to truncate the 64bit ram size field board: cm_fx6: use PRIx64 macros for printing ram size mpc85xx: add casts for ram size in min() calculation. arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 +- arch/arm/mach-rockchip/sdram_common.c | 8 ++++---- arch/arm/mach-stm32mp/dram_init.c | 2 +- arch/mips/mach-bmips/dram.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 6 ++++-- board/compulab/cm_fx6/cm_fx6.c | 3 ++- board/keymile/km_arm/km_arm.c | 6 ++++-- drivers/ram/rockchip/dmc-rk3368.c | 2 +- drivers/ram/stm32mp1/stm32mp1_ram.c | 2 +- include/asm-generic/global_data.h | 2 +- include/common.h | 1 + include/ram.h | 9 ++++++++- 12 files changed, 29 insertions(+), 16 deletions(-) -- 2.1.4

14 39

[U-Boot] [u-boot][PATCH] ls1046aqds: Bypass xfi port fixup for KR mode
by Florinel Iordache 18 Jan '19

18 Jan '19

u-boot makes a fixup for LS1046AQDS board to setup the properties 'fixed-link' and 'phy-connection-type' to 'xgmii' but in case of backplane mode this fixup is not correct because it causes the KR link to fail and so it must be bypassed in order to keep the link in KR mode as it is defined in DTS. Signed-off-by: Florinel Iordache <florinel.iordache(a)nxp.com> --- board/freescale/ls1046aqds/eth.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index d3e8831..1fd755c 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #include <common.h> @@ -153,6 +154,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { struct fixed_link f_link; + u32 *handle; + char *prop = NULL; + int off; if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { switch (port) { @@ -208,16 +212,27 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, "qsgmii"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && (port == FM1_10GEC1 || port == FM1_10GEC2)) { - /* XFI interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for XFI */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); + handle = fdt_getprop(fdt, offset, "phy-handle", NULL); + prop = NULL; + if (handle) { + off = fdt_node_offset_by_phandle(fdt, + fdt32_to_cpu(*handle)); + prop = fdt_getprop(fdt, off, "backplane-mode", NULL); + } + if (!prop || strcmp(prop, "10gbase-kr")) { + /* XFI interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(10000); + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "xgmii"); + } } } -- 1.9.1

2 2

[U-Boot] [PATCH] armv8: fsl-layerscape: properly configure qdma ICID
by laurentiu.tudor＠nxp.com 18 Jan '19

18 Jan '19

From: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> --- arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 6 +++++- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index a3f473fe28..f375fe7115 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -55,7 +55,11 @@ void fdt_fixup_icid(void *blob); CONFIG_SYS_FSL_ESDHC_ADDR) #define SET_QDMA_ICID(compat, streamid) \ - SET_SCFG_ICID(compat, streamid, dma_icid,\ + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ + QDMA_BASE_ADDR), \ + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ QDMA_BASE_ADDR) #define SET_EDMA_ICID(streamid) \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 4d0f16f21c..b4b7c3492e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -94,6 +94,7 @@ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) +#define QMAN_CQSIDR_REG 0x20a80 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL -- 2.17.1

2 1

[U-Boot] [PATCH v1] mmc: fsl_esdhc: make get_cd work well in dm_mmc_ops
by Yinbo Zhu 18 Jan '19

18 Jan '19

This patch is to make get_cd work well when DM_MMC enabled Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- drivers/mmc/fsl_esdhc.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4528345..bbde8cf 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1487,7 +1487,6 @@ static int fsl_esdhc_get_cd(struct udevice *dev) { struct fsl_esdhc_priv *priv = dev_get_priv(dev); - return true; return esdhc_getcd_common(priv); } -- 1.7.1

2 1

[U-Boot] [PATCH] fsl-layerscape: dpaa: fix fsl-mc status in fdt with bootefi
by Mian Yousaf Kaukab 18 Jan '19

18 Jan '19

fsl-mc lazyapply command applies dpl from efi_exit_boot_services(). Status of fsl-mc node in working fdt is updated at this stage. However, an efi application like grub may already have copied the fdt. So the updates to fdt done at efi_exit_boot_services() may not be visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply command is used. Fixes: b7b8410a8f (ls2080: Exit dpaa only right before exiting U-Boot) Signed-off-by: Mian Yousaf Kaukab <ykaukab(a)suse.de> --- board/freescale/ls1088a/ls1088a.c | 3 ++- board/freescale/ls2080a/ls2080a.c | 3 ++- board/freescale/ls2080aqds/ls2080aqds.c | 3 ++- board/freescale/ls2080ardb/ls2080ardb.c | 3 ++- drivers/net/fsl-mc/mc.c | 5 +++++ include/fsl-mc/fsl_mc.h | 1 + 6 files changed, 14 insertions(+), 4 deletions(-) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 1e2ad98c6e..1b87b33e50 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -535,7 +535,8 @@ void fdt_fixup_board_enet(void *fdt) return; } - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) fdt_status_okay(fdt, offset); else fdt_status_fail(fdt, offset); diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 698ae1f9a6..c352bccb10 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -89,7 +89,8 @@ void fdt_fixup_board_enet(void *fdt) return; } - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) fdt_status_okay(fdt, offset); else fdt_status_fail(fdt, offset); diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index d336ef840c..a0a3301691 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -294,7 +294,8 @@ void fdt_fixup_board_enet(void *fdt) return; } - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) fdt_status_okay(fdt, offset); else fdt_status_fail(fdt, offset); diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index cf91bc30fb..79f2bcc52f 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -330,7 +330,8 @@ void fdt_fixup_board_enet(void *fdt) return; } - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) fdt_status_okay(fdt, offset); else fdt_status_fail(fdt, offset); diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index b245fbc681..a51b8a4625 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -834,6 +834,11 @@ int get_dpl_apply_status(void) return mc_dpl_applied; } +int is_lazy_dpl_addr_valid(void) +{ + return !!mc_lazy_dpl_addr; +} + /* * Return the MC address of private DRAM block. * As per MC design document, MC initial base address diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index aef40d3911..0abd797cc4 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -54,6 +54,7 @@ struct mc_ccsr_registers { void fdt_fsl_mc_fixup_iommu_map_entry(void *blob); int get_mc_boot_status(void); int get_dpl_apply_status(void); +int is_lazy_dpl_addr_valid(void); #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET int get_aiop_apply_status(void); #endif -- 2.11.0

2 1

[U-Boot] [PATCH 1/2] armv8: ls1043a: add SVR definitions for 23x23 package silicon
by Z.q. Hou 18 Jan '19

18 Jan '19

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 ++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ 2 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 1fc025b..0b84954 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -51,7 +51,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4), CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2), CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index f5bef6d..7d95c4e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -80,6 +80,9 @@ enum boot_src get_boot_src(void); #define SVR_LS1012A 0x870400 #define SVR_LS1043A 0x879200 #define SVR_LS1023A 0x879208 +/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ +#define SVR_LS1043A_P23 0x879202 +#define SVR_LS1023A_P23 0x87920A #define SVR_LS1046A 0x870700 #define SVR_LS1026A 0x870708 #define SVR_LS1048A 0x870320 -- 1.7.1

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