January 2018 - U-Boot

[U-Boot] Guide to hush shell in u-boot
by Nathan Holder 27 Jan '18

27 Jan '18

Anyone know where a guide to hush shell in u-boot would be? -Nate This email and any files transmitted with it are confidential and are intended solely for the use of the individual or entity to whom they are addressed. If you are not the intended recipient or the person responsible for delivering the email to the intended recipient, be advised that you have received this email in error and that any use, dissemination, forwarding, printing or copying of this email is strictly prohibited. If you have received this email in error, please immediately notify the Network Administrator by telephone at 336.615.8555. You will be reimbursed for reasonable costs incurred in notifying us.

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[U-Boot] Manual is out of date, missing commands and information
by Nathan Holder 27 Jan '18

27 Jan '18

This manual http://www.denx.de/wiki/DULG/Manual is out of date and missing a lot of info. I have been using it thinking it was the official manual. But then I learned many commands are not listed there. Please take down the manual so that people don't mistakenly use it thinking it is correct. -Nate This email and any files transmitted with it are confidential and are intended solely for the use of the individual or entity to whom they are addressed. If you are not the intended recipient or the person responsible for delivering the email to the intended recipient, be advised that you have received this email in error and that any use, dissemination, forwarding, printing or copying of this email is strictly prohibited. If you have received this email in error, please immediately notify the Network Administrator by telephone at 336.615.8555. You will be reimbursed for reasonable costs incurred in notifying us.

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[U-Boot] [RFC v2] i2c, omap24xx: Fixup High Speed Initialization
by Adam Ford 27 Jan '18

27 Jan '18

For devices running I2C over 400KHz, this needs to be in HS mode. Currently, the code is only running in HS mode when the speed is equal or greater than 3.4MHz. At least on the OMAP3630/3730, this fails when trying to configure at 2.6MHz Using the Linux kernel setup as a reference, I used much of their calculation for fsscll, fssclh, hsscll, and hssclh. However, Linux uses fclk = clk_get(omap->dev, "fck") and fclk_rate = clk_get_rate(fclk) When dumping the data of fck, I got 96000000. The U-Boot omap24xx I2C driver sets the I2C_IP_CLK to SYSTEM_CLOCK_96 and I2C_INTERNAL_SAMPLING_CLK to 19200000 except for arch/arm/include/asm/arch-am33xx/i2c.h which defines I2C_INTERNAL_SAMPLING_CLK to 12000000 and I2C_IP_CLK 48000000. I do not have this hardware, so I cannot test, but I compared the values of psc=4, scll=4377, sclh=1803 for both U-Boot and Linux and they match on an OMAP630/3730. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 5d33815..eace748 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -205,8 +205,10 @@ static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed, int hsscll = 0, hssclh = 0; u32 scll = 0, sclh = 0; - if (speed >= OMAP_I2C_HIGH_SPEED) { + if (speed > OMAP_I2C_FAST_MODE) { /* High speed */ + unsigned long scl; + psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; psc -= 1; if (psc < I2C_PSC_MIN) { @@ -215,12 +217,10 @@ static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed, } /* For first phase of HS mode */ - fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); + scl = I2C_INTERNAL_SAMPLING_CLK / 400000; + fsscll = scl - (scl / 3) - 7; + fssclh = (scl / 3) - 5; - fssclh = fsscll; - - fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; - fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing first phase clock\n"); @@ -228,10 +228,10 @@ static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed, } /* For second phase of HS mode */ - hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); + scl = I2C_IP_CLK / speed; + hsscll = scl - (scl / 3) - 7; + hssclh = (scl / 3) - 5; - hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; - hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing second phase clock\n"); @@ -240,7 +240,6 @@ static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed, scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; - } else { /* Standard and fast speed */ psc = omap24_i2c_findpsc(&scll, &sclh, speed); -- 2.7.4

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[U-Boot] sandbox and spi emulation (err=-19 Invalid bus 0 for spec)
by Славкин Олег 27 Jan '18

27 Jan '18

Hello I'm trying to run u-boot (sandbox) with a spi emulation, but the start fails with an error (err=-19). What I did # clone and compile u-boot cd ~/ git clone git://git.denx.de/u-boot.git cd u-boot git checkout v2017.11 make sandbox_defconfig menuconfig "Sandbox architecture" -> "Run sandbox on 32/64-bit host" (32-bit host) make # create file for SPI flash cd ~/u-boot dd if=/dev/zero of=spi.bin bs=1M count=4 # run ./u-boot --spi_sf 0:0:M25P16:spi.bin ----- U-Boot 2017.11 (Jan 27 2018 - 11:52:29 +0300) DRAM: 128 MiB Invalid bus 0 for spec 'M25P16:spi.bin' (err=-19) initcall sequence 0816b0f8 failed at call 001cf813 (err=-19) ### ERROR ### Please RESET the board ### ---- My host: $ lsb_release -a No LSB modules are available. Distributor ID: Ubuntu Description: Ubuntu 14.04.4 LTS Release: 14.04 Codename: trusty $ uname -a Linux devx86 4.2.0-27-generic #32~14.04.1-Ubuntu SMP Fri Jan 22 15:32:27 UTC 2016 i686 i686 i686 GNU/Linux What am I doing wrong? -- BR Oleg Slavkin

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[U-Boot] [PATCH 1/1] log: add category LOGC_EFI
by Heinrich Schuchardt 26 Jan '18

26 Jan '18

The EFI implementation does not fit into any of the existing categories. Provide LOGC_EFI so that EFI related message can be filtered. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- doc/README.log | 1 + include/log.h | 1 + 2 files changed, 2 insertions(+) diff --git a/doc/README.log b/doc/README.log index f653fe7d79..be9978a270 100644 --- a/doc/README.log +++ b/doc/README.log @@ -51,6 +51,7 @@ The following main categories are defined: LOGC_BOARD - Related to board-specific code LOGC_CORE - Related to core driver-model support LOGC_DT - Related to device tree control + LOGC_EFI - Related to the EFI implementation Enabling logging diff --git a/include/log.h b/include/log.h index 8083b64831..b155725de0 100644 --- a/include/log.h +++ b/include/log.h @@ -43,6 +43,7 @@ enum log_category_t { LOGC_BOARD, LOGC_CORE, LOGC_DT, + LOGC_EFI, LOGC_COUNT, LOGC_END, -- 2.15.1

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[U-Boot] [PATCH 0/9] log: Support control over the log output format
by Simon Glass 26 Jan '18

26 Jan '18

This adds a few more features to the log system: - 'log format' command to control the log output format - 'log rec' command to output a log record manually - log_ret() function to log error-return values With these we have more control over how log records are output as well as the ability to log errors more easily. Simon Glass (9): dm: core: Add a function to look up a uclass by name log: Add functions to convert IDs to/from names log: Add control over log formatting log: Update log_console to honour the log format log: Add a command to control the log output format log: Add a command to output a log record log: Add tests for the new log features log: Add documentation for commands and formatting log: Add a way to log error-return values cmd/log.c | 82 +++++++++++++++++++++++++++++++++++++++ common/Kconfig | 13 +++++++ common/log.c | 68 ++++++++++++++++++++++++++++++++ common/log_console.c | 27 ++++++++++++- configs/sandbox_defconfig | 1 + doc/README.log | 35 +++++++++++++++++ drivers/core/uclass.c | 14 +++++++ include/asm-generic/global_data.h | 1 + include/dm/uclass.h | 8 ++++ include/log.h | 64 +++++++++++++++++++++++++++++- test/dm/core.c | 9 +++++ test/py/tests/test_log.py | 32 +++++++++++++-- 12 files changed, 348 insertions(+), 6 deletions(-) -- 2.15.1.620.gb9897f4670-goog

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[U-Boot] Pull request: u-boot-sunxi/master
by Jagan Teki 26 Jan '18

26 Jan '18

Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit 557767ed29968af0294e3aae48433e5d5a298e0b: Merge git://git.denx.de/u-boot-marvell (2018-01-20 08:39:47 -0500) are available in the git repository at: git://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to a6968ecb0ad6b06552c97005eba265a4c5761626: gpio: sunxi: Add compatible string for H5 PIO (2018-01-26 20:02:33 +0530) ---------------------------------------------------------------- Andre Heider (1): sunxi: imply CONFIG_OF_LIBFDT_OVERLAY Chris Blake (1): gpio: sunxi: Add compatible string for H5 PIO Giulio Benetti (1): sunxi: Fix display timing flags Maxime Ripard (11): dfu: select HASH cmd: crc32: Disable by default on sunXi cmd: unzip: Disable by default on sunXi cmd: loadb: Disable by default on sunXi cmd: loads: Disable by default on sunXi cmd: misc: Disable by default on sunXi video: bpp8: Disable by default on sunXi video: bpp16: Disable by default on sunXi net: regex: Disable by default on sunXi Makefile: Add size check to the u-boot.itb make target sunxi: Add limit with the MMC environment Makefile | 1 + arch/arm/Kconfig | 1 + cmd/Kconfig | 5 +++++ configs/CHIP_defconfig | 1 - configs/CHIP_pro_defconfig | 1 - drivers/dfu/Kconfig | 1 + drivers/gpio/sunxi_gpio.c | 1 + drivers/video/Kconfig | 2 ++ drivers/video/sunxi/sunxi_display.c | 2 ++ include/configs/sunxi-common.h | 10 ++++++++++ lib/Kconfig | 1 + 11 files changed, 24 insertions(+), 2 deletions(-)

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Re: [U-Boot] [PATCH] ARM: socfpga: Convert callers of cm_write_with_phase for wait_for_bit_le32
by Goldschmidt Simon 26 Jan '18

26 Jan '18

On 01/26/2018 17:28, Tom Rini wrote: > Now that we have and use wait_for_bit_le32() available, the callers of > cm_write_with_phase() should not be casting values to u32 and instead we > expect a const void *, so provide that directly. > > Fixes: 48263504c8d5 ("wait_bit: use wait_for_bit_le32 and remove wait_for_bit") > Cc: Marek Vasut <marex(a)denx.de> > Signed-off-by: Tom Rini <trini(a)konsulko.com> > --- > arch/arm/mach-socfpga/clock_manager_gen5.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c > index 3d048ba3e432..4e5b6d169371 100644 > --- a/arch/arm/mach-socfpga/clock_manager_gen5.c > +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c > @@ -33,7 +33,7 @@ static void cm_write_ctrl(u32 val) > } > > /* function to write a clock register that has phase information */ > -static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask) > +static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask) Shouldn't that better be a non-const void * since it is used for writing a value, too? That 'const' is later casted away by __arch_putl(), but it still looks wrong to me. Simon > { > int ret; > > @@ -268,26 +268,26 @@ int cm_basic_init(const struct cm_config * const cfg) > * are aligned nicely; so we can change any phase. > */ > ret = cm_write_with_phase(cfg->ddrdqsclk, > - (u32)&clock_manager_base->sdr_pll.ddrdqsclk, > + &clock_manager_base->sdr_pll.ddrdqsclk, > CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); > if (ret) > return ret; > > /* SDRAM DDR2XDQSCLK */ > ret = cm_write_with_phase(cfg->ddr2xdqsclk, > - (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk, > + &clock_manager_base->sdr_pll.ddr2xdqsclk, > CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); > if (ret) > return ret; > > ret = cm_write_with_phase(cfg->ddrdqclk, > - (u32)&clock_manager_base->sdr_pll.ddrdqclk, > + &clock_manager_base->sdr_pll.ddrdqclk, > CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); > if (ret) > return ret; > > ret = cm_write_with_phase(cfg->s2fuser2clk, > - (u32)&clock_manager_base->sdr_pll.s2fuser2clk, > + &clock_manager_base->sdr_pll.s2fuser2clk, > CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); > if (ret) > return ret; > -- > 2.7.4

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[U-Boot] [PATCH] ARM: socfpga: Convert callers of cm_write_with_phase for wait_for_bit_le32
by Tom Rini 26 Jan '18

26 Jan '18

Now that we have and use wait_for_bit_le32() available, the callers of cm_write_with_phase() should not be casting values to u32 and instead we expect a const void *, so provide that directly. Fixes: 48263504c8d5 ("wait_bit: use wait_for_bit_le32 and remove wait_for_bit") Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/mach-socfpga/clock_manager_gen5.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 3d048ba3e432..4e5b6d169371 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -33,7 +33,7 @@ static void cm_write_ctrl(u32 val) } /* function to write a clock register that has phase information */ -static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask) +static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask) { int ret; @@ -268,26 +268,26 @@ int cm_basic_init(const struct cm_config * const cfg) * are aligned nicely; so we can change any phase. */ ret = cm_write_with_phase(cfg->ddrdqsclk, - (u32)&clock_manager_base->sdr_pll.ddrdqsclk, + &clock_manager_base->sdr_pll.ddrdqsclk, CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); if (ret) return ret; /* SDRAM DDR2XDQSCLK */ ret = cm_write_with_phase(cfg->ddr2xdqsclk, - (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk, + &clock_manager_base->sdr_pll.ddr2xdqsclk, CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); if (ret) return ret; ret = cm_write_with_phase(cfg->ddrdqclk, - (u32)&clock_manager_base->sdr_pll.ddrdqclk, + &clock_manager_base->sdr_pll.ddrdqclk, CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); if (ret) return ret; ret = cm_write_with_phase(cfg->s2fuser2clk, - (u32)&clock_manager_base->sdr_pll.s2fuser2clk, + &clock_manager_base->sdr_pll.s2fuser2clk, CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); if (ret) return ret; -- 2.7.4

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[U-Boot] [PULL] u-boot-mips/master
by Daniel Schwierzeck 26 Jan '18

26 Jan '18

The following changes since commit fb4413295c765aa8c013650984dc2d908964c81d: Merge git://git.denx.de/u-boot-mmc (2018-01-24 11:28:44 -0500) are available in the Git repository at: git://git.denx.de/u-boot-mips.git master for you to fetch changes up to 664ec31db7b99269b612360ffb3c9840a195e263: MIPS: add BMIPS Comtrend AR-5315u board (2018-01-26 12:38:13 +0100) ---------------------------------------------------------------- Paul Burton (1): boston: Pad binary in .mcs to a multiple of 16 bytes Álvaro Fernández Rojas (8): mips: bmips: increment SYS_MALLOC_F_LEN dm: cpu: bmips: add BCM6368 support MIPS: add support for Broadcom MIPS BCM6368 SoC family MIPS: add BMIPS Comtrend WAP-5813n board dm: cpu: bmips: add BCM6318 support dm: ram: bmips: add BCM6318 support MIPS: add support for Broadcom MIPS BCM6318 SoC family MIPS: add BMIPS Comtrend AR-5315u board arch/mips/dts/Makefile | 2 ++ arch/mips/dts/brcm,bcm6318.dtsi | 157 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/mips/dts/brcm,bcm6368.dtsi | 168 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/mips/dts/comtrend,ar-5315u.dts | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/mips/dts/comtrend,wap-5813n.dts | 65 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 51 ++++++++++++++++++++++++++++++++++ board/comtrend/ar5315u/Kconfig | 12 ++++++++ board/comtrend/ar5315u/MAINTAINERS | 6 ++++ board/comtrend/ar5315u/Makefile | 5 ++++ board/comtrend/ar5315u/ar-5315u.c | 7 +++++ board/comtrend/wap5813n/Kconfig | 12 ++++++++ board/comtrend/wap5813n/MAINTAINERS | 6 ++++ board/comtrend/wap5813n/Makefile | 5 ++++ board/comtrend/wap5813n/wap-5813n.c | 7 +++++ board/imgtec/boston/config.mk | 5 +++- configs/comtrend_ar5315u_ram_defconfig | 51 ++++++++++++++++++++++++++++++++++ configs/comtrend_wap5813n_ram_defconfig | 43 ++++++++++++++++++++++++++++ drivers/cpu/bmips_cpu.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/ram/bmips_ram.c | 19 +++++++++++++ include/configs/bmips_bcm6318.h | 25 +++++++++++++++++ include/configs/bmips_bcm6368.h | 30 ++++++++++++++++++++ include/configs/comtrend_ar5315u.h | 16 +++++++++++ include/configs/comtrend_wap5813n.h | 19 +++++++++++++ include/dt-bindings/clock/bcm6318-clock.h | 37 +++++++++++++++++++++++++ include/dt-bindings/clock/bcm6368-clock.h | 31 +++++++++++++++++++++ include/dt-bindings/power-domain/bcm6318-power-domain.h | 13 +++++++++ include/dt-bindings/reset/bcm6318-reset.h | 26 +++++++++++++++++ include/dt-bindings/reset/bcm6368-reset.h | 22 +++++++++++++++ 28 files changed, 995 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/brcm,bcm6318.dtsi create mode 100644 arch/mips/dts/brcm,bcm6368.dtsi create mode 100644 arch/mips/dts/comtrend,ar-5315u.dts create mode 100644 arch/mips/dts/comtrend,wap-5813n.dts create mode 100644 board/comtrend/ar5315u/Kconfig create mode 100644 board/comtrend/ar5315u/MAINTAINERS create mode 100644 board/comtrend/ar5315u/Makefile create mode 100644 board/comtrend/ar5315u/ar-5315u.c create mode 100644 board/comtrend/wap5813n/Kconfig create mode 100644 board/comtrend/wap5813n/MAINTAINERS create mode 100644 board/comtrend/wap5813n/Makefile create mode 100644 board/comtrend/wap5813n/wap-5813n.c create mode 100644 configs/comtrend_ar5315u_ram_defconfig create mode 100644 configs/comtrend_wap5813n_ram_defconfig create mode 100644 include/configs/bmips_bcm6318.h create mode 100644 include/configs/bmips_bcm6368.h create mode 100644 include/configs/comtrend_ar5315u.h create mode 100644 include/configs/comtrend_wap5813n.h create mode 100644 include/dt-bindings/clock/bcm6318-clock.h create mode 100644 include/dt-bindings/clock/bcm6368-clock.h create mode 100644 include/dt-bindings/power-domain/bcm6318-power-domain.h create mode 100644 include/dt-bindings/reset/bcm6318-reset.h create mode 100644 include/dt-bindings/reset/bcm6368-reset.h

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