September 2017 - U-Boot

[U-Boot] [PATCH] armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC
by Sriram Dash 25 Sep '17

25 Sep '17

IFC code is put under CONFIG_FSL_IFC Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 ++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 639e9d2..a538d76 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -192,7 +192,9 @@ void bypass_smmu(void) void fsl_lsch3_early_init_f(void) { erratum_rcw_src(); +#ifdef CONFIG_FSL_IFC init_early_memctl_regs(); /* tighten IFC timing */ +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 erratum_a009203(); #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index c4e5ecc..f231688 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -102,6 +102,7 @@ static struct mm_region early_map[] = { { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_SIZE1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, +#ifdef CONFIG_FSL_IFC /* For IFC Region #1, only the first 4MB is cache-enabled */ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1_1, @@ -116,6 +117,7 @@ static struct mm_region early_map[] = { CONFIG_SYS_FSL_IFC_SIZE1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) @@ -125,11 +127,13 @@ static struct mm_region early_map[] = { #endif PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_FSL_IFC /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#endif { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -159,10 +163,12 @@ static struct mm_region early_map[] = { CONFIG_SYS_FSL_QSPI_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#ifdef CONFIG_FSL_IFC { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) @@ -206,10 +212,12 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#ifdef CONFIG_FSL_IFC { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_SIZE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#endif { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -304,10 +312,12 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#ifdef CONFIG_FSL_IFC { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | -- 1.9.1

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[U-Boot] [PATCH] pci: layerscape: Fixup iommu-map for LS208xA
by Bharat Bhushan 25 Sep '17

25 Sep '17

"pci: layerscape: Fixup device tree node for ls2088a" added support for LS208xA devices but fixing iommu-map property is missing. This patch adds support for fixing iommu-map. Signed-off-by: Bharat Bhushan <Bharat.Bhushan(a)nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei(a)nxp.com> --- drivers/pci/pcie_layerscape_fixup.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 9e6c2f5..3dae201 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -130,19 +130,28 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie, u32 iommu_map[4]; int nodeoffset; int lenp; + uint svr; + char *compat = NULL; /* find pci controller node */ nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", pcie->dbi_res.start); if (nodeoffset < 0) { #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ - nodeoffset = fdt_node_offset_by_compat_reg(blob, - CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start); + svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; + if (svr == SVR_LS2088A || svr == SVR_LS2084A || + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) + compat = "fsl,ls2088a-pcie"; + else + compat = CONFIG_FSL_PCIE_COMPAT; + + if (compat) + nodeoffset = fdt_node_offset_by_compat_reg(blob, + compat, pcie->dbi_res.start); +#endif if (nodeoffset < 0) return; -#else - return; -#endif } /* get phandle to iommu controller */ -- 1.9.3

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[U-Boot] [PATCH 1/1] board/ls2080ardb: Remove CONFIG_DISPLAY_BOARDINFO_LATE
by Santan Kumar 25 Sep '17

25 Sep '17

CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay the prints of boardinfo late in cycle during uboot boot. This feature is not required in case of QSPI_BOOT. Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- This patch is split version of another patch https://patchwork.ozlabs.org/patch/779931/ include/configs/ls2080ardb.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 9b9a710..a5f7eea 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -18,7 +18,6 @@ #define CONFIG_QIXIS_I2C_ACCESS #endif #define CONFIG_SYS_I2C_EARLY_INIT -#define CONFIG_DISPLAY_BOARDINFO_LATE #endif #define I2C_MUX_CH_VOL_MONITOR 0xa -- 1.9.1

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[U-Boot] [PATCH] armv8: fsl-layerscape: Put SATA code under SATA configs
by Ashish Kumar 25 Sep '17

25 Sep '17

It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ddb7d82..a704103 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -215,11 +215,14 @@ int sata_init(void) { struct ccsr_ahci __iomem *ccsr_ahci; +#ifdef CONFIG_SYS_SATA2 ccsr_ahci = (void *)CONFIG_SYS_SATA2; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); +#endif +#ifdef CONFIG_SYS_SATA1 ccsr_ahci = (void *)CONFIG_SYS_SATA1; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); @@ -227,6 +230,7 @@ int sata_init(void) ahci_init((void __iomem *)CONFIG_SYS_SATA1); scsi_scan(false); +#endif return 0; } -- 2.7.4

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[U-Boot] [PATCH] armv7: ls1021a: Fix marco CONFIG_LS102XA
by York Sun 25 Sep '17

25 Sep '17

Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A to CONFIG_LS102XA. Signed-off-by: York Sun <york.sun(a)nxp.com> --- include/usb/ehci-ci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index cd3eb47..59bfc14 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -156,7 +156,7 @@ #elif defined(CONFIG_MPC85xx) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR -#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A) +#elif defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #endif -- 2.7.4

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[U-Boot] [PATCH v2 0/7] Enable falcon boot for LS1043ARDB
by York Sun 25 Sep '17

25 Sep '17

This is the 2nd version to enable falcon boot for LS1043ARDB. With SPL FIT patches merged, enabling falcon boot for this board is straight forward after fixing some errors introduced by other commits. Secure boot is dropped in this set due to SPL image size issue. Recent changes made the SPL image bigger and the secure boot image doesn't fit any more. A follow-up patch set will enable secure boot if the image can be future trimmed to fit. Changes in v2: New patch to fix spl after rebasing to latest master. New patch to fix compiling error after rebasing to latest mater. New patch to fix gd->ram_size error after rebasing to latest mater. Drop checking secure boot in this patch after rebasing to latest mater. Recent change in SPL makes the image size bigger. Relace getenv_f() with env_get_f() after rebasing to latet master. York Sun (7): spl: fix assignment of board info to global data cmd: spl: fix compiling error when CONFIG_CMD_SPL_WRITE_SIZE not defined armv8: fsl-layerscape: Avoid running dram_init_banksize again armv8: ls1043ardb: Use static DDR setting for SPL boot armv8: layerscape: Eanble falcon boot armv8: ls1043ardb: Enable spl_board_init() function armv8: ls1043ardb_sdcard: Enable falcon boot arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 18 ++- .../arm/cpu/armv8/fsl-layerscape/doc/README.falcon | 140 +++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/spl.c | 29 +++++ arch/arm/include/asm/system.h | 2 +- arch/arm/lib/spl.c | 11 ++ board/freescale/ls1043ardb/ddr.c | 46 +++++++ board/freescale/ls1043ardb/ddr.h | 67 ++++++++++ cmd/spl.c | 2 + common/spl/spl.c | 8 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 7 ++ include/configs/ls1043a_common.h | 7 +- include/configs/ls1043ardb.h | 11 +- 15 files changed, 342 insertions(+), 9 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon -- 2.7.4

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[U-Boot] [PATCH 1/6] mx6sabresd: Avoid calling setup_display() from SPL code
by Fabio Estevam 25 Sep '17

25 Sep '17

From: Fabio Estevam <fabio.estevam(a)nxp.com> There is no need call setup_display() from SPL code, so move it to board_init(), which executes only in U-Boot proper. Reported-by: Stefano Babic <sbabic(a)denx.de> Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- board/freescale/mx6sabresd/mx6sabresd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 5b50bc8..f14b759 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -620,9 +620,6 @@ int board_ehci_power(int port, int on) int board_early_init_f(void) { setup_iomux_uart(); -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); -#endif return 0; } @@ -639,6 +636,9 @@ int board_init(void) setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); else setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif #ifdef CONFIG_USB_EHCI_MX6 setup_usb(); #endif -- 2.7.4

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[U-Boot] [PATCH] sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operation
by Lukasz Majewski 25 Sep '17

25 Sep '17

The content of Bank Address Register (BAR) is volatile. It is cleared after power cycle or reset command (RESET F0h). Some memories (like e.g. s25fl256s) use it to access memory larger than 0x1000000 (16 MiB). The problem shows up when one: 1. Reads/writes/erases memory > 16 MiB 2. Calls "reset" u-boot command (which is not causing BAR to be cleared) In the above scenario, the SoC ROM sends 0x000000 address to read SPL. Unfortunately, the BA24 bit is still set and hence it receives content from 0x1000000 memory address. As a result the SoC aborts and we hang. Only power cycle can take the SoC out of this state. How to reproduce/test: sf probe; sf erase 0x1200000 0x800000; reset sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset sf probe; sf read 0x11000000 0x1200000 0x800000; reset Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- drivers/mtd/spi/spi_flash.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 34f6888..d19d64a 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -113,6 +113,27 @@ static int write_cr(struct spi_flash *flash, u8 wc) #endif #ifdef CONFIG_SPI_FLASH_BAR +/* + * This "cleanup" is necessary in a situation when one was accessing + * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. + * + * After it the BA24 bit shall be cleared to allow access to correct + * memory region after SW reset (by calling "reset" command). + * + * Otherwise, the BA24 bit may be left set and then after reset, the + * ROM would seek for SPL from 0x1000000, not 0x0. + */ +static int cleanup_bar(struct spi_flash *flash) +{ + u8 cmd, bank_sel = 0; + + if (flash->bank_curr == 0) + return 0; + cmd = flash->bank_write_cmd; + + return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); +} + static int write_bar(struct spi_flash *flash, u32 offset) { u8 cmd, bank_sel; @@ -339,6 +360,10 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) len -= erase_size; } +#ifdef CONFIG_SPI_FLASH_BAR + ret = cleanup_bar(flash); +#endif + return ret; } @@ -397,6 +422,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, offset += chunk_len; } +#ifdef CONFIG_SPI_FLASH_BAR + ret = cleanup_bar(flash); +#endif + return ret; } @@ -500,6 +529,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, data += read_len; } +#ifdef CONFIG_SPI_FLASH_BAR + ret = cleanup_bar(flash); +#endif + free(cmd); return ret; } -- 2.1.4

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[U-Boot] [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO
by Suresh Gupta 25 Sep '17

25 Sep '17

In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Signed-off-by: Suresh Gupta <suresh.gupta(a)nxp.com> Signed-off-by: Anupam Kumar <anupam.kumar_1(a)nxp.com> --- drivers/spi/fsl_qspi.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e61c67b..d596377 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -659,22 +659,20 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) tx_size = (len > TX_BUFFER_SIZE) ? TX_BUFFER_SIZE : len; - size = tx_size / 4; - for (i = 0; i < size; i++) { + size = tx_size / 16; + /* + * There must be atleast 128bit data + * available in TX FIFO for any pop operation + */ + if (tx_size % 16) + size++; + for (i = 0; i < size * 4; i++) { memcpy(&data, txbuf, 4); data = qspi_endian_xchg(data); qspi_write32(priv->flags, &regs->tbdr, data); txbuf += 4; } - size = tx_size % 4; - if (size) { - data = 0; - memcpy(&data, txbuf, size); - data = qspi_endian_xchg(data); - qspi_write32(priv->flags, &regs->tbdr, data); - } - qspi_write32(priv->flags, &regs->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) -- 1.9.3

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Re: [U-Boot] [PATCH 00/15] spl: atf: update booting images via ATF to use info from FIT images
by Michal Simek 25 Sep '17

25 Sep '17

Hi Philipp, On 13.9.2017 21:29, Philipp Tomsich wrote: > > A number of things about how we boot the RK3368 and RK3399 through ATF > are less than ideal today, especially when considering future > platforms that will follow a similar boot concept: > - the auto-detection of images from the FIT images was limited (i.e. > the start address of the BL33 image could not automatically retrieved) > - no implementation for the platform-specific parameters exists (and > there is a danger that we'll end up with highly different, proprietary > platform parameters for different SOCs and boards, even though the > ATF code base already has FDT support) > > This series tries to put us into a better position to support various > boot scenarios (e.g. loading an OPTEE from the FIT image; and: booting > a Linux kernel via ATF) in the future... and it establishes the FDT as > a mechanism to pass boot-info to later stages. > > For a practical example, refer to how we use this on the RK3399-Q7: > * the ATF can read the full U-Boot's FDT to determine how to best issue > a cold-reset for the board > * we inject information on where we loaded the M0 firmware into the > same FDT that is now visible to the ATF, so the ATF can relocate it > to its final destination---and we no longer need to overwrite parts > of the SPL binary during bootup > > Note that there are still some limitations (e.g. the support for > passing OPTEE as a BL3-2, is not in this version ... and there isn't > support for booting Linux directly via ATF yet, either), but these can > now be plugged cleanly into this infrastructure. can you please send also sent your bootlogs? I would like to see your flow also with pmu-firmware loading. Thanks, Michal

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