September 2017 - U-Boot

[U-Boot] [PATCH RESEND] DW SPI: Get clock value from Device Tree
by Eugeniy Paltsev 11 Oct '17

11 Oct '17

Add option to set spi controller clock frequency via device tree using standard clock bindings. Old way of setting spi controller clock frequency (via implementation of 'cm_get_spi_controller_clk_hz' function in platform specific code) remains supported. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev(a)synopsys.com> --- Resending due to previously sent one was discarded by mailing list. drivers/spi/designware_spi.c | 68 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 5aa507b..c70697e 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -11,6 +11,7 @@ */ #include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <malloc.h> @@ -94,6 +95,7 @@ struct dw_spi_priv { void __iomem *regs; unsigned int freq; /* Default frequency */ unsigned int mode; + unsigned long bus_clk_rate; int bits_per_word; u8 cs; /* chip select pin */ @@ -176,14 +178,78 @@ static void spi_hw_init(struct dw_spi_priv *priv) debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); } +/* + * cm_get_spi_controller_clk_hz function is old way to set spi controller + * frequency. If it isn't implemented and spi controller frequency isn't set via + * device tree we will get into next default function. + */ +__weak unsigned int cm_get_spi_controller_clk_hz(void) +{ + error("SPI clock is defined neither via device tree nor via cm_get_spi_controller_clk_hz!"); + + return 0; +} + +static int dw_spi_of_get_clk(struct udevice *bus) +{ +#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK) + struct dw_spi_priv *priv = dev_get_priv(bus); + unsigned long clk_rate; + struct clk clk; + int ret; + + ret = clk_get_by_index(bus, 0, &clk); + if (ret) + return -EINVAL; + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) + return ret; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) + return -EINVAL; + + priv->bus_clk_rate = clk_rate; + + clk_free(&clk); + + return 0; +#endif + + return -ENOSYS; +} + +static int dw_spi_get_clk(struct udevice *bus) +{ + struct dw_spi_priv *priv = dev_get_priv(bus); + + /* Firstly try to get clock frequency from device tree */ + if (!dw_spi_of_get_clk(bus)) + return 0; + + /* In case of failure rollback to cm_get_spi_controller_clk_hz */ + priv->bus_clk_rate = cm_get_spi_controller_clk_hz(); + + if (!priv->bus_clk_rate) + return -EINVAL; + + return 0; +} + static int dw_spi_probe(struct udevice *bus) { struct dw_spi_platdata *plat = dev_get_platdata(bus); struct dw_spi_priv *priv = dev_get_priv(bus); + int ret; priv->regs = plat->regs; priv->freq = plat->frequency; + ret = dw_spi_get_clk(bus); + if (ret) + return ret; + /* Currently only bits_per_word == 8 supported */ priv->bits_per_word = 8; @@ -369,7 +435,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed) spi_enable_chip(priv, 0); /* clk_div doesn't support odd number */ - clk_div = cm_get_spi_controller_clk_hz() / speed; + clk_div = priv->bus_clk_rate / speed; clk_div = (clk_div + 1) & 0xfffe; dw_writel(priv, DW_SPI_BAUDR, clk_div); -- 2.9.3

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[U-Boot] [PATCH] Powerpc: Make pcie link state judge more specific
by Bao Xiaowei 10 Oct '17

10 Oct '17

For some special reset times for longer pcie devices, in this case, the pcie device may on polling compliance state, the RC considers the pcie device is link up, but the pcie device is not link up, only the L0 state is link up state. So add the link up status judgement mechanisms. Signed-off-by: Bao Xiaowei <xiaowei.bao(a)nxp.com> --- v2: - Detailed function module - Adjust the code structure arch/powerpc/include/asm/fsl_pci.h | 3 + drivers/pci/fsl_pci_init.c | 151 ++++++++++++++++++++----------------- 2 files changed, 86 insertions(+), 68 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index cad341e..9dfbf19 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -24,6 +24,9 @@ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ +#define PCIE_GEN3_LTSSM_L0 0x11 /* L0 state */ +#define LTSSM_PCIE_DETECT_QUIET 0x00 /* Detect state */ +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* Detect state */ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index af20cf0..5d697bc 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) #endif +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 /* Setup one inbound ATMU window. * @@ -290,6 +292,81 @@ static void fsl_pcie_boot_master_release_slave(int port) } #endif +static int is_pcie_gen3(struct fsl_pci_info *pci_info) +{ + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; + u32 block_rev; + + block_rev = in_be32(&pci->block_rev1); + if (block_rev >= PEX_IP_BLK_REV_3_0) + return 1; + else + return 0; +} + +static int get_ltssm_val(struct pci_controller *hose, + struct fsl_pci_info *pci_info) +{ + u16 ltssm = 0; + pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; + + if (is_pcie_gen3(pci_info)) + ltssm = (in_be32(&pci->pex_csr0) + & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; + else + pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); + + return ltssm; +} + +static int pci_link_up(struct pci_controller *hose, + struct fsl_pci_info *pci_info) +{ + int enabled = 0; + u16 ltssm; + int i, pcie_ltssm_l0; + + if (is_pcie_gen3(pci_info)) + pcie_ltssm_l0 = PCIE_GEN3_LTSSM_L0; + else + pcie_ltssm_l0 = PCI_LTSSM_L0; + + ltssm = get_ltssm_val(hose, pci_info); + if (ltssm == LTSSM_PCIE_DETECT_QUIET || + ltssm == LTSSM_PCIE_DETECT_ACTIVE) + enabled = 0; + else if (ltssm == PCIE_GEN3_LTSSM_L0) + enabled = 1; + else { + for (i = 0; i < 100 && ltssm != pcie_ltssm_l0; i++) { + ltssm = get_ltssm_val(hose, pci_info); + udelay(1000); + } + enabled = (ltssm == pcie_ltssm_l0) ? 1 : 0; + } + return enabled; +} + +#if defined(CONFIG_FSL_PCIE_RESET) || \ + defined(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) +static void do_pcie_reset(struct fsl_pci_info *pci_info) +{ + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; + + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); + asm("sync;isync"); +} +#endif + void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) { u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; @@ -298,7 +375,6 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) u32 temp32; u32 block_rev; int enabled, r, inbound = 0; - u16 ltssm; u8 temp8, pcie_cap; int pcie_cap_pos; int pci_dcr; @@ -438,63 +514,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) udelay(1); #endif if (pcie_cap == PCI_CAP_ID_EXP) { - if (block_rev >= PEX_IP_BLK_REV_3_0) { -#define PEX_CSR0_LTSSM_MASK 0xFC -#define PEX_CSR0_LTSSM_SHIFT 2 - ltssm = (in_be32(&pci->pex_csr0) - & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; - enabled = (ltssm == 0x11) ? 1 : 0; #ifdef CONFIG_FSL_PCIE_RESET - int i; - /* assert PCIe reset */ - setbits_be32(&pci->pdb_stat, 0x08000000); - (void) in_be32(&pci->pdb_stat); - udelay(1000); - /* clear PCIe reset */ - clrbits_be32(&pci->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { - pci_hose_read_config_word(hose, dev, PCI_LTSSM, - &ltssm); - udelay(1000); - } + do_pcie_reset(pci_info); + pci_hose_write_config_dword(hose, dev, + PCI_BASE_ADDRESS_0, pcicsrbar); #endif - } else { - /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */ - /* enabled = ltssm >= PCI_LTSSM_L0; */ - pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); - enabled = ltssm >= PCI_LTSSM_L0; - -#ifdef CONFIG_FSL_PCIE_RESET - if (ltssm == 1) { - int i; - debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); - /* assert PCIe reset */ - setbits_be32(&pci->pdb_stat, 0x08000000); - (void) in_be32(&pci->pdb_stat); - udelay(100); - debug(" Asserting PCIe reset @%p = %x\n", - &pci->pdb_stat, in_be32(&pci->pdb_stat)); - /* clear PCIe reset */ - clrbits_be32(&pci->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { - pci_hose_read_config_word(hose, dev, PCI_LTSSM, - &ltssm); - udelay(1000); - debug("....PCIe link error. " - "LTSSM=0x%02x.\n", ltssm); - } - enabled = ltssm >= PCI_LTSSM_L0; - - /* we need to re-write the bar0 since a reset will - * clear it - */ - pci_hose_write_config_dword(hose, dev, - PCI_BASE_ADDRESS_0, pcicsrbar); - } -#endif - } + enabled = pci_link_up(hose, pci_info); #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { @@ -502,19 +527,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) temp32 = in_be32(&srds_regs->srdspccr0); if ((temp32 >> 28) == 3) { - int i; - out_be32(&srds_regs->srdspccr0, 2 << 28); - setbits_be32(&pci->pdb_stat, 0x08000000); - in_be32(&pci->pdb_stat); - udelay(100); - clrbits_be32(&pci->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { - pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); - udelay(1000); - } - enabled = ltssm >= PCI_LTSSM_L0; + do_pcie_reset(pci_info); + enabled = pci_link_up(hose, pci_info); } } #endif -- 2.7.4

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[U-Boot] [PATCH v2 1/2] fs/fat: Fix 'CACHE: Misaligned operation at range' warnings
by Tuomas Tynkkynen 09 Oct '17

09 Oct '17

The 'block' field of fat_itr needs to be properly aligned for DMA and while it does have '__aligned(ARCH_DMA_MINALIGN)', the fat_itr structure itself needs to be properly aligned as well. While at it use malloc_cache_aligned() for the other aligned allocations in the file as well. Fixes: 2460098cffacd1 ("fs/fat: Reduce stack usage") Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen(a)iki.fi> --- v2: No change --- fs/fat/fat.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 3d3e17e8fa..35941c1498 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -495,7 +495,7 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) return -1; } - block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz); + block = malloc_cache_aligned(cur_dev->blksz); if (block == NULL) { debug("Error: allocating block\n"); return -1; @@ -599,7 +599,7 @@ static int get_fs_info(fsdata *mydata) mydata->fatbufnum = -1; mydata->fat_dirty = 0; - mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE); + mydata->fatbuf = malloc_cache_aligned(FATBUFSIZE); if (mydata->fatbuf == NULL) { debug("Error: allocating memory\n"); return -1; @@ -1038,7 +1038,7 @@ int fat_exists(const char *filename) fat_itr *itr; int ret; - itr = malloc(sizeof(fat_itr)); + itr = malloc_cache_aligned(sizeof(fat_itr)); ret = fat_itr_root(itr, &fsdata); if (ret) return 0; @@ -1055,7 +1055,7 @@ int fat_size(const char *filename, loff_t *size) fat_itr *itr; int ret; - itr = malloc(sizeof(fat_itr)); + itr = malloc_cache_aligned(sizeof(fat_itr)); ret = fat_itr_root(itr, &fsdata); if (ret) return ret; @@ -1089,7 +1089,7 @@ int file_fat_read_at(const char *filename, loff_t pos, void *buffer, fat_itr *itr; int ret; - itr = malloc(sizeof(fat_itr)); + itr = malloc_cache_aligned(sizeof(fat_itr)); ret = fat_itr_root(itr, &fsdata); if (ret) return ret; -- 2.13.0

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[U-Boot] [PATCH] cmd: Make CMD_LZMA / CMD_UNZIP default y if CMD_BOOTI
by Tom Rini 09 Oct '17

09 Oct '17

In the Linux Kernel on ARM64, the Image.COMPRESSION file is not self-extracting in the way that x86 and ARM images are. So when CMD_BOOTI is enabled we should also default to enabling CMD_UNZIP and CONFIG_LZMA in order for the user to be able to decompress many of the common compressions that will be done to an Image file. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- cmd/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index d6d130edfa91..f923b0e421f7 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -526,6 +526,7 @@ menu "Compression commands" config CMD_LZMADEC bool "lzmadec" + default y if CMD_BOOTI select LZMA help Support decompressing an LZMA (Lempel-Ziv-Markov chain algorithm) @@ -533,6 +534,7 @@ config CMD_LZMADEC config CMD_UNZIP bool "unzip" + default y if CMD_BOOTI help Uncompress a zip-compressed memory region. -- 1.9.1

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[U-Boot] [PATCH] scripts: Move Kconfig contents to cmd/Kconfig
by Sam Protsenko 09 Oct '17

09 Oct '17

On case-insensitive file systems we have collision between scripts/kconfig/ directory and scripts/Kconfig file. This patch moves scripts/Kcofnig contents to cmd/Kconfig to fix that. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- Kconfig | 2 -- cmd/Kconfig | 3 +++ scripts/Kconfig | 2 -- 3 files changed, 3 insertions(+), 4 deletions(-) delete mode 100644 scripts/Kconfig diff --git a/Kconfig b/Kconfig index 238fa3e1ed..d951e9f804 100644 --- a/Kconfig +++ b/Kconfig @@ -398,5 +398,3 @@ source "fs/Kconfig" source "lib/Kconfig" source "test/Kconfig" - -source "scripts/Kconfig" diff --git a/cmd/Kconfig b/cmd/Kconfig index d6d130edfa..1db74f8f50 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -116,6 +116,9 @@ endmenu source "cmd/fastboot/Kconfig" +config BUILD_BIN2C + bool + comment "Commands" menu "Info commands" diff --git a/scripts/Kconfig b/scripts/Kconfig deleted file mode 100644 index 2a2c18e96e..0000000000 --- a/scripts/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config BUILD_BIN2C - bool -- 2.14.1

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[U-Boot] [PATCH v1 0/6] Update stm32x7 serial driver
by patrice.chotard＠st.com 09 Oct '17

09 Oct '17

From: Patrice Chotard <patrice.chotard(a)st.com> This series update the serial_stm32x7 driver used by both STM32F7 and STM32H7 SoCs : _ clean the code by using BIT and GENMASK macro _ remove useless CLK and OF_CONTROL flags _ add fifo support for H7 _ introduce STM32F4 support Currently, STM32F4 uses a dedicated serial driver drivers/serial/serial_stm32.c. whereas STM32F7 and STM32H7 uses drivers/serial/serial/serial_stm32x7.c . There is no reason to have 2 separate serial driver for STM32 SoCs family. It's the first step to prepare STM32F4 conversion to driver model and device tree support. Hence this conversion will be done, serial_stm32x7.c driver will support alls SoCs (ie F4/F7 and H7) it will be then renamed with the generic name serial_stm32.c Patrice Chotard (6): serial: stm32x7: cleanup code serial: stm32x7: remove stm32f7-usart and stm32h7-usart compatible serial: stm32x7: prepare the ground to STM32F4 support serial: stm32x7: add fifo support for STM32H7 serial: stm32x7: add STM32F4 support serial: stm32x7: remove useless CONFIG_CLK and OF_CONTROL flag arch/arm/dts/stm32h743.dtsi | 4 +- drivers/serial/Kconfig | 4 +- drivers/serial/serial_stm32x7.c | 84 ++++++++++++++++++++++------------------- drivers/serial/serial_stm32x7.h | 71 +++++++++++++++++++++++----------- 4 files changed, 99 insertions(+), 64 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 1/1] ARMv8: make master CPU checking logic more clear
by zijun_hu 09 Oct '17

09 Oct '17

From: zijun_hu <zijun_hu(a)htc.com> macro branch_if_master checks master CPU via (Aff3 & (Aff2:Aff1:Aff0)) it is simple but a little obscure. fix by checking Affx fields within MPIDR_EL1 directly. Signed-off-by: zijun_hu <zijun_hu(a)htc.com> --- arch/arm/include/asm/macro.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index e1916f7..0c8652a 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -131,6 +131,7 @@ lr .req x30 /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ mrs \xreg1, mpidr_el1 lsr \xreg2, \xreg1, #32 + lsl \xreg2, \xreg2, #32 lsl \xreg1, \xreg1, #40 lsr \xreg1, \xreg1, #40 orr \xreg1, \xreg1, \xreg2 -- 1.9.1

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[U-Boot] [PATCH v3 0/3] STiH410-B2260: update environment/configuration settings
by patrice.chotard＠st.com 09 Oct '17

09 Oct '17

From: Patrice Chotard <patrice.chotard(a)st.com> Update the CONFIG_EXTRA_ENV_SETTINGS, BOOT_TARGET_DEVICES and CONFIG_BOOTARGS Fix SDRAM size v3: fix typo in patch 2 v2: rebase on v2017.09 Lee Jones (1): board: STiH410-B2260: set ramdisk_addr_r to 0x48000000 Nicolas Le Bayon (1): board: STiH410-B2260: fix sdram size Patrice Chotard (1): board: STiH410-B2260: update environment variable configs/stih410-b2260_defconfig | 2 +- include/configs/stih410-b2260.h | 27 +++++++++++++++++++++++---- 2 files changed, 24 insertions(+), 5 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 1/1] ARMv8: fix error in freeing stack frame
by zijun_hu 09 Oct '17

09 Oct '17

From: zijun_hu <zijun_hu(a)htc.com> relocate_code() allocates 32 bytes stack frame but only 16 bytes are freed before return. it will cause errors to possible previous frames and doesn't make relocate_code() look like a function. fix by freeing 32 bytes stack space Signed-off-by: zijun_hu <zijun_hu(a)htc.com> --- arch/arm/lib/relocate_64.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index c7600537063f..fdba004363af 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -73,6 +73,6 @@ relocate_done: isb sy 4: ldp x0, x1, [sp, #16] bl __asm_flush_dcache_range -5: ldp x29, x30, [sp],#16 +5: ldp x29, x30, [sp],#32 ret ENDPROC(relocate_code) -- 1.9.1

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[U-Boot] [PATCH 1/1] ARMv8: get new GD address from gd->new_gd directly
by zijun_hu 09 Oct '17

09 Oct '17

From: zijun_hu <zijun_hu(a)htc.com> the new GD address is calculated via board data BD currently it require the new GD area locates below BD tightly, so a strict constraint is imposed on memory layout which maybe make special platform unpleasant. fix it by getting new GD address from gd->new_gd directly. Signed-off-by: zijun_hu <zijun_hu(a)htc.com> --- arch/arm/lib/crt0_64.S | 3 +-- lib/asm-offsets.c | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 62fad45..9c46c93 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -95,8 +95,7 @@ ENTRY(_main) */ ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */ bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - ldr x18, [x18, #GD_BD] /* x18 <- gd->bd */ - sub x18, x18, #GD_SIZE /* new GD is below bd */ + ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */ adr lr, relocation_return ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */ diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c index b04f7c6..f4f1bb8 100644 --- a/lib/asm-offsets.c +++ b/lib/asm-offsets.c @@ -38,5 +38,7 @@ int main(void) DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp)); + DEFINE(GD_NEW_GD, offsetof(struct global_data, new_gd)); + return 0; } -- 1.9.1

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