August 2017 - U-Boot

[U-Boot] [GIT PULL] Please pull u-boot-rockchip/master
by Dr. Philipp Tomsich 19 Aug '17

19 Aug '17

Tom, there's a (trivial) fix for some fallout from f94e643 (spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds) (and one unrelated trivial DTS change) in u-boot-rockchip/master ready for you. Please pull. Regards, Philipp. The following changes since commit 336aee50cf55d4d98ddf3a4412c18286e7f0a4c0: Merge git://git.denx.de/u-boot-tegra (2017-08-16 18:12:58 -0400) are available in the git repository at: git://git.denx.de/u-boot-rockchip.git master for you to fetch changes up to b5c4d81b3507b3abb239ea8323515fce09dc378f: spl: fix Makefile for NOR, XIP and YMODEM (2017-08-17 10:15:24 +0200) ---------------------------------------------------------------- Kever Yang (1): rockchip: dts: rk3399-firefly: update gmac parameter Philipp Tomsich (1): spl: fix Makefile for NOR, XIP and YMODEM arch/arm/dts/rk3399-firefly.dts | 4 ++-- common/spl/Makefile | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-)

2 1

[U-Boot] Initializing global_data on SuperH before board_init_f() ?
by Thomas Petazzoni 19 Aug '17

19 Aug '17

Hello, As you probably noticed with the few patches I sent late July, I am porting U-Boot to an old SH7786 platform. As part of this effort, I stumbled across a bug: the global_data structure is not initialized to zero by the SuperH architecture code before calling board_init_f(). The SuperH architecture code defines the global data in arch/sh/lib/start.S: mov.l ._gd_init, r13 /* global data */ [...] mov.l ._sh_generic_init, r0 jsr @r0 [...] ._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE) ._sh_generic_init: .long board_init_f So basically, it makes r13 points to the global data (which is expected on this architecture), and then calls board_init_f(). Hence, we enter board_init_f() with global_data uninitialized, which have caused me quite some troubles, as I was seeing semi-random behavior: in various places, we test if a pointer in global_data is NULL or not to decide to do something (or not). This obviously goes really bad when global_data contains garbage. Should we put global_data within the .bss section, so that it gets zero-initialized automatically? Should we zero-initialize it explicitly? I've currently worked-around the problem by adding a memset() to zero of the global_data at the beginning of board_init_f(), but I'd prefer to find an upstreamable fix. Thanks! Thomas Petazzoni -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com

3 4

[U-Boot] [PATCH 0/2] improve hello_world standalone application for arm
by Max Krummenacher 19 Aug '17

19 Aug '17

This series addresses - hardcoded entry address, use LOADADDR if available as the entry point instead - fix thumb build, jumping with 'go' to the entry point expects arm code Note that in addition to the two fixes I've seen random freezes or 'random' printed stuff when using an early linaro gcc 6 compiler. Adding an initialized variable helped in that case static int dummy_var_in_text = 1; I assume that this forces alignment of some linker sections. (e.g. I see that __bss_start points to 0x1201027e, with the variable this moves to 0x12010280) However with the current linaro compilers this does not happen so I don't propose a patch for this issue. Linaro GCC 5.4-2017.05 5.4.1 20170404 Linaro GCC 6.3-2017.05 6.3.1 20170404 Linaro GCC 7.1-2017.05 7.1.1 20170510 This series is available at http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next Max Krummenacher (2): arm: use $loadaddr as the standalone entry point hello_world.c: fix entry point in case of arm thumb binary arch/arm/config.mk | 4 ++++ doc/README.standalone | 2 +- examples/standalone/hello_world.c | 15 +++++++++++++++ 3 files changed, 20 insertions(+), 1 deletion(-) -- 2.13.1

3 19

[U-Boot] [PATCH v3 1/8] armv8: Add workaround for USB erratum A-009008
by Ran Wang 18 Aug '17

18 Aug '17

USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 1001 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- Change in v3: Use inline function to make code cleaner. Change in v2: In function erratum_a009008(): 1.Put a blank line after variable declaration. 2.Move common code together. arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 39 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5825f9b..300f5ce 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -22,6 +22,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -43,6 +44,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -79,6 +81,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009203 + select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F @@ -222,6 +225,10 @@ config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A010539 bool "Workaround for PIN MUX erratum A010539" +config SYS_FSL_ERRATUM_A009008 + bool "Workaround for USB PHY erratum A009008" + + config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" default 4 if ARCH_LS1043A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index aee1ffa..7e5288b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -52,6 +52,29 @@ bool soc_has_aiop(void) return false; } +static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) +{ + u32 val; + + val = scfg_in32(scfg + offset / 4) & ~(0xF << 6); + val |= USB_TXVREFTUNE << 6; + scfg_out32(scfg + offset / 4, val); +} + +static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); +#elif defined(CONFIG_ARCH_LS2080A) + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -198,6 +221,7 @@ void fsl_lsch3_early_init_f(void) #endif erratum_a008514(); erratum_a008336(); + erratum_a009008(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -473,6 +497,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009929(); erratum_a009660(); erratum_a010539(); + erratum_a009008(); } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f..62d7046 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -337,6 +337,12 @@ struct ccsr_gur { #define SCFG_USBPWRFAULT_USB2_SHIFT 2 #define SCFG_USBPWRFAULT_USB1_SHIFT 0 +#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR_USB1 0x070 +#define SCFG_USB3PRM1CR_USB2 0x07C +#define SCFG_USB3PRM1CR_USB3 0x088 +#define USB_TXVREFTUNE 0x9 + #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 59410aa..c622ee5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -133,6 +133,7 @@ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 #define SCFG_USB3PRM1CR_INIT 0x27672b2a +#define USB_TXVREFTUNE 0x9 #define SCFG_QSPICLKCTLR 0x10 #define TP_ITYP_AV 0x00000001 /* Initiator available */ -- 2.1.0.27.g96db324

4 12

[U-Boot] [PATCH] rockchip: rk322x: update MACRO for mmc clksel reg
by Kever Yang 18 Aug '17

18 Aug '17

The description for eMMC/SDIO/SDMMC src is not correct, update the CRU_CLKSEL11_CON value definition according to TRM. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h index 2a2f804..a7999ca 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -162,20 +162,17 @@ enum { /* CRU_CLKSEL11_CON */ EMMC_PLL_SHIFT = 12, EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, - EMMC_SEL_APLL = 0, - EMMC_SEL_DPLL, + EMMC_SEL_CPLL = 0, EMMC_SEL_GPLL, EMMC_SEL_24M, SDIO_PLL_SHIFT = 10, SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, - SDIO_SEL_APLL = 0, - SDIO_SEL_DPLL, + SDIO_SEL_CPLL = 0, SDIO_SEL_GPLL, SDIO_SEL_24M, MMC0_PLL_SHIFT = 8, MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, - MMC0_SEL_APLL = 0, - MMC0_SEL_DPLL, + MMC0_SEL_CPLL = 0, MMC0_SEL_GPLL, MMC0_SEL_24M, MMC0_DIV_SHIFT = 0, -- 1.9.1

2 3

[U-Boot] [PATCH 0/5] rockchip: rk3229: add sdram and sd support
by Kever Yang 18 Aug '17

18 Aug '17

Add sdram driver for rk3229 and other fix like pinctrl and sd node. Kever Yang (5): rockchip: rk322x: update dram bank size rockchip: rk322x: add sdram driver rockchip: dts: rk322x: add sdmmc device node rockchip: rk322x: pinctrl: using compatible name same with dts rockchip: dts: rk3229: remove dram channel info arch/arm/dts/rk3229-evb.dts | 13 +- arch/arm/dts/rk322x.dtsi | 62 ++ arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 581 +++++++++++++++ arch/arm/mach-rockchip/rk322x-board.c | 10 +- arch/arm/mach-rockchip/rk322x/Makefile | 1 + arch/arm/mach-rockchip/rk322x/sdram_rk322x.c | 855 ++++++++++++++++++++++ drivers/pinctrl/rockchip/pinctrl_rk322x.c | 8 +- 7 files changed, 1521 insertions(+), 9 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk322x.h create mode 100644 arch/arm/mach-rockchip/rk322x/sdram_rk322x.c -- 1.9.1

4 19

[U-Boot] [PATCH] rockchip: dts: rk3399-evb: remove redundant gmac node
by Kever Yang 18 Aug '17

18 Aug '17

There are two same gmac node, remove one. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/dts/rk3399-evb.dts | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index f5af75b..f33e165 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -264,19 +264,3 @@ rx_delay = <0x10>; status = "okay"; }; - -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x10>; - rx_delay = <0x10>; - status = "okay"; -}; -- 1.9.1

3 4

[U-Boot] [PATCH 1/3] rockchip: rk3399: detect boot mode
by Kever Yang 18 Aug '17

18 Aug '17

U-Boot fastboot, kernel may reboot with parameter which require bootloader to get into different boot mode, detect it and enter proper mode. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/mach-rockchip/rk3399/Kconfig | 1 + arch/arm/mach-rockchip/rk3399/rk3399.c | 42 +++++++++++++++++++++++++++++++++- 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 415466a..c4a6d46 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -5,6 +5,7 @@ choice config TARGET_EVB_RK3399 bool "RK3399 evaluation board" + select BOARD_LATE_INIT help RK3399evb is a evaluation board for Rockchp rk3399, with full function and phisical connectors support like type-C ports, diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 3484b28..d7a8aa6 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -5,9 +5,13 @@ */ #include <common.h> +#include <syscon.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> +#include <asm/arch/boot_mode.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3399.h> #include <asm/arch/hardware.h> +#include <asm/io.h> #define GRF_EMMCCORE_CON11 0xff77f02c @@ -53,3 +57,39 @@ int arch_cpu_init(void) return 0; } + +static void setup_boot_mode(void) +{ + struct rk3399_pmugrf_regs *pmugrf; + int boot_mode; + + pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + boot_mode = readl(&pmugrf->os_reg0); + debug("boot mode %x\n", boot_mode); + + /* Clear boot mode */ + writel(BOOT_NORMAL, &pmugrf->os_reg0); + + switch (boot_mode) { + case BOOT_FASTBOOT: + printf("enter fastboot!\n"); + setenv("preboot", "setenv preboot; fastboot usb0"); + break; + case BOOT_UMS: + printf("enter UMS!\n"); + setenv("preboot", "setenv preboot; if mmc dev 0;" + "then ums mmc 0; else ums mmc 1;fi"); + break; + case BOOT_LOADER: + printf("enter Rockusb!\n"); + setenv("preboot", "setenv preboot; rockusb 0 mmc 0"); + break; + } +} + +int board_late_init(void) +{ + setup_boot_mode(); + + return 0; +} -- 1.9.1

3 8

[U-Boot] [PATCH 0/3] rockchip: rv1108: support USB OTG and Host ports on evb-rv1108
by William Wu 18 Aug '17

18 Aug '17

This patch support USB OTG and Host ports on evb-rv1108 board. With this patch, we can use fastboot over USB and mount USB mass storage on OTG and Host ports. William Wu (3): configs: rockchip: add USB configs for evb-rv1108 board ARM: dts: rockchip: add USB nodes for evb-rv1108 rockchip: evb-rv1108: add usb init function for dwc2 gadget arch/arm/dts/rv1108-evb.dts | 22 ++++++++++++++++ arch/arm/dts/rv1108.dtsi | 24 +++++++++++++++++ board/rockchip/evb_rv1108/evb_rv1108.c | 47 ++++++++++++++++++++++++++++++++++ configs/evb-rv1108_defconfig | 22 ++++++++++++++++ include/configs/rv1108_common.h | 3 +++ 5 files changed, 118 insertions(+) -- 2.0.0

2 6

[U-Boot] [PATCH v2] rockchip: phycore: Read configuration EEPROM & set ethaddr in late init
by Wadim Egorov 18 Aug '17

18 Aug '17

Read SoM information from EEPROM and set ethaddr in late init. Signed-off-by: Wadim Egorov <w.egorov(a)phytec.de> --- Changes in v2: - Fixed fdt_path_offset() error handling --- board/phytec/phycore_rk3288/phycore-rk3288.c | 62 ++++++++++++++++++++++++++++ board/phytec/phycore_rk3288/som.h | 21 ++++++++++ configs/phycore-rk3288_defconfig | 2 + 3 files changed, 85 insertions(+) create mode 100644 board/phytec/phycore_rk3288/som.h diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index 20696f6..1b60be9 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -5,4 +5,66 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <asm/io.h> #include <common.h> +#include <dm.h> +#include <i2c.h> +#include <i2c_eeprom.h> +#include <netdev.h> +#include "som.h" + +static int valid_rk3288_som(struct rk3288_som *som) +{ + unsigned char *p = (unsigned char *)som; + unsigned char *e = p + sizeof(struct rk3288_som) - 1; + int hw = 0; + + while (p < e) { + hw += hweight8(*p); + p++; + } + + return hw == som->bs; +} + +int rk_board_late_init(void) +{ + int ret; + struct udevice *dev; + struct rk3288_som opt; + int off; + + /* Get the identificatioin page of M24C32-D EEPROM */ + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); + if (off < 0) { + printf("%s: No eeprom0 path offset\n", __func__); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + printf("%s: Could not find EEPROM\n", __func__); + return ret; + } + + ret = i2c_set_chip_offset_len(dev, 2); + if (ret) + return ret; + + ret = i2c_eeprom_read(dev, 0, (uint8_t *)&opt, + sizeof(struct rk3288_som)); + if (ret) { + printf("%s: Could not read EEPROM\n", __func__); + return ret; + } + + if (opt.api_version != 0 || !valid_rk3288_som(&opt)) { + printf("Invalid data or wrong EEPROM layout version.\n"); + /* Proceed anyway, since there is no fallback option */ + } + + if (is_valid_ethaddr(opt.mac)) + eth_setenv_enetaddr("ethaddr", opt.mac); + + return 0; +} diff --git a/board/phytec/phycore_rk3288/som.h b/board/phytec/phycore_rk3288/som.h new file mode 100644 index 0000000..1b7f9a1 --- /dev/null +++ b/board/phytec/phycore_rk3288/som.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov(a)phytec.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * rk3288_som struct represents the eeprom layout for PHYTEC RK3288 based SoMs + */ +struct rk3288_som { + unsigned char api_version; /* EEPROM layout API version */ + unsigned char mod_version; /* PCM/PFL/PCA */ + unsigned char option[12]; /* coding for variants */ + unsigned char som_rev; /* SOM revision */ + unsigned char mac[6]; + unsigned char ksp; /* 1: KSP, 2: KSM */ + unsigned char kspno; /* Number for KSP/KSM module */ + unsigned char reserved[8]; /* not used */ + unsigned char bs; /* Bits set in previous bytes */ +} __attribute__ ((__packed__)); diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 618d983..4e016fe 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -43,6 +43,8 @@ CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_DM_ETH=y -- 1.9.1

3 6