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July 2017

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[U-Boot] [PATCH v4] powerpc, 8xx: Add support for MCR3000 board from CSSI
by Christophe Leroy 09 Jul '17

09 Jul '17

CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000 and CMPC885 which are respectively based on MPC866 and MPC885 processors. This patch adds support for the first board. Signed-off-by: Christophe Leroy <christophe.leroy(a)c-s.fr> --- v4: Takes into account additional comments from Wolfgang v3: Takes into account comments received from Heiko and Wolfgang Applies after the v2 serie 'powerpc, 8xx: Modernise the 8xx' .travis.yml | 2 + arch/powerpc/cpu/mpc8xx/Kconfig | 5 ++ board/cssi/MAINTAINERS | 6 ++ board/cssi/MCR3000/Kconfig | 15 ++++ board/cssi/MCR3000/MCR3000.c | 144 ++++++++++++++++++++++++++++++++++++ board/cssi/MCR3000/Makefile | 10 +++ board/cssi/MCR3000/nand.c | 65 +++++++++++++++++ board/cssi/MCR3000/u-boot.lds | 91 +++++++++++++++++++++++ configs/MCR3000_defconfig | 88 ++++++++++++++++++++++ drivers/net/mpc8xx_fec.c | 20 +++++ include/configs/MCR3000.h | 158 ++++++++++++++++++++++++++++++++++++++++ 11 files changed, 604 insertions(+) create mode 100644 board/cssi/MAINTAINERS create mode 100644 board/cssi/MCR3000/Kconfig create mode 100644 board/cssi/MCR3000/MCR3000.c create mode 100644 board/cssi/MCR3000/Makefile create mode 100644 board/cssi/MCR3000/nand.c create mode 100644 board/cssi/MCR3000/u-boot.lds create mode 100644 configs/MCR3000_defconfig create mode 100644 include/configs/MCR3000.h diff --git a/.travis.yml b/.travis.yml index 6f14ec2396..226c8313b1 100644 --- a/.travis.yml +++ b/.travis.yml @@ -210,6 +210,8 @@ matrix: - env: - BUILDMAN="mpc86xx" - env: + - BUILDMAN="mpc8xx" + - env: - BUILDMAN="siemens" - env: - BUILDMAN="tegra" diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index 9e1ad33c28..5a7db335ed 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -8,6 +8,9 @@ choice prompt "Target select" optional +config TARGET_MCR3000 + bool "Support MCR3000 board from CSSI" + endchoice choice @@ -167,4 +170,6 @@ config SYS_OR7_PRELIM config SYS_IMMR hex "Value for IMMR" +source "board/cssi/MCR3000/Kconfig" + endmenu diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS new file mode 100644 index 0000000000..cbf1406a54 --- /dev/null +++ b/board/cssi/MAINTAINERS @@ -0,0 +1,6 @@ +BOARDS from CS Systemes d'Information +M: Christophe Leroy <christophe.leroy(a)c-s.fr> +S: Maintained +F: board/cssi/ +F: include/configs/MCR3000.h +F: configs/MCR3000_defconfig diff --git a/board/cssi/MCR3000/Kconfig b/board/cssi/MCR3000/Kconfig new file mode 100644 index 0000000000..ecfd90fd4c --- /dev/null +++ b/board/cssi/MCR3000/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MCR3000 + +config SYS_BOARD + default "MCR3000" + +config SYS_VENDOR + default "cssi" + +config SYS_CONFIG_NAME + default "MCR3000" + +config SYS_TEXT_BASE + default 0x04000000 + +endif diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c new file mode 100644 index 0000000000..43c4cb77bb --- /dev/null +++ b/board/cssi/MCR3000/MCR3000.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2010-2017 CS Systemes d'Information + * Florent Trinh Thai <florent.trinh-thai(a)c-s.fr> + * Christophe Leroy <christophe.leroy(a)c-s.fr> + * + * Board specific routines for the MCR3000 board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <hwconfig.h> +#include <mpc8xx.h> +#include <fdt_support.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const uint cs1_dram_table_66[] = { + /* DRAM - single read. (offset 0 in upm RAM) */ + 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400, + 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* DRAM - burst read. (offset 8 in upm RAM) */ + 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00, + 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* DRAM - single write. (offset 18 in upm RAM) */ + 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804, + 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, + + /* DRAM - burst write. (offset 20 in upm RAM) */ + 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00, + 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404, + 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* refresh (offset 30 in upm RAM) */ + 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04, + 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF, + + /* init */ + 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF, + + /* exception. (offset 3c in upm RAM) */ + 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +}; + +int ft_board_setup(void *blob, bd_t *bd) +{ + const char *sync = "receive"; + + ft_cpu_setup(blob, bd); + + /* BRG */ + do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", + bd->bi_busfreq, 1); + + /* MAC addr */ + fdt_fixup_ethernet(blob); + + /* Bus Frequency for CPM */ + do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1); + + /* E1 interface - Set data rate */ + do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1); + + /* E1 interface - Set channel phase to 0 */ + do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1); + + /* E1 interface - rising edge sync pulse transmit */ + do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse", + sync, strlen(sync), 1); + + return 0; +} + +int checkboard(void) +{ + serial_puts("BOARD: MCR3000 CSSI\n"); + + return 0; +} + +int dram_init(void) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + memctl8xx_t __iomem *memctl = &immap->im_memctl; + + printf("UPMA init for SDRAM (CAS latency 2), "); + printf("init address 0x%08x, size ", (int)dram_init); + /* Configure UPMA for cs1 */ + upmconfig(UPMA, (uint *)cs1_dram_table_66, + sizeof(cs1_dram_table_66) / sizeof(uint)); + udelay(10); + out_be16(&memctl->memc_mptpr, 0x0200); + out_be32(&memctl->memc_mamr, 0x14904000); + udelay(10); + out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM); + out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM); + udelay(10); + out_be32(&memctl->memc_mcr, 0x80002830); + out_be32(&memctl->memc_mar, 0x00000088); + out_be32(&memctl->memc_mcr, 0x80002038); + udelay(200); + + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + SDRAM_MAX_SIZE); + + return 0; +} + +int misc_init_r(void) +{ + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; + iop8xx_t __iomem *iop = &immr->im_ioport; + + /* Set port C13 as GPIO (BTN_ACQ_AL) */ + clrbits_be16(&iop->iop_pcpar, 0x4); + clrbits_be16(&iop->iop_pcdir, 0x4); + + /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */ + if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0) + setenv("bootdelay", "60"); + + return 0; +} + +int board_early_init_f(void) +{ + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; + + /* + * Erase FPGA(s) for reboot + */ + clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */ + setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */ + udelay(1); /* Wait more than 300ns */ + setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */ + + return 0; +} diff --git a/board/cssi/MCR3000/Makefile b/board/cssi/MCR3000/Makefile new file mode 100644 index 0000000000..401d5aa4c1 --- /dev/null +++ b/board/cssi/MCR3000/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2010-2017 CS Systemes d'Information +# Christophe Leroy <christophe.leroy(a)c-s.fr> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# + +obj-y += MCR3000.o +obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/cssi/MCR3000/nand.c b/board/cssi/MCR3000/nand.c new file mode 100644 index 0000000000..8e5b0d0618 --- /dev/null +++ b/board/cssi/MCR3000/nand.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2010-2017 CS Systemes d'Information + * Florent Trinh Thai <florent.trinh-thai(a)c-s.fr> + * Christophe Leroy <christophe.leroy(a)c-s.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <nand.h> +#include <asm/io.h> + +#define BIT_CLE ((unsigned short)0x0800) +#define BIT_ALE ((unsigned short)0x0400) +#define BIT_NCE ((unsigned short)0x1000) + +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtdinfo->priv; + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; + unsigned short pddat = 0; + + /* The hardware control change */ + if (ctrl & NAND_CTRL_CHANGE) { + pddat = in_be16(&immr->im_ioport.iop_pddat); + + /* Clearing ALE and CLE */ + pddat &= ~(BIT_CLE | BIT_ALE); + + /* Driving NCE pin */ + if (ctrl & NAND_NCE) + pddat &= ~BIT_NCE; + else + pddat |= BIT_NCE; + + /* Driving CLE and ALE pin */ + if (ctrl & NAND_CLE) + pddat |= BIT_CLE; + if (ctrl & NAND_ALE) + pddat |= BIT_ALE; + + out_be16(&immr->im_ioport.iop_pddat, pddat); + } + + /* Writing the command */ + if (cmd != NAND_CMD_NONE) + out_8(this->IO_ADDR_W, cmd); +} + +int board_nand_init(struct nand_chip *nand) +{ + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; + + /* Set GPIO Port */ + setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00); + clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00); + clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000); + + nand->chip_delay = 60; + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = nand_hwcontrol; + + return 0; +} diff --git a/board/cssi/MCR3000/u-boot.lds b/board/cssi/MCR3000/u-boot.lds new file mode 100644 index 0000000000..cd042ca0ce --- /dev/null +++ b/board/cssi/MCR3000/u-boot.lds @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2010-2017 CS Systemes d'Information + * Christophe Leroy <christophe.leroy(a)c-s.fr> + * + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Modified by Yuli Barcohen <yuli(a)arabellasw.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .text : + { + arch/powerpc/cpu/mpc8xx/start.o (.text) + arch/powerpc/cpu/mpc8xx/start.o (.text*) + arch/powerpc/cpu/mpc8xx/traps.o (.text*) + arch/powerpc/cpu/mpc8xx/built-in.o (.text*) + arch/powerpc/lib/built-in.o (.text*) + board/cssi/MCR3000/built-in.o (.text*) + disk/built-in.o (.text*) + drivers/net/built-in.o (.text*) + + *(.text) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + } + __bss_end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig new file mode 100644 index 0000000000..562face283 --- /dev/null +++ b/configs/MCR3000_defconfig @@ -0,0 +1,88 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_MCR3000=y +CONFIG_BOOTDELAY=5 +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_NET=y +CONFIG_CMD_DHCP=y +# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set +# CONFIG_MMC is not set +CONFIG_MTD_NOR_FLASH=y +# CONFIG_PCI is not set +CONFIG_OF_LIBFDT=y +CONFIG_SYS_PROMPT="S3K> " +CONFIG_NETDEVICES=y +CONFIG_MPC8XX_FEC=y + +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_MD5SUM is not set +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_SETGETDCR is not set +# CONFIG_CMD_SHA1 is not set +# CONFIG_CMD_SOURCE is not set +CONFIG_CMD_IMMAP=y + +CONFIG_SYS_IMMR=0xFF000000 + +CONFIG_SYS_OR0_PRELIM=0xFFC00926 +CONFIG_SYS_BR0_PRELIM=0x04000801 +CONFIG_SYS_BR1_PRELIM_BOOL=y +CONFIG_SYS_BR1_PRELIM=0x00000081 +CONFIG_SYS_OR1_PRELIM=0xFE000E00 +CONFIG_SYS_BR2_PRELIM_BOOL=y +CONFIG_SYS_BR2_PRELIM=0x08000801 +CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A +CONFIG_SYS_BR3_PRELIM_BOOL=y +CONFIG_SYS_BR3_PRELIM=0x0C000401 +CONFIG_SYS_OR3_PRELIM=0xFFFF8142 +CONFIG_SYS_BR4_PRELIM_BOOL=y +CONFIG_SYS_BR4_PRELIM=0x10000801 +CONFIG_SYS_OR4_PRELIM=0xFFFF8D08 +CONFIG_SYS_BR5_PRELIM_BOOL=y +CONFIG_SYS_BR5_PRELIM=0x14000801 +CONFIG_SYS_OR5_PRELIM=0xFFFF8916 +CONFIG_SYS_BR6_PRELIM_BOOL=y +CONFIG_SYS_BR6_PRELIM=0x18000801 +CONFIG_SYS_OR6_PRELIM=0xFFFF0908 +CONFIG_SYS_BR7_PRELIM_BOOL=y +CONFIG_SYS_BR7_PRELIM=0x1C000001 +CONFIG_SYS_OR7_PRELIM=0xFFFF810A + +CONFIG_8xx_GCLK_FREQ=132000000 + +CONFIG_SYS_SYPCR=0xFFFFFF8F +CONFIG_SYS_SIUMCR=0x00600400 +CONFIG_SYS_TBSCR=0x00C3 +CONFIG_SYS_PISCR=0x0000 +CONFIG_SYS_PLPRCR_BOOL=y +CONFIG_SYS_PLPRCR=0x00460004 +CONFIG_SYS_SCCR_MASK=0x60000000 +CONFIG_SYS_SCCR=0x00C20000 +CONFIG_SYS_DER=0x2002000F + +CONFIG_AUTOBOOT=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n" +CONFIG_AUTOBOOT_DELAY_STR="root" + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_LZMA=y +CONFIG_SHA256=y + diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c index b070d6696a..e525d3b593 100644 --- a/drivers/net/mpc8xx_fec.c +++ b/drivers/net/mpc8xx_fec.c @@ -413,6 +413,26 @@ static void fec_pin_init(int fecidx) */ out_be16(&immr->im_ioport.iop_pdpar, 0x1fff); out_be16(&immr->im_ioport.iop_pddir, 0x1fff); + +#if defined(CONFIG_TARGET_MCR3000) + out_be16(&immr->im_ioport.iop_papar, 0xBBFF); + out_be16(&immr->im_ioport.iop_padir, 0x04F0); + out_be16(&immr->im_ioport.iop_paodr, 0x0000); + + out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF); + out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F); + out_be16(&immr->im_cpm.cp_pbodr, 0x0000); + + out_be16(&immr->im_ioport.iop_pcpar, 0x0400); + out_be16(&immr->im_ioport.iop_pcdir, 0x0080); + out_be16(&immr->im_ioport.iop_pcso , 0x0D53); + out_be16(&immr->im_ioport.iop_pcint, 0x0000); + + out_be16(&immr->im_ioport.iop_pdpar, 0x03FE); + out_be16(&immr->im_ioport.iop_pddir, 0x1C09); + + setbits_be32(&immr->im_ioport.utmode, 0x80); +#endif #endif #endif /* CONFIG_ETHER_ON_FEC1 */ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h new file mode 100644 index 0000000000..15bb0e9d6a --- /dev/null +++ b/include/configs/MCR3000.h @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2010-2017 CS Systemes d'Information + * Christophe Leroy <christophe.leroy(a)c-s.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "sdram_type=SDRAM\0" \ + "flash_type=AM29LV160DB\0" \ + "loadaddr=0x400000\0" \ + "filename=uImage.lzma\0" \ + "nfsroot=/opt/ofs\0" \ + "dhcp_ip=ip=:::::eth0:dhcp\0" \ + "console_args=console=ttyCPM0,115200N8\0" \ + "flashboot=setenv bootargs " \ + "${console_args} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "mcr3k:eth0:off;" \ + "${ofl_args}; " \ + "bootm 0x04060000 - 0x04050000\0" \ + "tftpboot=setenv bootargs " \ + "${console_args} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "mcr3k:eth0:off " \ + "${ofl_args}; " \ + "tftp ${loadaddr} ${filename};" \ + "tftp 0xf00000 mcr3000.dtb;" \ + "bootm ${loadaddr} - 0xf00000\0" \ + "netboot=dhcp ${loadaddr} ${filename};" \ + "tftp 0xf00000 mcr3000.dtb;" \ + "setenv bootargs " \ + "root=/dev/nfs rw " \ + "${console_args} " \ + "${dhcp_ip};" \ + "bootm ${loadaddr} - 0xf00000\0" \ + "nfsboot=setenv bootargs " \ + "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \ + "${console_args} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "mcr3k:eth0:off;" \ + "bootm 0x04060000 - 0x04050000\0" \ + "dhcpboot=dhcp ${loadaddr} ${filename};" \ + "tftp 0xf00000 mcr3000.dtb;" \ + "setenv bootargs " \ + "${console_args} " \ + "${dhcp_ip} " \ + "${ofl_args}; " \ + "bootm ${loadaddr} - 0xf00000\0" + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_IPADDR 192.168.0.3 +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_NETMASK 255.0.0.0 + +#define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_BOOTARGS "ubi.mtd=4 root=ubi0:rootfs rw " \ + "rootfstype=ubifs rootflags=sync " \ + "console=ttyCPM0,115200N8 " \ + "ip=${ipaddr}:::${netmask}:mcr3k:eth0:off" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CONFIG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_WATCHDOG 1 /* watchdog enabled */ + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMDLINE_EDITING 1 +#ifdef CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "S3K> " +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00002000 +#define CONFIG_SYS_MEMTEST_END 0x00800000 + +#define CONFIG_SYS_LOAD_ADDR 0x200000 + +#define CONFIG_SYS_HZ 1000 + +/* Definitions for initial stack pointer and data area (in DPRAM) */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 +#define CONFIG_SYS_GBL_DATA_SIZE 64 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define SDRAM_MAX_SIZE (32 * 1024 * 1024) + +/* FLASH organization */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 35 +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN (4096 << 10) + +/* Environment Configuration */ + +/* environment is in FLASH */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +#define CONFIG_ENV_OVERWRITE 1 + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +/* Ethernet configuration part */ +#define CONFIG_SYS_DISCOVER_PHY 1 +#ifdef CONFIG_MPC8XX_FEC +#define CONFIG_MII_INIT 1 +#endif + +/* NAND configuration part */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x0C000000 + +/* Internal Definitions */ + +/* Boot Flags*/ +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +/* Misc Settings */ +#define CONFIG_CMD_REGINFO + +#endif /* __CONFIG_H */ -- 2.12.0

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[U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx
by Christophe Leroy 09 Jul '17

09 Jul '17

This patchset modernises the resurrected 8xx. Christophe Leroy (10): powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/ powerpc, 8xx: move specific reginfo powerpc, 8xx: Use IO accessors to access IO memory powerpc, 8xx: Implement GLL2 ERRATA powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks powerpc, 8xx: Properly set CPM frequency in the device tree powerpc, 8xx: Migrate to Kconfig powerpc, 8xx: move FEC Ethernet driver in drivers/net powerpc, 8xx: move SPI driver to drivers/spi/ powerpc, 8xx: move Serial driver to drivers/serial/ README | 49 --- arch/powerpc/Kconfig | 2 - arch/powerpc/cpu/mpc8xx/Kconfig | 157 ++++++++ arch/powerpc/cpu/mpc8xx/Makefile | 5 +- arch/powerpc/cpu/mpc8xx/cpu.c | 183 ++++----- arch/powerpc/cpu/mpc8xx/cpu_init.c | 112 +++--- arch/powerpc/cpu/mpc8xx/fdt.c | 10 +- arch/powerpc/cpu/mpc8xx/immap.c | 380 ++++++++++++++++++ arch/powerpc/cpu/mpc8xx/interrupts.c | 121 +++--- arch/powerpc/cpu/mpc8xx/reginfo.c | 70 ++++ arch/powerpc/cpu/mpc8xx/serial.c | 301 -------------- arch/powerpc/cpu/mpc8xx/speed.c | 39 +- arch/powerpc/cpu/mpc8xx/traps.c | 37 +- arch/powerpc/include/asm/iopin_8xx.h | 441 +++++++++++++-------- arch/powerpc/include/asm/ppc.h | 5 - arch/powerpc/lib/Kconfig | 7 - arch/powerpc/lib/Makefile | 1 - arch/powerpc/lib/immap.c | 397 ------------------- arch/powerpc/lib/time.c | 7 +- cmd/reginfo.c | 54 +-- drivers/i2c/soft_i2c.c | 2 +- drivers/net/Kconfig | 58 +++ drivers/net/Makefile | 1 + .../cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c | 369 +++++++++-------- drivers/serial/Kconfig | 53 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_mpc8xx.c | 256 ++++++++++++ drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + .../cpu/mpc8xx/spi.c => drivers/spi/mpc8xx_spi.c | 212 +++++----- include/commproc.h | 12 +- include/watchdog.h | 2 +- scripts/config_whitelist.txt | 22 - 33 files changed, 1778 insertions(+), 1595 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xx/immap.c create mode 100644 arch/powerpc/cpu/mpc8xx/reginfo.c delete mode 100644 arch/powerpc/cpu/mpc8xx/serial.c delete mode 100644 arch/powerpc/lib/Kconfig delete mode 100644 arch/powerpc/lib/immap.c rename arch/powerpc/cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c (62%) create mode 100644 drivers/serial/serial_mpc8xx.c rename arch/powerpc/cpu/mpc8xx/spi.c => drivers/spi/mpc8xx_spi.c (62%) -- 2.12.0

6 34

[U-Boot] [PATCH v2b 04/10] powerpc, 8xx: Implement GLL2 ERRATA
by Christophe Leroy 09 Jul '17

09 Jul '17

Signed-off-by: Christophe Leroy <christophe.leroy(a)c-s.fr> --- Takes into account comments received from Wolfgang and Heiko. Superseeds the one included in v2 of the serie 'powerpc, 8xx: Modernise the 8xx'. Not resending the entire serie. arch/powerpc/cpu/mpc8xx/cpu_init.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index cf1280983a..a51596a583 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -51,6 +51,26 @@ void cpu_init_f(immap_t __iomem *immr) clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK, CONFIG_SYS_SCCR); + /* + * MPC866/885 ERRATA GLL2 + * Description: + * In 1:2:1 mode, when HRESET is detected at the positive edge of + * EXTCLK, then there will be a loss of phase between + * EXTCLK and CLKOUT. + * + * Workaround: + * Reprogram the SCCR: + * 1. Write 1'b00 to SCCR[EBDF]. + * 2. Write 1'b01 to SCCR[EBDF]. + * 3. Rewrite the desired value to the PLPRCR register. + */ + reg = in_be32(&immr->im_clkrst.car_sccr); + /* Are we in mode 1:2:1 ? */ + if ((reg & SCCR_EBDF11) == SCCR_EBDF01) { + clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11); + setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01); + } + /* PLL (CPU clock) settings (15-30) */ out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY); -- 2.12.0

4 3

[U-Boot] [PATCH v6] powerpc: Partialy restore core of mpc8xx
by Christophe Leroy 09 Jul '17

09 Jul '17

CS Systemes d'Information (CSSI) manufactures 8xx boards for critical communication systems. Those boards have been running U-Boot since 2010 and will have to be maintained until at least 2027. commit 5b8e76c35ec312a3f73126bd1a2d2c0965b98a9f ("powerpc, 8xx: remove support for 8xx") orphaned those boards by removing support for the mpc8xx CPU. This commit partially restores support for the 8xx, with the following limitations: - Restores support for MPC866 and MPC885 only - Does not restore IDE, PCMCIA, I2C, USB - Does not restore examples - Does not restore POST - Does not restore Ethernet on SCC - Does not restore console on SCC - Does not restore bedbug and kgdb support As the 866 and 885 do not support the following features, they are not restored either: - VIDEO / LCD - RTC clock The CPM uCODE patch is not restored either, because: - 866 and 885 already have support for I2C and SPI relocation without a uCODE patch - relocation of SMC, I2C or SPI is only needed for using SCCs for Ethernet or QMC The dynamic setup/calculation of clocks is removed, we expect the target being use with the clock and PLPRCR register defined in the configuration. All the clock settings for 8xx prior to 866 is removed as well as we now only support 866 and 885. This code is mature and addresses mature boards. Therefore all code enclosed in '#if 0/#endif' and '#if XX_DEBUG/#endif' is unneeded. The following files are not restored by this patch: - arch/powerpc/cpu/mpc8xx/bedbug_860.c - arch/powerpc/cpu/mpc8xx/fec.h - arch/powerpc/cpu/mpc8xx/kgdb.S - arch/powerpc/cpu/mpc8xx/plprcr_write.S - arch/powerpc/cpu/mpc8xx/scc.c - arch/powerpc/cpu/mpc8xx/upatch.c - arch/powerpc/cpu/mpc8xx/video.c - arch/powerpc/include/asm/status_led.h - arch/powerpc/lib/ide.c - arch/powerpc/lib/ide.h - doc/README.MPC866 - drivers/pcmcia/mpc8xx_pcmcia.c - drivers/rtc/mpc8xx.c - drivers/usb/gadget/mpc8xx_udc.c - drivers/video/mpc8xx_lcd.c - examples/standalone/test_burst.c - examples/standalone/test_burst.h - examples/standalone/test_burst_lib.S - examples/standalone/timer.c - include/mpc823_lcd.h - include/usb/mpc8xx_udc.h - post/cpu/mpc8xx/Makefile - post/cpu/mpc8xx/cache.c - post/cpu/mpc8xx/cache_8xx.S - post/cpu/mpc8xx/ether.c - post/cpu/mpc8xx/spr.c - post/cpu/mpc8xx/uart.c - post/cpu/mpc8xx/usb.c - post/cpu/mpc8xx/watchdog.c Some of the restored files are not located in a proper location. In order to keep traceability of the changes, they will be moved to their correct location and moved to Kconfig in a followup patch. This patch also declares CSSI as point of contact for the update of the 8xx platform, as those boards are the only ones still being maintained on the 8xx area. A later patch will add those boards to the tree. Signed-off-by: Christophe Leroy <christophe.leroy(a)c-s.fr> --- v6: Removed travis-CI setup as it fails due to lack of board. Will be added back with the board. Removed SCC console. Keep only 866 and 885 in check_CPU(). Removed commands that just print 'not implemented' from immap.c. Removed code enclosed in #if 0/#endif . v5: Only restore the needed parts. v4: Restored some common CONFIG_ removed by 5xx removal in README and config_whitelist Removed all impacts on 4xx; Removed a few remaining references to 82xx Fixed unbalanced #ifdef in i2c v3: Fixed build error in arch/powerpc/include/asm/ppc.h ; removed commproc.h from 4xx v2: Tom squashed patches 1-10 of the serie MAINTAINERS | 2 +- README | 62 ++- api/api_platform-powerpc.c | 2 +- arch/powerpc/Kconfig | 6 + arch/powerpc/cpu/mpc8xx/Kconfig | 13 + arch/powerpc/cpu/mpc8xx/Makefile | 17 + arch/powerpc/cpu/mpc8xx/config.mk | 8 + arch/powerpc/cpu/mpc8xx/cpu.c | 331 +++++++++++++ arch/powerpc/cpu/mpc8xx/cpu_init.c | 180 +++++++ arch/powerpc/cpu/mpc8xx/fdt.c | 27 ++ arch/powerpc/cpu/mpc8xx/fec.c | 847 +++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xx/interrupts.c | 259 ++++++++++ arch/powerpc/cpu/mpc8xx/serial.c | 301 ++++++++++++ arch/powerpc/cpu/mpc8xx/speed.c | 62 +++ arch/powerpc/cpu/mpc8xx/spi.c | 368 ++++++++++++++ arch/powerpc/cpu/mpc8xx/start.S | 636 +++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xx/traps.c | 168 +++++++ arch/powerpc/include/asm/8xx_immap.h | 468 ++++++++++++++++++ arch/powerpc/include/asm/cache.h | 41 +- arch/powerpc/include/asm/global_data.h | 3 + arch/powerpc/include/asm/iopin_8xx.h | 379 +++++++++++++++ arch/powerpc/include/asm/ppc.h | 11 + arch/powerpc/lib/Kconfig | 7 + arch/powerpc/lib/Makefile | 1 + arch/powerpc/lib/immap.c | 397 +++++++++++++++ arch/powerpc/lib/time.c | 11 + cmd/bdinfo.c | 2 +- cmd/reginfo.c | 59 ++- include/asm-generic/u-boot.h | 2 +- include/commproc.h | 687 ++++++++++++++++++++++++++ include/mpc8xx.h | 14 - include/ppc_asm.tmpl | 46 ++ include/watchdog.h | 5 + scripts/config_whitelist.txt | 22 + 34 files changed, 5418 insertions(+), 26 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xx/Kconfig create mode 100644 arch/powerpc/cpu/mpc8xx/Makefile create mode 100644 arch/powerpc/cpu/mpc8xx/config.mk create mode 100644 arch/powerpc/cpu/mpc8xx/cpu.c create mode 100644 arch/powerpc/cpu/mpc8xx/cpu_init.c create mode 100644 arch/powerpc/cpu/mpc8xx/fdt.c create mode 100644 arch/powerpc/cpu/mpc8xx/fec.c create mode 100644 arch/powerpc/cpu/mpc8xx/interrupts.c create mode 100644 arch/powerpc/cpu/mpc8xx/serial.c create mode 100644 arch/powerpc/cpu/mpc8xx/speed.c create mode 100644 arch/powerpc/cpu/mpc8xx/spi.c create mode 100644 arch/powerpc/cpu/mpc8xx/start.S create mode 100644 arch/powerpc/cpu/mpc8xx/traps.c create mode 100644 arch/powerpc/include/asm/8xx_immap.h create mode 100644 arch/powerpc/include/asm/iopin_8xx.h create mode 100644 arch/powerpc/lib/Kconfig create mode 100644 arch/powerpc/lib/immap.c create mode 100644 include/commproc.h diff --git a/MAINTAINERS b/MAINTAINERS index 85dfa14cac..3505da5648 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -325,7 +325,7 @@ S: Maintained F: arch/powerpc/ POWERPC MPC8XX -M: Wolfgang Denk <wd(a)denx.de> +M: Christophe Leroy <christophe.leroy(a)c-s.fr> S: Maintained T: git git://git.denx.de/u-boot-mpc8xx.git F: arch/powerpc/cpu/mpc8xx/ diff --git a/README b/README index 5f4f97cb01..c3ab481a56 100644 --- a/README +++ b/README @@ -328,6 +328,9 @@ The following options need to be configured: multiple fs option at one time for marvell soc family +- 8xx CPU Options: (if using an MPC8xx CPU) + CONFIG_8xx_GCLK_FREQ - CPU clock + - 85xx CPU Options: CONFIG_SYS_PPC64 @@ -691,10 +694,29 @@ The following options need to be configured: Define this variable to enable hw flow control in serial driver. Current user of this option is drivers/serial/nsl16550.c driver +- Console Interface: + Depending on board, define exactly one serial port + (CONFIG_8xx_CONS_SMC1 or CONFIG_8xx_CONS_SMC2), + or switch off the serial console by defining + CONFIG_8xx_CONS_NONE + + Note: if CONFIG_8xx_CONS_NONE is defined, the serial + port routines must be defined elsewhere + (i.e. serial_init(), serial_getc(), ...) + - Console Baudrate: CONFIG_BAUDRATE - in bps Select one of the baudrates listed in CONFIG_SYS_BAUDRATE_TABLE, see below. + CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale + +- Console Rx buffer length + With CONFIG_SYS_SMC_RXBUFLEN it is possible to define + the maximum receive buffer length for the SMC. + This option is actual only for 8xx possible. + If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE + must be defined, to setup the maximum idle timeout for + the SMC. - Autoboot Command: CONFIG_BOOTCOMMAND @@ -860,7 +882,7 @@ The following options need to be configured: (configuration option CONFIG_CMD_CACHE) unless you know what you (and your U-Boot users) are doing. Data cache cannot be enabled on systems like the - 8260 (where accesses to the IMMR region must be + 8xx (where accesses to the IMMR region must be uncached), and it cannot be disabled on all other systems where we (mis-) use the data cache to hold an initial stack and some data. @@ -923,9 +945,11 @@ The following options need to be configured: CONFIG_WATCHDOG If this variable is defined, it enables watchdog support for the SoC. There must be support in the SoC - specific code for a watchdog. When supported for a - specific SoC is available, then no further board specific - code should be needed to use it. + specific code for a watchdog. For the 8xx + CPUs, the SIU Watchdog feature is enabled in the SYPCR + register. When supported for a specific SoC is + available, then no further board specific code should + be needed to use it. CONFIG_HW_WATCHDOG When using a watchdog circuitry external to the used @@ -3936,7 +3960,7 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're - doing! (11-4) [82xx systems only] + doing! (11-4) [MPC8xx systems only] - CONFIG_SYS_INIT_RAM_ADDR: @@ -3949,6 +3973,7 @@ Low Level (hardware related) configuration options: sequences. U-Boot uses the following memory types: + - MPC8xx: IMMR (internal memory of the CPU) - CONFIG_SYS_GBL_DATA_OFFSET: @@ -3968,6 +3993,16 @@ Low Level (hardware related) configuration options: point to an otherwise UNUSED address space between the top of RAM and the start of the PCI space. +- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6) + +- CONFIG_SYS_SYPCR: System Protection Control (11-9) + +- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26) + +- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31) + +- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) + - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27) - CONFIG_SYS_OR_TIMING_SDRAM: @@ -3976,6 +4011,8 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_MAMR_PTA: periodic timer for refresh +- CONFIG_SYS_DER: Debug Event Register (37-47) + - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM, CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM, @@ -4061,6 +4098,21 @@ Low Level (hardware related) configuration options: Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. +- CONFIG_ETHER_ON_FEC[12] + Define to enable FEC[12] on a 8xx series processor. + +- CONFIG_FEC[12]_PHY + Define to the hardcoded PHY address which corresponds + to the given FEC; i. e. + #define CONFIG_FEC1_PHY 4 + means that the PHY with address 4 is connected to FEC1 + + When set to -1, means to probe for first available. + +- CONFIG_FEC[12]_PHY_NORXERR + The PHY does not have a RXERR line (RMII only). + (so program the FEC to ignore it). + - CONFIG_RMII Enable RMII mode for all FECs. Note that this is a global option, we can't diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index d1b54ea4e1..9e9bc63b2f 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si) si->clk_bus = gd->bus_clk; si->clk_cpu = gd->cpu_clk; -#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define bi_bar bi_immr_base #elif defined(CONFIG_MPC83xx) #define bi_bar bi_immrbar diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index c3dba8955d..a7558d59b2 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -29,10 +29,16 @@ config MPC86xx select SYS_FSL_DDR select SYS_FSL_DDR_BE +config 8xx + bool "MPC8xx" + endchoice +source "arch/powerpc/lib/Kconfig" + source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc86xx/Kconfig" +source "arch/powerpc/cpu/mpc8xx/Kconfig" endmenu diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig new file mode 100644 index 0000000000..a425cba8aa --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -0,0 +1,13 @@ +menu "mpc8xx CPU" + depends on 8xx + +config SYS_CPU + default "mpc8xx" + +choice + prompt "Target select" + optional + +endchoice + +endmenu diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile new file mode 100644 index 0000000000..5dd801d76e --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -0,0 +1,17 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y += start.o +extra-y += traps.o +obj-y += cpu.o +obj-y += cpu_init.o +obj-y += fec.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-y += interrupts.o +obj-y += serial.o +obj-y += speed.o +obj-y += spi.o diff --git a/arch/powerpc/cpu/mpc8xx/config.mk b/arch/powerpc/cpu/mpc8xx/config.mk new file mode 100644 index 0000000000..485e43d2de --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/config.mk @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2010 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c new file mode 100644 index 0000000000..80b9596813 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -0,0 +1,331 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * m8xx.c + * + * CPU specific code + * + * written or collected and sometimes rewritten by + * Magnus Damm <damm(a)bitsmart.com> + * + * minor modifications by + * Wolfgang Denk <wd(a)denx.de> + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <mpc8xx.h> +#include <commproc.h> +#include <netdev.h> +#include <asm/cache.h> +#include <linux/compiler.h> +#include <asm/io.h> + +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <fdt_support.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static char *cpu_warning = "\n " \ + "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***"; + +static int check_CPU (long clock, uint pvr, uint immr) +{ + char *id_str = + NULL; + volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); + uint k, m; + char buf[32]; + char pre = 'X'; + char *mid = "xx"; + char *suf; + + /* the highest 16 bits should be 0x0050 for a 860 */ + + if ((pvr >> 16) != 0x0050) + return -1; + + k = (immr << 16) | + immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; + m = 0; + suf = ""; + + /* + * Some boards use sockets so different CPUs can be used. + * We have to check chip version in run time. + */ + switch (k) { + /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ + case 0x08010004: /* Rev. A.0 */ + suf = "A"; + /* fall through */ + case 0x08000003: /* Rev. 0.3 */ + pre = 'M'; m = 1; + if (id_str == NULL) + id_str = + "PC866x"; /* Unknown chip from MPC866 family */ + break; + case 0x09000000: pre = 'M'; mid = suf = ""; m = 1; + if (id_str == NULL) + id_str = "PC885"; /* 870/875/880/885 */ + break; + + default: suf = NULL; break; + } + + if (id_str == NULL) + id_str = "PC86x"; /* Unknown 86x chip */ + if (suf) + printf ("%c%s%sZPnn%s", pre, id_str, mid, suf); + else + printf ("unknown M%s (0x%08x)", id_str, k); + + printf (" at %s MHz: ", strmhz (buf, clock)); + + print_size(checkicache(), " I-Cache "); + print_size(checkdcache(), " D-Cache"); + + /* do we have a FEC (860T/P or 852/859/866/885)? */ + + immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; + if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { + printf (" FEC present"); + } + + if (!m) { + puts (cpu_warning); + } + + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +int checkcpu (void) +{ + ulong clock = gd->cpu_clk; + uint immr = get_immr (0); /* Return full IMMR contents */ + uint pvr = get_pvr (); + + puts ("CPU: "); + + return check_CPU (clock, pvr, immr); +} + +/* ------------------------------------------------------------------------- */ +/* L1 i-cache */ + +int checkicache (void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + u32 cacheon = rd_ic_cst () & IDC_ENABLED; + + u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ + u32 m; + u32 lines = -1; + + wr_ic_cst (IDC_UNALL); + wr_ic_cst (IDC_INVALL); + wr_ic_cst (IDC_DISABLE); + __asm__ volatile ("isync"); + + while (!((m = rd_ic_cst ()) & IDC_CERR2)) { + wr_ic_adr (k); + wr_ic_cst (IDC_LDLCK); + __asm__ volatile ("isync"); + + lines++; + k += 0x10; /* the number of bytes in a cacheline */ + } + + wr_ic_cst (IDC_UNALL); + wr_ic_cst (IDC_INVALL); + + if (cacheon) + wr_ic_cst (IDC_ENABLE); + else + wr_ic_cst (IDC_DISABLE); + + __asm__ volatile ("isync"); + + return lines << 4; +}; + +/* ------------------------------------------------------------------------- */ +/* L1 d-cache */ +/* call with cache disabled */ + +int checkdcache (void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + u32 cacheon = rd_dc_cst () & IDC_ENABLED; + + u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ + u32 m; + u32 lines = -1; + + wr_dc_cst (IDC_UNALL); + wr_dc_cst (IDC_INVALL); + wr_dc_cst (IDC_DISABLE); + + while (!((m = rd_dc_cst ()) & IDC_CERR2)) { + wr_dc_adr (k); + wr_dc_cst (IDC_LDLCK); + lines++; + k += 0x10; /* the number of bytes in a cacheline */ + } + + wr_dc_cst (IDC_UNALL); + wr_dc_cst (IDC_INVALL); + + if (cacheon) + wr_dc_cst (IDC_ENABLE); + else + wr_dc_cst (IDC_DISABLE); + + return lines << 4; +}; + +/* ------------------------------------------------------------------------- */ + +void upmconfig (uint upm, uint * table, uint size) +{ + uint i; + uint addr = 0; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + for (i = 0; i < size; i++) { + memctl->memc_mdr = table[i]; /* (16-15) */ + memctl->memc_mcr = addr | upm; /* (16-16) */ + addr++; + } +} + +/* ------------------------------------------------------------------------- */ + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong msr, addr; + + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ + + /* Interrupts and MMU off */ + __asm__ volatile ("mtspr 81, 0"); + __asm__ volatile ("mfmsr %0":"=r" (msr)); + + msr &= ~0x1030; + __asm__ volatile ("mtmsr %0"::"r" (msr)); + + /* + * Trying to execute the next instruction at a non-existing address + * should cause a machine check, resulting in reset + */ +#ifdef CONFIG_SYS_RESET_ADDRESS + addr = CONFIG_SYS_RESET_ADDRESS; +#else + /* + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE + * - sizeof (ulong) is usually a valid address. Better pick an address + * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. + * "(ulong)-1" used to be a good choice for many systems... + */ + addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); +#endif + ((void (*)(void)) addr) (); + return 1; +} + +/* ------------------------------------------------------------------------- */ + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + * + * See sections 14.2 and 14.6 of the User's Manual + */ +unsigned long get_tbclk (void) +{ + uint immr = get_immr (0); /* Return full IMMR contents */ + volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000); + ulong oscclk, factor, pll; + + if (immap->im_clkrst.car_sccr & SCCR_TBS) { + return (gd->cpu_clk / 16); + } + + pll = immap->im_clkrst.car_plprcr; + +#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) + + /* + * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication + * factor is calculated as follows: + * + * MFN + * MFI + ------- + * MFD + 1 + * factor = ----------------- + * (PDF + 1) * 2^S + * + */ + factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ + (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S)); + + oscclk = gd->cpu_clk / factor; + + if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { + return (oscclk / 4); + } + return (oscclk / 16); +} + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + int re_enable = disable_interrupts (); + + reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); + if (re_enable) + enable_interrupts (); +} +#endif /* CONFIG_WATCHDOG */ + +#if defined(CONFIG_WATCHDOG) + +void reset_8xx_watchdog (volatile immap_t * immr) +{ + /* + * All other boards use the MPC8xx Internal Watchdog + */ + immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ + immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ +} +#endif /* CONFIG_WATCHDOG */ + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ +#if defined(FEC_ENET) + fec_initialize(bis); +#endif + return 0; +} diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c new file mode 100644 index 0000000000..0f935aff9e --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <watchdog.h> + +#include <mpc8xx.h> +#include <commproc.h> + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f (volatile immap_t * immr) +{ + volatile memctl8xx_t *memctl = &immr->im_memctl; +# ifdef CONFIG_SYS_PLPRCR + ulong mfmask; +# endif + ulong reg; + + /* SYPCR - contains watchdog control (11-9) */ + + immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; + +#if defined(CONFIG_WATCHDOG) + reset_8xx_watchdog (immr); +#endif /* CONFIG_WATCHDOG */ + + /* SIUMCR - contains debug pin configuration (11-6) */ + immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; + /* initialize timebase status and control register (11-26) */ + /* unlock TBSCRK */ + + immr->im_sitk.sitk_tbscrk = KAPWR_KEY; + immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; + + /* initialize the PIT (11-31) */ + + immr->im_sitk.sitk_piscrk = KAPWR_KEY; + immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; + + /* System integration timers. Don't change EBDF! (15-27) */ + + immr->im_clkrstk.cark_sccrk = KAPWR_KEY; + reg = immr->im_clkrst.car_sccr; + reg &= SCCR_MASK; + reg |= CONFIG_SYS_SCCR; + immr->im_clkrst.car_sccr = reg; + + /* PLL (CPU clock) settings (15-30) */ + + immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; + + /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to + * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, + * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF + * field value. + * + * For newer (starting MPC866) chips PLPRCR layout is different. + */ +#ifdef CONFIG_SYS_PLPRCR + mfmask = PLPRCR_MFACT_MSK; + + if ((CONFIG_SYS_PLPRCR & mfmask) != 0) + reg = CONFIG_SYS_PLPRCR; /* reset control bits */ + else { + reg = immr->im_clkrst.car_plprcr; + reg &= mfmask; /* isolate MF-related fields */ + reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ + } + immr->im_clkrst.car_plprcr = reg; +#endif + + /* + * Memory Controller: + */ + + /* perform BR0 reset that MPC850 Rev. A can't guarantee */ + reg = memctl->memc_br0; + reg &= BR_PS_MSK; /* Clear everything except Port Size bits */ + reg |= BR_V; /* then add just the "Bank Valid" bit */ + memctl->memc_br0 = reg; + + /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at + * preliminary addresses - these have to be modified later + * when FLASH size has been determined + * + * Depending on the size of the memory region defined by + * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the + * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't + * map CONFIG_SYS_MONITOR_BASE. + * + * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is + * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000. + * + * If BR0 wasn't loaded with address base 0xff000000, then BR0's + * base address remains as 0x00000000. However, the address mask + * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped + * into the Bank0. + * + * This is why CONFIG_IVMS8 and similar boards must load BR0 with + * CONFIG_SYS_BR0_PRELIM in advance. + * + * [Thanks to Michael Liao for this explanation. + * I owe him a free beer. - wd] + */ + +#if defined(CONFIG_SYS_OR0_REMAP) + memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; +#endif +#if defined(CONFIG_SYS_OR1_REMAP) + memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; +#endif +#if defined(CONFIG_SYS_OR5_REMAP) + memctl->memc_or5 = CONFIG_SYS_OR5_REMAP; +#endif + + /* now restrict to preliminary range */ + memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; + memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; + +#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) + memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; + memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) + memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; + memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) + memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; + memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) + memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; + memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; +#endif + + /* + * Reset CPM + */ + immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG; + do { /* Spin until command processed */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r (void) +{ + return (0); +} diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c new file mode 100644 index 0000000000..34d36478d3 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -0,0 +1,27 @@ +/* + * Copyright 2008 (C) Bryan O'Donoghue + * + * Code copied & edited from Freescale mpc85xx stuff. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", get_tbclk(), 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", + gd->arch.brg_clk, 1); + + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c new file mode 100644 index 0000000000..7aa526d7ec --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -0,0 +1,847 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <commproc.h> +#include <malloc.h> +#include <net.h> + +#include <phy.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && \ + (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) + +/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ +#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2) +#define CONFIG_ETHER_ON_FEC1 1 +#endif + +/* define WANT_MII when MII support is required */ +#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) +#define WANT_MII +#else +#undef WANT_MII +#endif + +#if defined(WANT_MII) +#include <miiphy.h> + +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#endif + +#if defined(CONFIG_RMII) && !defined(WANT_MII) +#error RMII support is unusable without a working PHY. +#endif + +#ifdef CONFIG_SYS_DISCOVER_PHY +static int mii_discover_phy(struct eth_device *dev); +#endif + +int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); +int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value); + +static struct ether_fcc_info_s +{ + int ether_index; + int fecp_offset; + int phy_addr; + int actual_phy_addr; + int initialized; +} + ether_fcc_info[] = { +#if defined(CONFIG_ETHER_ON_FEC1) + { + 0, + offsetof(immap_t, im_cpm.cp_fec1), +#if defined(CONFIG_FEC1_PHY) + CONFIG_FEC1_PHY, +#else + -1, /* discover */ +#endif + -1, + 0, + + }, +#endif +#if defined(CONFIG_ETHER_ON_FEC2) + { + 1, + offsetof(immap_t, im_cpm.cp_fec2), +#if defined(CONFIG_FEC2_PHY) + CONFIG_FEC2_PHY, +#else + -1, +#endif + -1, + 0, + }, +#endif +}; + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +#define TOUT_LOOP 100 + +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 + +#ifdef __GNUC__ +static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8))); +#else +#error txbuf must be aligned. +#endif + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * FEC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +typedef volatile struct CommonBufferDescriptor { + cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ + cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ +} RTXBD; + +static RTXBD *rtx = NULL; + +static int fec_send(struct eth_device *dev, void *packet, int length); +static int fec_recv(struct eth_device* dev); +static int fec_init(struct eth_device* dev, bd_t * bd); +static void fec_halt(struct eth_device* dev); +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +static void __mii_init(void); +#endif + +int fec_initialize(bd_t *bis) +{ + struct eth_device* dev; + struct ether_fcc_info_s *efis; + int i; + + for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) { + + dev = malloc(sizeof(*dev)); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + /* for FEC1 make sure that the name of the interface is the same + as the old one for compatibility reasons */ + if (i == 0) { + strcpy(dev->name, "FEC"); + } else { + sprintf (dev->name, "FEC%d", + ether_fcc_info[i].ether_index + 1); + } + + efis = &ether_fcc_info[i]; + + /* + * reset actual phy addr + */ + efis->actual_phy_addr = -1; + + dev->priv = efis; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = fec8xx_miiphy_read; + mdiodev->write = fec8xx_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; +#endif + } + return 1; +} + +static int fec_send(struct eth_device *dev, void *packet, int length) +{ + int j, rc; + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); + + /* section 16.9.23.3 + * Wait for ready + */ + j = 0; + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { + udelay(1); + j++; + } + if (j>=TOUT_LOOP) { + printf("TX not ready\n"); + } + + rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; + __asm__ ("eieio"); + + /* Activate transmit Buffer Descriptor polling */ + fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ + + j = 0; + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { + udelay(1); + j++; + } + if (j>=TOUT_LOOP) { + printf("TX timeout\n"); + } + /* return only status bits */; + rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); + + txIdx = (txIdx + 1) % TX_BUF_CNT; + + return rc; +} + +static int fec_recv (struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = + (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); + int length; + + for (;;) { + /* section 16.9.23.2 */ + if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = rtx->rxbd[rxIdx].cbd_datlen; + + if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { + } else { + uchar *rx = net_rx_packets[rxIdx]; + + length -= 4; + +#if defined(CONFIG_CMD_CDP) + if ((rx[0] & 1) != 0 && + memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 && + !is_cdp_packet((uchar *)rx)) + rx = NULL; +#endif + /* + * Pass the packet up to the protocol layers. + */ + if (rx != NULL) + net_process_received_packet(rx, length); + } + + /* Give the buffer back to the FEC. */ + rtx->rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx->rxbd[PKTBUFSRX - 1].cbd_sc = + (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } else { + rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + + __asm__ ("eieio"); + + /* Try to fill Buffer Descriptors */ + fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ + } + + return length; +} + +/************************************************************** + * + * FEC Ethernet Initialization Routine + * + *************************************************************/ + +#define FEC_ECNTRL_PINMUX 0x00000004 +#define FEC_ECNTRL_ETHER_EN 0x00000002 +#define FEC_ECNTRL_RESET 0x00000001 + +#define FEC_RCNTRL_BC_REJ 0x00000010 +#define FEC_RCNTRL_PROM 0x00000008 +#define FEC_RCNTRL_MII_MODE 0x00000004 +#define FEC_RCNTRL_DRT 0x00000002 +#define FEC_RCNTRL_LOOP 0x00000001 + +#define FEC_TCNTRL_FDEN 0x00000004 +#define FEC_TCNTRL_HBC 0x00000002 +#define FEC_TCNTRL_GTS 0x00000001 + +#define FEC_RESET_DELAY 50 + +#if defined(CONFIG_RMII) + +static inline void fec_10Mbps(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + int fecidx = efis->ether_index; + uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; + + if ((unsigned int)fecidx >= 2) + hang(); + + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask; +} + +static inline void fec_100Mbps(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + int fecidx = efis->ether_index; + uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; + + if ((unsigned int)fecidx >= 2) + hang(); + + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask; +} + +#endif + +static inline void fec_full_duplex(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); + + fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT; + fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */ +} + +static inline void fec_half_duplex(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); + + fecp->fec_r_cntrl |= FEC_RCNTRL_DRT; + fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */ +} + +static void fec_pin_init(int fecidx) +{ + bd_t *bd = gd->bd; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + + /* + * Set MII speed to 2.5 MHz or slightly below. + * + * According to the MPC860T (Rev. D) Fast ethernet controller user + * manual (6.2.14), + * the MII management interface clock must be less than or equal + * to 2.5 MHz. + * This MDC frequency is equal to system clock / (2 * MII_SPEED). + * Then MII_SPEED = system_clock / 2 * 2,5 MHz. + * + * All MII configuration is done via FEC1 registers: + */ + immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; + +#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) + /* use MDC for MII */ + immr->im_ioport.iop_pdpar |= 0x0080; + immr->im_ioport.iop_pddir &= ~0x0080; +#endif + + if (fecidx == 0) { +#if defined(CONFIG_ETHER_ON_FEC1) + +#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ + +#if !defined(CONFIG_RMII) + + immr->im_ioport.iop_papar |= 0xf830; + immr->im_ioport.iop_padir |= 0x0830; + immr->im_ioport.iop_padir &= ~0xf000; + + immr->im_cpm.cp_pbpar |= 0x00001001; + immr->im_cpm.cp_pbdir &= ~0x00001001; + + immr->im_ioport.iop_pcpar |= 0x000c; + immr->im_ioport.iop_pcdir &= ~0x000c; + + immr->im_cpm.cp_pepar |= 0x00000003; + immr->im_cpm.cp_pedir |= 0x00000003; + immr->im_cpm.cp_peso &= ~0x00000003; + + immr->im_cpm.cp_cptr &= ~0x00000100; + +#else + +#if !defined(CONFIG_FEC1_PHY_NORXERR) + immr->im_ioport.iop_papar |= 0x1000; + immr->im_ioport.iop_padir &= ~0x1000; +#endif + immr->im_ioport.iop_papar |= 0xe810; + immr->im_ioport.iop_padir |= 0x0810; + immr->im_ioport.iop_padir &= ~0xe000; + + immr->im_cpm.cp_pbpar |= 0x00000001; + immr->im_cpm.cp_pbdir &= ~0x00000001; + + immr->im_cpm.cp_cptr |= 0x00000100; + immr->im_cpm.cp_cptr &= ~0x00000050; + +#endif /* !CONFIG_RMII */ + +#else + /* + * Configure all of port D for MII. + */ + immr->im_ioport.iop_pdpar = 0x1fff; + + immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ +#endif + +#endif /* CONFIG_ETHER_ON_FEC1 */ + } else if (fecidx == 1) { + +#if defined(CONFIG_ETHER_ON_FEC2) + +#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ + +#if !defined(CONFIG_RMII) + immr->im_cpm.cp_pepar |= 0x0003fffc; + immr->im_cpm.cp_pedir |= 0x0003fffc; + immr->im_cpm.cp_peso &= ~0x000087fc; + immr->im_cpm.cp_peso |= 0x00037800; + + immr->im_cpm.cp_cptr &= ~0x00000080; +#else + +#if !defined(CONFIG_FEC2_PHY_NORXERR) + immr->im_cpm.cp_pepar |= 0x00000010; + immr->im_cpm.cp_pedir |= 0x00000010; + immr->im_cpm.cp_peso &= ~0x00000010; +#endif + immr->im_cpm.cp_pepar |= 0x00039620; + immr->im_cpm.cp_pedir |= 0x00039620; + immr->im_cpm.cp_peso |= 0x00031000; + immr->im_cpm.cp_peso &= ~0x00008620; + + immr->im_cpm.cp_cptr |= 0x00000080; + immr->im_cpm.cp_cptr &= ~0x00000028; +#endif /* CONFIG_RMII */ + +#endif /* CONFIG_MPC885_FAMILY */ + +#endif /* CONFIG_ETHER_ON_FEC2 */ + + } +} + +static int fec_reset(volatile fec_t *fecp) +{ + int i; + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) + return -1; + + return 0; +} + +static int fec_init (struct eth_device *dev, bd_t * bd) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile fec_t *fecp = + (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); + int i; + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + /* the MII interface is connected to FEC1 + * so for the miiphy_xxx function to work we must + * call mii_init since fec_halt messes the thing up + */ + if (efis->ether_index != 0) + __mii_init(); +#endif + + if (fec_reset(fecp) < 0) + printf ("FEC_RESET_DELAY timeout\n"); + + /* We use strictly polling mode only + */ + fecp->fec_imask = 0; + + /* Clear any pending interrupt + */ + fecp->fec_ievent = 0xffc0; + + /* No need to set the IVEC register */ + + /* Set station address + */ +#define ea dev->enetaddr + fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->fec_addr_high = (ea[4] << 8) | (ea[5]); +#undef ea + +#if defined(CONFIG_CMD_CDP) + /* + * Turn on multicast address hash table + */ + fecp->fec_hash_table_high = 0xffffffff; + fecp->fec_hash_table_low = 0xffffffff; +#else + /* Clear multicast address hash table + */ + fecp->fec_hash_table_high = 0; + fecp->fec_hash_table_low = 0; +#endif + + /* Set maximum receive buffer size. + */ + fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; + + /* Set maximum frame length + */ + fecp->fec_r_hash = PKT_MAXBUF_SIZE; + + /* + * Setup Buffers and Buffer Desriptors + */ + rxIdx = 0; + txIdx = 0; + + if (!rtx) + rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_FEC_BASE); + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + for (i = 0; i < PKTBUFSRX; i++) { + rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx->rxbd[i].cbd_datlen = 0; /* Reset */ + rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; + } + rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Last, Tx CRC + */ + for (i = 0; i < TX_BUF_CNT; i++) { + rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; + rtx->txbd[i].cbd_datlen = 0; /* Reset */ + rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); + } + rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* Set receive and transmit descriptor base + */ + fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); + fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); + + /* Enable MII mode + */ + /* Half duplex mode */ + fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; + fecp->fec_x_cntrl = 0; + + /* Enable big endian and don't care about SDMA FC. + */ + fecp->fec_fun_code = 0x78000000; + + /* + * Setup the pin configuration of the FEC + */ + fec_pin_init (efis->ether_index); + + rxIdx = 0; + txIdx = 0; + + /* + * Now enable the transmit and receive processing + */ + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; + + if (efis->phy_addr == -1) { +#ifdef CONFIG_SYS_DISCOVER_PHY + /* + * wait for the PHY to wake up after reset + */ + efis->actual_phy_addr = mii_discover_phy (dev); + + if (efis->actual_phy_addr == -1) { + printf ("Unable to discover phy!\n"); + return -1; + } +#else + efis->actual_phy_addr = -1; +#endif + } else { + efis->actual_phy_addr = efis->phy_addr; + } + +#if defined(CONFIG_MII) && defined(CONFIG_RMII) + /* + * adapt the RMII speed to the speed of the phy + */ + if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) { + fec_100Mbps (dev); + } else { + fec_10Mbps (dev); + } +#endif + +#if defined(CONFIG_MII) + /* + * adapt to the half/full speed settings + */ + if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) { + fec_full_duplex (dev); + } else { + fec_half_duplex (dev); + } +#endif + + /* And last, try to fill Rx Buffer Descriptors */ + fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ + + efis->initialized = 1; + + return 0; +} + + +static void fec_halt(struct eth_device* dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); + int i; + + /* avoid halt if initialized; mii gets stuck otherwise */ + if (!efis->initialized) + return; + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { + printf ("FEC_RESET_DELAY timeout\n"); + return; + } + + efis->initialized = 0; +} + +#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + +/* Make MII read/write commands for the FEC. +*/ + +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18) | \ + (VAL & 0xffff)) + +/* Interrupt events/masks. +*/ +#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ +#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ +#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ +#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ +#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ +#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ +#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ +#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ +#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ +#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ + +/* send command to phy using mii, wait for result */ +static uint +mii_send(uint mii_cmd) +{ + uint mii_reply; + volatile fec_t *ep; + int cnt; + + ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec); + + ep->fec_mii_data = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + cnt = 0; + while (!(ep->fec_ievent & FEC_ENET_MII)) { + if (++cnt > 1000) { + printf("mii_send STUCK!\n"); + break; + } + } + mii_reply = ep->fec_mii_data; /* result from phy */ + ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif + +#if defined(CONFIG_SYS_DISCOVER_PHY) +static int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + uint phyno; + int pass; + uint phytype; + int phyaddr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2)); + if (phytype != 0xffff) { + phyaddr = phyno; + phytype |= mii_send(mk_mii_read(phyno, + MII_PHYSID1)) << 16; + } + } + } + if (phyaddr < 0) { + printf("No PHY device found.\n"); + } + return phyaddr; +} +#endif /* CONFIG_SYS_DISCOVER_PHY */ + +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) + +/**************************************************************************** + * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +static void __mii_init(void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile fec_t *fecp = &(immr->im_cpm.cp_fec); + + if (fec_reset(fecp) < 0) + printf ("FEC_RESET_DELAY timeout\n"); + + /* We use strictly polling mode only + */ + fecp->fec_imask = 0; + + /* Clear any pending interrupt + */ + fecp->fec_ievent = 0xffc0; + + /* Now enable the transmit and receive processing + */ + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; +} + +void mii_init (void) +{ + int i; + + __mii_init(); + + /* Setup the pin configuration of the FEC(s) + */ + for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) + fec_pin_init(ether_fcc_info[i].ether_index); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + unsigned short value = 0; + short rdreg; /* register working value */ + + rdreg = mii_send(mk_mii_read(addr, reg)); + + value = rdreg; + return value; +} + +int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) +{ + (void)mii_send(mk_mii_write(addr, reg, value)); + + return 0; +} +#endif + +#endif diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c new file mode 100644 index 0000000000..f090ad9ecb --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/interrupts.c @@ -0,0 +1,259 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mpc8xx.h> +#include <mpc8xx_irq.h> +#include <asm/processor.h> +#include <commproc.h> + +/************************************************************************/ + +/* + * CPM interrupt vector functions. + */ +struct interrupt_action { + interrupt_handler_t *handler; + void *arg; +}; + +static struct interrupt_action cpm_vecs[CPMVEC_NR]; +static struct interrupt_action irq_vecs[NR_IRQS]; + +static void cpm_interrupt_init (void); +static void cpm_interrupt (void *regs); + +/************************************************************************/ + +int interrupt_init_cpu (unsigned *decrementer_count) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + + *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; + + /* disable all interrupts */ + immr->im_siu_conf.sc_simask = 0; + + /* Configure CPM interrupts */ + cpm_interrupt_init (); + + return (0); +} + +/************************************************************************/ + +/* + * Handle external interrupts + */ +void external_interrupt (struct pt_regs *regs) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + int irq; + ulong simask, newmask; + ulong vec, v_bit; + + /* + * read the SIVEC register and shift the bits down + * to get the irq number + */ + vec = immr->im_siu_conf.sc_sivec; + irq = vec >> 26; + v_bit = 0x80000000UL >> irq; + + /* + * Read Interrupt Mask Register and Mask Interrupts + */ + simask = immr->im_siu_conf.sc_simask; + newmask = simask & (~(0xFFFF0000 >> irq)); + immr->im_siu_conf.sc_simask = newmask; + + if (!(irq & 0x1)) { /* External Interrupt ? */ + ulong siel; + + /* + * Read Interrupt Edge/Level Register + */ + siel = immr->im_siu_conf.sc_siel; + + if (siel & v_bit) { /* edge triggered interrupt ? */ + /* + * Rewrite SIPEND Register to clear interrupt + */ + immr->im_siu_conf.sc_sipend = v_bit; + } + } + + if (irq_vecs[irq].handler != NULL) { + irq_vecs[irq].handler (irq_vecs[irq].arg); + } else { + printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", + irq, vec); + /* turn off the bogus interrupt to avoid it from now */ + simask &= ~v_bit; + } + /* + * Re-Enable old Interrupt Mask + */ + immr->im_siu_conf.sc_simask = simask; +} + +/************************************************************************/ + +/* + * CPM interrupt handler + */ +static void cpm_interrupt (void *regs) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + uint vec; + + /* + * Get the vector by setting the ACK bit + * and then reading the register. + */ + immr->im_cpic.cpic_civr = 1; + vec = immr->im_cpic.cpic_civr; + vec >>= 11; + + if (cpm_vecs[vec].handler != NULL) { + (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg); + } else { + immr->im_cpic.cpic_cimr &= ~(1 << vec); + printf ("Masking bogus CPM interrupt vector 0x%x\n", vec); + } + /* + * After servicing the interrupt, + * we have to remove the status indicator. + */ + immr->im_cpic.cpic_cisr |= (1 << vec); +} + +/* + * The CPM can generate the error interrupt when there is a race + * condition between generating and masking interrupts. All we have + * to do is ACK it and return. This is a no-op function so we don't + * need any special tests in the interrupt handler. + */ +static void cpm_error_interrupt (void *dummy) +{ +} + +/************************************************************************/ +/* + * Install and free an interrupt handler + */ +void irq_install_handler (int vec, interrupt_handler_t * handler, + void *arg) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + + if ((vec & CPMVEC_OFFSET) != 0) { + /* CPM interrupt */ + vec &= 0xffff; + if (cpm_vecs[vec].handler != NULL) { + printf ("CPM interrupt 0x%x replacing 0x%x\n", + (uint) handler, + (uint) cpm_vecs[vec].handler); + } + cpm_vecs[vec].handler = handler; + cpm_vecs[vec].arg = arg; + immr->im_cpic.cpic_cimr |= (1 << vec); + } else { + /* SIU interrupt */ + if (irq_vecs[vec].handler != NULL) { + printf ("SIU interrupt %d 0x%x replacing 0x%x\n", + vec, + (uint) handler, + (uint) cpm_vecs[vec].handler); + } + irq_vecs[vec].handler = handler; + irq_vecs[vec].arg = arg; + immr->im_siu_conf.sc_simask |= 1 << (31 - vec); + } +} + +void irq_free_handler (int vec) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + + if ((vec & CPMVEC_OFFSET) != 0) { + /* CPM interrupt */ + vec &= 0xffff; + immr->im_cpic.cpic_cimr &= ~(1 << vec); + cpm_vecs[vec].handler = NULL; + cpm_vecs[vec].arg = NULL; + } else { + /* SIU interrupt */ + immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); + irq_vecs[vec].handler = NULL; + irq_vecs[vec].arg = NULL; + } +} + +/************************************************************************/ + +static void cpm_interrupt_init (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + + /* + * Initialize the CPM interrupt controller. + */ + + immr->im_cpic.cpic_cicr = + (CICR_SCD_SCC4 | + CICR_SCC_SCC3 | + CICR_SCB_SCC2 | + CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK; + + immr->im_cpic.cpic_cimr = 0; + + /* + * Install the error handler. + */ + irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL); + + immr->im_cpic.cpic_cicr |= CICR_IEN; + + /* + * Install the cpm interrupt handler + */ + irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL); +} + +/************************************************************************/ + +/* + * timer_interrupt - gets called when the decrementer overflows, + * with interrupts disabled. + * Trivial implementation - no need to be really accurate. + */ +void timer_interrupt_cpu (struct pt_regs *regs) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + + /* Reset Timer Expired and Timers Interrupt Status */ + immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; + __asm__ ("nop"); + /* + Clear TEXPS (and TMIST on older chips). SPLSS (on older + chips) is cleared too. + + Bitwise OR is a read-modify-write operation so ALL bits + which are cleared by writing `1' would be cleared by + operations like + + immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; + + The same can be achieved by simple writing of the PLPRCR + to itself. If a bit value should be preserved, read the + register, ZERO the bit and write, not OR, the result back. + */ + immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr; +} + +/************************************************************************/ diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c new file mode 100644 index 0000000000..d4f1a41a1a --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <commproc.h> +#include <command.h> +#include <serial.h> +#include <watchdog.h> +#include <linux/compiler.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ + +#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ +#define SMC_INDEX 0 +#define PROFF_SMC PROFF_SMC1 +#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 + +#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ +#define SMC_INDEX 1 +#define PROFF_SMC PROFF_SMC2 +#define CPM_CR_CH_SMC CPM_CR_CH_SMC2 + +#endif /* CONFIG_8xx_CONS_SMCx */ + +#if !defined(CONFIG_SYS_SMC_RXBUFLEN) +#define CONFIG_SYS_SMC_RXBUFLEN 1 +#define CONFIG_SYS_MAXIDLE 0 +#else +#if !defined(CONFIG_SYS_MAXIDLE) +#error "you must define CONFIG_SYS_MAXIDLE" +#endif +#endif + +typedef volatile struct serialbuffer { + cbd_t rxbd; /* Rx BD */ + cbd_t txbd; /* Tx BD */ + uint rxindex; /* index for next character to read */ + volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ + volatile uchar txbuf; /* tx buffers */ +} serialbuffer_t; + +static void serial_setdivisor(volatile cpm8xx_t *cp) +{ + int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; + + if(divisor/16>0x1000) { + /* bad divisor, assume 50MHz clock and 9600 baud */ + divisor=(50*1000*1000 + 8*9600)/16/9600; + } + +#ifdef CONFIG_SYS_BRGCLK_PRESCALE + divisor /= CONFIG_SYS_BRGCLK_PRESCALE; +#endif + + if(divisor<=0x1000) { + cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN; + } else { + cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16; + } +} + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +static void smc_setbrg (void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + + /* Set up the baud rate generator. + * See 8xx_io/commproc.c for details. + * + * Wire BRG1 to SMCx + */ + + cp->cp_simode = 0x00000000; + + serial_setdivisor(cp); +} + +static int smc_init (void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile smc_t *sp; + volatile smc_uart_t *up; + volatile cpm8xx_t *cp = &(im->im_cpm); + uint dpaddr; + volatile serialbuffer_t *rtx; + + /* initialize pointers to SMC */ + + sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); + up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; + /* Disable relocation */ + up->smc_rpbase = 0; + + /* Disable transmitter/receiver. */ + sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); + + /* Enable SDMA. */ + im->im_siu_conf.sc_sdcr = 1; + + /* clear error conditions */ +#ifdef CONFIG_SYS_SDSR + im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; +#else + im->im_sdma.sdma_sdsr = 0x83; +#endif + + /* clear SDMA interrupt mask */ +#ifdef CONFIG_SYS_SDMR + im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; +#else + im->im_sdma.sdma_sdmr = 0x00; +#endif + +#if defined(CONFIG_8xx_CONS_SMC1) + /* Use Port B for SMC1 instead of other functions. */ + cp->cp_pbpar |= 0x000000c0; + cp->cp_pbdir &= ~0x000000c0; + cp->cp_pbodr &= ~0x000000c0; +#else /* CONFIG_8xx_CONS_SMC2 */ + /* Use Port B for SMC2 instead of other functions. + */ + cp->cp_pbpar |= 0x00000c00; + cp->cp_pbdir &= ~0x00000c00; + cp->cp_pbodr &= ~0x00000c00; +#endif + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + dpaddr = CPM_SERIAL_BASE; + + rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr]; + /* Allocate space for two buffer descriptors in the DP ram. + * For now, this address seems OK, but it may have to + * change with newer versions of the firmware. + * damm: allocating space after the two buffers for rx/tx data + */ + + rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; + rtx->rxbd.cbd_sc = 0; + + rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; + rtx->txbd.cbd_sc = 0; + + /* Set up the uart parameters in the parameter ram. */ + up->smc_rbase = dpaddr; + up->smc_tbase = dpaddr+sizeof(cbd_t); + up->smc_rfcr = SMC_EB; + up->smc_tfcr = SMC_EB; + + /* Set UART mode, 8 bit, no parity, one stop. + * Enable receive and transmit. + */ + sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; + + /* Mask all interrupts and remove anything pending. + */ + sp->smc_smcm = 0; + sp->smc_smce = 0xff; + + /* Set up the baud rate generator */ + smc_setbrg (); + + /* Make the first buffer the only buffer. */ + rtx->txbd.cbd_sc |= BD_SC_WRAP; + rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + + /* single/multi character receive. */ + up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; + up->smc_maxidl = CONFIG_SYS_MAXIDLE; + rtx->rxindex = 0; + + /* Initialize Tx/Rx parameters. */ + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. */ + sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; + + return (0); +} + +static void +smc_putc(const char c) +{ + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + volatile serialbuffer_t *rtx; + + if (c == '\n') + smc_putc ('\r'); + + up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; + + rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; + + /* Wait for last character to go. */ + rtx->txbuf = c; + rtx->txbd.cbd_datlen = 1; + rtx->txbd.cbd_sc |= BD_SC_READY; + __asm__("eieio"); + + while (rtx->txbd.cbd_sc & BD_SC_READY) { + WATCHDOG_RESET (); + __asm__("eieio"); + } +} + +static void +smc_puts (const char *s) +{ + while (*s) { + smc_putc (*s++); + } +} + +static int +smc_getc(void) +{ + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + volatile serialbuffer_t *rtx; + unsigned char c; + + up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; + rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; + + /* Wait for character to show up. */ + while (rtx->rxbd.cbd_sc & BD_SC_EMPTY) + WATCHDOG_RESET (); + + /* the characters are read one by one, + * use the rxindex to know the next char to deliver + */ + c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex); + rtx->rxindex++; + + /* check if all char are readout, then make prepare for next receive */ + if (rtx->rxindex >= rtx->rxbd.cbd_datlen) { + rtx->rxindex = 0; + rtx->rxbd.cbd_sc |= BD_SC_EMPTY; + } + return(c); +} + +static int +smc_tstc(void) +{ + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + volatile serialbuffer_t *rtx; + + up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; + + rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; + + return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY); +} + +struct serial_device serial_smc_device = +{ + .name = "serial_smc", + .start = smc_init, + .stop = NULL, + .setbrg = smc_setbrg, + .getc = smc_getc, + .tstc = smc_tstc, + .putc = smc_putc, + .puts = smc_puts, +}; + +__weak struct serial_device *default_serial_console(void) +{ + return &serial_smc_device; +} + +void mpc8xx_serial_initialize(void) +{ + serial_register(&serial_smc_device); +} + +#endif /* CONFIG_8xx_CONS_NONE */ diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c new file mode 100644 index 0000000000..751c089a6d --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mpc8xx.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +void get_brgclk(uint sccr) +{ + uint divider = 0; + + switch((sccr&SCCR_DFBRG11)>>11){ + case 0: + divider = 1; + break; + case 1: + divider = 4; + break; + case 2: + divider = 16; + break; + case 3: + divider = 64; + break; + } + gd->arch.brg_clk = gd->cpu_clk/divider; +} + +/* + * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ + */ +int get_clocks (void) +{ + uint immr = get_immr (0); /* Return full IMMR contents */ + volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); + uint sccr = immap->im_clkrst.car_sccr; + /* + * If for some reason measuring the gclk frequency won't + * work, we return the hardwired value. + * (For example, the cogent CMA286-60 CPU module has no + * separate oscillator for PITRTCLK) + */ + gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; + + if ((sccr & SCCR_EBDF11) == 0) { + /* No Bus Divider active */ + gd->bus_clk = gd->cpu_clk; + } else { + /* The MPC8xx has only one BDF: half clock speed */ + gd->bus_clk = gd->cpu_clk / 2; + } + + get_brgclk(sccr); + + return (0); +} diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/arch/powerpc/cpu/mpc8xx/spi.c new file mode 100644 index 0000000000..c7863ecd09 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/spi.c @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2001 Navin Boppuri / Prashant Patel + * <nboppuri(a)trinetcommunication.com>, + * <pmpatel(a)trinetcommunication.com> + * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen(a)icn.siemens.de> + * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de>. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * MPC8xx CPM SPI interface. + * + * Parts of this code are probably not portable and/or specific to + * the board which I used for the tests. Please send fixes/complaints + * to wd(a)denx.de + * + */ + +#include <common.h> +#include <mpc8xx.h> +#include <commproc.h> +#include <linux/ctype.h> +#include <malloc.h> +#include <post.h> +#include <serial.h> + +#ifdef CONFIG_SPI + +#define SPI_EEPROM_WREN 0x06 +#define SPI_EEPROM_RDSR 0x05 +#define SPI_EEPROM_READ 0x03 +#define SPI_EEPROM_WRITE 0x02 + +/* --------------------------------------------------------------- + * Offset for initial SPI buffers in DPRAM: + * We need a 520 byte scratch DPRAM area to use at an early stage. + * It is used between the two initialization calls (spi_init_f() + * and spi_init_r()). + * The value 0xb00 makes it far enough from the start of the data + * area (as well as from the stack pointer). + * --------------------------------------------------------------- */ +#ifndef CONFIG_SYS_SPI_INIT_OFFSET +#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 +#endif + +/* ------------------- + * Function prototypes + * ------------------- */ +void spi_init (void); + +ssize_t spi_read (uchar *, int, uchar *, int); +ssize_t spi_write (uchar *, int, uchar *, int); +ssize_t spi_xfer (size_t); + +/* ------------------- + * Variables + * ------------------- */ + +#define MAX_BUFFER 0x104 + +/* ---------------------------------------------------------------------- + * Initially we place the RX and TX buffers at a fixed location in DPRAM! + * ---------------------------------------------------------------------- */ +static uchar *rxbuf = + (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem + [CONFIG_SYS_SPI_INIT_OFFSET]; +static uchar *txbuf = + (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem + [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; + +/* ************************************************************************** + * + * Function: spi_init_f + * + * Description: Init SPI-Controller (ROM part) + * + * return: --- + * + * *********************************************************************** */ +void spi_init_f (void) +{ + unsigned int dpaddr; + + volatile spi_t *spi; + volatile immap_t *immr; + volatile cpm8xx_t *cp; + volatile cbd_t *tbdf, *rbdf; + + immr = (immap_t *) CONFIG_SYS_IMMR; + cp = (cpm8xx_t *) &immr->im_cpm; + + spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; + /* Disable relocation */ + spi->spi_rpbase = 0; + +/* 1 */ + /* ------------------------------------------------ + * Initialize Port B SPI pins -> page 34-8 MPC860UM + * (we are only in Master Mode !) + * ------------------------------------------------ */ + + /* -------------------------------------------- + * GPIO or per. Function + * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) + * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) + * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) + * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) + * -------------------------------------------- */ + cp->cp_pbpar |= 0x0000000E; /* set bits */ + cp->cp_pbpar &= ~0x00000001; /* reset bit */ + + /* ---------------------------------------------- + * In/Out or per. Function 0/1 + * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO + * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI + * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK + * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM + * ---------------------------------------------- */ + cp->cp_pbdir |= 0x0000000F; + + /* ---------------------------------------------- + * open drain or active output + * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO + * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI + * PBODR[30] = 0 [0x00000002] -> active output: SPICLK + * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM + * ---------------------------------------------- */ + + cp->cp_pbodr |= 0x00000008; + cp->cp_pbodr &= ~0x00000007; + + /* Initialize the parameter ram. + * We need to make sure many things are initialized to zero + */ + spi->spi_rstate = 0; + spi->spi_rdp = 0; + spi->spi_rbptr = 0; + spi->spi_rbc = 0; + spi->spi_rxtmp = 0; + spi->spi_tstate = 0; + spi->spi_tdp = 0; + spi->spi_tbptr = 0; + spi->spi_tbc = 0; + spi->spi_txtmp = 0; + + dpaddr = CPM_SPI_BASE; + +/* 3 */ + /* Set up the SPI parameters in the parameter ram */ + spi->spi_rbase = dpaddr; + spi->spi_tbase = dpaddr + sizeof (cbd_t); + + /***********IMPORTANT******************/ + + /* + * Setting transmit and receive buffer descriptor pointers + * initially to rbase and tbase. Only the microcode patches + * documentation talks about initializing this pointer. This + * is missing from the sample I2C driver. If you dont + * initialize these pointers, the kernel hangs. + */ + spi->spi_rbptr = spi->spi_rbase; + spi->spi_tbptr = spi->spi_tbase; + +/* 4 */ + /* Init SPI Tx + Rx Parameters */ + while (cp->cp_cpcr & CPM_CR_FLG) + ; + cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG; + while (cp->cp_cpcr & CPM_CR_FLG) + ; + +/* 5 */ + /* Set SDMA configuration register */ + immr->im_siu_conf.sc_sdcr = 0x0001; + +/* 6 */ + /* Set to big endian. */ + spi->spi_tfcr = SMC_EB; + spi->spi_rfcr = SMC_EB; + +/* 7 */ + /* Set maximum receive size. */ + spi->spi_mrblr = MAX_BUFFER; + +/* 8 + 9 */ + /* tx and rx buffer descriptors */ + tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; + rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; + + tbdf->cbd_sc &= ~BD_SC_READY; + rbdf->cbd_sc &= ~BD_SC_EMPTY; + + /* Set the bd's rx and tx buffer address pointers */ + rbdf->cbd_bufaddr = (ulong) rxbuf; + tbdf->cbd_bufaddr = (ulong) txbuf; + +/* 10 + 11 */ + cp->cp_spim = 0; /* Mask all SPI events */ + cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ + + return; +} + +/* ************************************************************************** + * + * Function: spi_init_r + * + * Description: Init SPI-Controller (RAM part) - + * The malloc engine is ready and we can move our buffers to + * normal RAM + * + * return: --- + * + * *********************************************************************** */ +void spi_init_r (void) +{ + volatile cpm8xx_t *cp; + volatile spi_t *spi; + volatile immap_t *immr; + volatile cbd_t *tbdf, *rbdf; + + immr = (immap_t *) CONFIG_SYS_IMMR; + cp = (cpm8xx_t *) &immr->im_cpm; + + spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; + /* Disable relocation */ + spi->spi_rpbase = 0; + + /* tx and rx buffer descriptors */ + tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; + rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; + + /* Allocate memory for RX and TX buffers */ + rxbuf = (uchar *) malloc (MAX_BUFFER); + txbuf = (uchar *) malloc (MAX_BUFFER); + + rbdf->cbd_bufaddr = (ulong) rxbuf; + tbdf->cbd_bufaddr = (ulong) txbuf; + + return; +} + +/**************************************************************************** + * Function: spi_write + **************************************************************************** */ +ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) +{ + int i; + + memset(rxbuf, 0, MAX_BUFFER); + memset(txbuf, 0, MAX_BUFFER); + *txbuf = SPI_EEPROM_WREN; /* write enable */ + spi_xfer(1); + memcpy(txbuf, addr, alen); + *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ + memcpy(alen + txbuf, buffer, len); + spi_xfer(alen + len); + /* ignore received data */ + for (i = 0; i < 1000; i++) { + *txbuf = SPI_EEPROM_RDSR; /* read status */ + txbuf[1] = 0; + spi_xfer(2); + if (!(rxbuf[1] & 1)) { + break; + } + udelay(1000); + } + if (i >= 1000) { + printf ("*** spi_write: Time out while writing!\n"); + } + + return len; +} + +/**************************************************************************** + * Function: spi_read + **************************************************************************** */ +ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) +{ + memset(rxbuf, 0, MAX_BUFFER); + memset(txbuf, 0, MAX_BUFFER); + memcpy(txbuf, addr, alen); + *txbuf = SPI_EEPROM_READ; /* READ memory array */ + + /* + * There is a bug in 860T (?) that cuts the last byte of input + * if we're reading into DPRAM. The solution we choose here is + * to always read len+1 bytes (we have one extra byte at the + * end of the buffer). + */ + spi_xfer(alen + len + 1); + memcpy(buffer, alen + rxbuf, len); + + return len; +} + +/**************************************************************************** + * Function: spi_xfer + **************************************************************************** */ +ssize_t spi_xfer (size_t count) +{ + volatile immap_t *immr; + volatile cpm8xx_t *cp; + volatile spi_t *spi; + cbd_t *tbdf, *rbdf; + ushort loop; + int tm; + + immr = (immap_t *) CONFIG_SYS_IMMR; + cp = (cpm8xx_t *) &immr->im_cpm; + + spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; + /* Disable relocation */ + spi->spi_rpbase = 0; + + tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; + rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; + + /* Set CS for device */ + cp->cp_pbdat &= ~0x0001; + + /* Setting tx bd status and data length */ + tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; + tbdf->cbd_datlen = count; + + /* Setting rx bd status and data length */ + rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; + rbdf->cbd_datlen = 0; /* rx length has no significance */ + + loop = cp->cp_spmode & SPMODE_LOOP; + cp->cp_spmode = /*SPMODE_DIV16 |*/ /* BRG/16 mode not used here */ + loop | + SPMODE_REV | + SPMODE_MSTR | + SPMODE_EN | + SPMODE_LEN(8) | /* 8 Bits per char */ + SPMODE_PM(0x8) ; /* medium speed */ + cp->cp_spim = 0; /* Mask all SPI events */ + cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ + + /* start spi transfer */ + cp->cp_spcom |= SPI_STR; /* Start transmit */ + + /* -------------------------------- + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * -------------------------------- */ + for (tm=0; tm<1000; ++tm) { + if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */ + break; + } + if ((tbdf->cbd_sc & BD_SC_READY) == 0) { + break; + } + udelay (1000); + } + if (tm >= 1000) { + printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); + } + + /* Clear CS for device */ + cp->cp_pbdat |= 0x0001; + + return count; +} +#endif /* CONFIG_SPI */ diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S new file mode 100644 index 0000000000..b00696fc75 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -0,0 +1,636 @@ +/* + * Copyright (C) 1998 Dan Malek <dmalek(a)jlc.net> + * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> + * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* U-Boot - Startup Code for PowerPC based Embedded Boards + * + * + * The processor starts at 0x00000100 and the code is executed + * from flash. The code is organized to be at an other address + * in memory, but as long we don't jump around before relocating, + * board_init lies at a quite high address and when the cpu has + * jumped there, everything is ok. + * This works because the cpu gives the FLASH (CS0) the whole + * address space at startup, and board_init lies as a echo of + * the flash somewhere up there in the memory map. + * + * board_init will change CS0 to be positioned at the correct + * address and (s)dram will be positioned at address 0 + */ +#include <asm-offsets.h> +#include <config.h> +#include <mpc8xx.h> +#include <version.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> +#include <asm/u-boot.h> + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ + +/* + * Set up GOT: Global Offset Table + * + * Use r12 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(__bss_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +_start: + lis r3, CONFIG_SYS_IMMR@h /* position IMMR */ + mtspr 638, r3 + + /* Initialize machine status; enable machine check interrupt */ + /*----------------------------------------------------------------------*/ + li r3, MSR_KERNEL /* Set ME, RI flags */ + mtmsr r3 + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + mfspr r3, ICR /* clear Interrupt Cause Register */ + + /* Initialize debug port registers */ + /*----------------------------------------------------------------------*/ + xor r0, r0, r0 /* Clear R0 */ + mtspr LCTRL1, r0 /* Initialize debug port regs */ + mtspr LCTRL2, r0 + mtspr COUNTA, r0 + mtspr COUNTB, r0 + + /* Reset the caches */ + /*----------------------------------------------------------------------*/ + + mfspr r3, IC_CST /* Clear error bits */ + mfspr r3, DC_CST + + lis r3, IDC_UNALL@h /* Unlock all */ + mtspr IC_CST, r3 + mtspr DC_CST, r3 + + lis r3, IDC_INVALL@h /* Invalidate all */ + mtspr IC_CST, r3 + mtspr DC_CST, r3 + + lis r3, IDC_DISABLE@h /* Disable data cache */ + mtspr DC_CST, r3 + + lis r3, IDC_ENABLE@h /* Enable instruction cache */ + mtspr IC_CST, r3 + + /* invalidate all tlb's */ + /*----------------------------------------------------------------------*/ + + tlbia + isync + + /* + * Calculate absolute address in FLASH and jump there + *----------------------------------------------------------------------*/ + + lis r3, CONFIG_SYS_MONITOR_BASE@h + ori r3, r3, CONFIG_SYS_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r3 + blr + +in_flash: + + /* initialize some SPRs that are hard to access from C */ + /*----------------------------------------------------------------------*/ + + lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */ + ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */ + /* Note: R0 is still 0 here */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* + * Disable serialized ifetch and show cycles + * (i.e. set processor to normal mode). + * This is also a silicon bug workaround, see errata + */ + + li r2, 0x0007 + mtspr ICTRL, r2 + + /* Set up debug mode entry */ + + lis r2, CONFIG_SYS_DER@h + ori r2, r2, CONFIG_SYS_DER@l + mtspr DER, r2 + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*----------------------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + + bl board_init_f /* run 1st part of board init code (from Flash) */ + + /* NOTREACHED - board_init_f() does not return */ + + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG(SRR0, SRR1) + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG(SRR0, SRR1) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) + + /* No FPU on MPC8xx. This exception is not supposed to happen. + */ + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + /* On the MPC8xx, this is a software emulation interrupt. It occurs + * for all unimplemented and illegal instructions. + */ + STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) + + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) + STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) + STD_EXCEPTION(0x1400, DataTLBError, UnknownException) + + STD_EXCEPTION(0x1500, Reserved5, UnknownException) + STD_EXCEPTION(0x1600, Reserved6, UnknownException) + STD_EXCEPTION(0x1700, Reserved7, UnknownException) + STD_EXCEPTION(0x1800, Reserved8, UnknownException) + STD_EXCEPTION(0x1900, Reserved9, UnknownException) + STD_EXCEPTION(0x1a00, ReservedA, UnknownException) + STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + + STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) + STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException) + STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) + STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) + + + .globl _end_of_vectors +_end_of_vectors: + + + . = 0x2000 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* Cache functions. +*/ + .globl icache_enable +icache_enable: + SYNC + lis r3, IDC_INVALL@h + mtspr IC_CST, r3 + lis r3, IDC_ENABLE@h + mtspr IC_CST, r3 + blr + + .globl icache_disable +icache_disable: + SYNC + lis r3, IDC_DISABLE@h + mtspr IC_CST, r3 + blr + + .globl icache_status +icache_status: + mfspr r3, IC_CST + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl dcache_enable +dcache_enable: + lis r3, 0x0400 /* Set cache mode with MMU off */ + mtspr MD_CTR, r3 + + lis r3, IDC_INVALL@h + mtspr DC_CST, r3 + lis r3, IDC_ENABLE@h + mtspr DC_CST, r3 + blr + + .globl dcache_disable +dcache_disable: + SYNC + lis r3, IDC_DISABLE@h + mtspr DC_CST, r3 + lis r3, IDC_INVALL@h + mtspr DC_CST, r3 + blr + + .globl dcache_status +dcache_status: + mfspr r3, DC_CST + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl dc_read +dc_read: + mtspr DC_ADR, r3 + mfspr r3, DC_DAT + blr + +/* + * unsigned int get_immr (unsigned int mask) + * + * return (mask ? (IMMR & mask) : IMMR); + */ + .globl get_immr +get_immr: + mr r4,r3 /* save mask */ + mfspr r3, IMMR /* IMMR */ + cmpwi 0,r4,0 /* mask != 0 ? */ + beq 4f + and r3,r3,r4 /* IMMR & mask */ +4: + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + + + .globl wr_ic_cst +wr_ic_cst: + mtspr IC_CST, r3 + blr + + .globl rd_ic_cst +rd_ic_cst: + mfspr r3, IC_CST + blr + + .globl wr_ic_adr +wr_ic_adr: + mtspr IC_ADR, r3 + blr + + + .globl wr_dc_cst +wr_dc_cst: + mtspr DC_CST, r3 + blr + + .globl rd_dc_cst +rd_dc_cst: + mfspr r3, DC_CST + blr + + .globl wr_dc_adr +wr_dc_adr: + mtspr DC_ADR, r3 + blr + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + GET_GOT + mr r3, r5 /* Destination Address */ + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r12, r12, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r12 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f + add r0,r0,r11 + stw r0,0(r3) +2: bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ + li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + cmpwi r0,0 + add r0,r0,r11 + stw r4,0(r3) + beq- 5f + stw r0,0(r4) +5: bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(__bss_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + mflr r4 /* save link register */ + GET_GOT + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mtlr r4 /* restore link register */ + blr diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c new file mode 100644 index 0000000000..ec283d83fa --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/traps.c @@ -0,0 +1,168 @@ +/* + * linux/arch/powerpc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt(a)linuxppc.org) + * + * Modified by Cort Dougan (cort(a)cs.nmt.edu) + * and Paul Mackerras (paulus(a)cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. +*/ +#define END_OF_MEM 0x02000000 + +/* + * Trap & Exception support + */ + +static void print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void show_regs(struct pt_regs *regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +static void _exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +void MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + printf("Data parity signal\n"); + break; + case (0x80000000>>15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void AlignmentException(struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void ProgramCheckException(struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void SoftEmuException(struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + + +void UnknownException(struct pt_regs *regs) +{ + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +void DebugException(struct pt_regs *regs) +{ + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int addr_probe(uint *addr) +{ + return 0; +} diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h new file mode 100644 index 0000000000..3999a02b9c --- /dev/null +++ b/arch/powerpc/include/asm/8xx_immap.h @@ -0,0 +1,468 @@ +/* + * MPC8xx Internal Memory Map + * Copyright (c) 1997 Dan Malek (dmalek(a)jlc.net) + * + * The I/O on the MPC860 is comprised of blocks of special registers + * and the dual port ram for the Communication Processor Module. + * Within this space are functional units such as the SIU, memory + * controller, system timers, and other control functions. It is + * a combination that I found difficult to separate into logical + * functional files.....but anyone else is welcome to try. -- Dan + */ +#ifndef __IMMAP_8XX__ +#define __IMMAP_8XX__ + +/* System configuration registers. +*/ +typedef struct sys_conf { + uint sc_siumcr; + uint sc_sypcr; + uint sc_swt; + char res1[2]; + ushort sc_swsr; + uint sc_sipend; + uint sc_simask; + uint sc_siel; + uint sc_sivec; + uint sc_tesr; + char res2[0xc]; + uint sc_sdcr; + char res3[0x4c]; +} sysconf8xx_t; + +/* PCMCIA configuration registers. +*/ +typedef struct pcmcia_conf { + uint pcmc_pbr0; + uint pcmc_por0; + uint pcmc_pbr1; + uint pcmc_por1; + uint pcmc_pbr2; + uint pcmc_por2; + uint pcmc_pbr3; + uint pcmc_por3; + uint pcmc_pbr4; + uint pcmc_por4; + uint pcmc_pbr5; + uint pcmc_por5; + uint pcmc_pbr6; + uint pcmc_por6; + uint pcmc_pbr7; + uint pcmc_por7; + char res1[0x20]; + uint pcmc_pgcra; + uint pcmc_pgcrb; + uint pcmc_pscr; + char res2[4]; + uint pcmc_pipr; + char res3[4]; + uint pcmc_per; + char res4[4]; +} pcmconf8xx_t; + +/* Memory controller registers. +*/ +typedef struct mem_ctlr { + uint memc_br0; + uint memc_or0; + uint memc_br1; + uint memc_or1; + uint memc_br2; + uint memc_or2; + uint memc_br3; + uint memc_or3; + uint memc_br4; + uint memc_or4; + uint memc_br5; + uint memc_or5; + uint memc_br6; + uint memc_or6; + uint memc_br7; + uint memc_or7; + char res1[0x24]; + uint memc_mar; + uint memc_mcr; + char res2[4]; + uint memc_mamr; + uint memc_mbmr; + ushort memc_mstat; + ushort memc_mptpr; + uint memc_mdr; + char res3[0x80]; +} memctl8xx_t; + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + ushort sit_tbscr; + char res0[0x02]; + uint sit_tbreff0; + uint sit_tbreff1; + char res1[0x14]; + ushort sit_rtcsc; + char res2[0x02]; + uint sit_rtc; + uint sit_rtsec; + uint sit_rtcal; + char res3[0x10]; + ushort sit_piscr; + char res4[2]; + uint sit_pitc; + uint sit_pitr; + char res5[0x34]; +} sit8xx_t; + +#define TBSCR_TBIRQ_MASK ((ushort)0xff00) +#define TBSCR_REFA ((ushort)0x0080) +#define TBSCR_REFB ((ushort)0x0040) +#define TBSCR_REFAE ((ushort)0x0008) +#define TBSCR_REFBE ((ushort)0x0004) +#define TBSCR_TBF ((ushort)0x0002) +#define TBSCR_TBE ((ushort)0x0001) + +#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) +#define RTCSC_SEC ((ushort)0x0080) +#define RTCSC_ALR ((ushort)0x0040) +#define RTCSC_38K ((ushort)0x0010) +#define RTCSC_SIE ((ushort)0x0008) +#define RTCSC_ALE ((ushort)0x0004) +#define RTCSC_RTF ((ushort)0x0002) +#define RTCSC_RTE ((ushort)0x0001) + +#define PISCR_PIRQ_MASK ((ushort)0xff00) +#define PISCR_PS ((ushort)0x0080) +#define PISCR_PIE ((ushort)0x0004) +#define PISCR_PTF ((ushort)0x0002) +#define PISCR_PTE ((ushort)0x0001) + +/* Clocks and Reset. +*/ +typedef struct clk_and_reset { + uint car_sccr; + uint car_plprcr; + uint car_rsr; + char res[0x74]; /* Reserved area */ +} car8xx_t; + +/* System Integration Timers keys. +*/ +typedef struct sitk { + uint sitk_tbscrk; + uint sitk_tbreff0k; + uint sitk_tbreff1k; + uint sitk_tbk; + char res1[0x10]; + uint sitk_rtcsck; + uint sitk_rtck; + uint sitk_rtseck; + uint sitk_rtcalk; + char res2[0x10]; + uint sitk_piscrk; + uint sitk_pitck; + char res3[0x38]; +} sitk8xx_t; + +/* Clocks and reset keys. +*/ +typedef struct cark { + uint cark_sccrk; + uint cark_plprcrk; + uint cark_rsrk; + char res[0x474]; +} cark8xx_t; + +/* The key to unlock registers maintained by keep-alive power. +*/ +#define KAPWR_KEY ((unsigned int)0x55ccaa33) + +/* I2C +*/ +typedef struct i2c { + u_char i2c_i2mod; + char res1[3]; + u_char i2c_i2add; + char res2[3]; + u_char i2c_i2brg; + char res3[3]; + u_char i2c_i2com; + char res4[3]; + u_char i2c_i2cer; + char res5[3]; + u_char i2c_i2cmr; + char res6[0x8b]; +} i2c8xx_t; + +/* DMA control/status registers. +*/ +typedef struct sdma_csr { + char res1[4]; + uint sdma_sdar; + u_char sdma_sdsr; + char res3[3]; + u_char sdma_sdmr; + char res4[3]; + u_char sdma_idsr1; + char res5[3]; + u_char sdma_idmr1; + char res6[3]; + u_char sdma_idsr2; + char res7[3]; + u_char sdma_idmr2; + char res8[0x13]; +} sdma8xx_t; + +/* Communication Processor Module Interrupt Controller. +*/ +typedef struct cpm_ic { + ushort cpic_civr; + char res[0xe]; + uint cpic_cicr; + uint cpic_cipr; + uint cpic_cimr; + uint cpic_cisr; +} cpic8xx_t; + +/* Input/Output Port control/status registers. +*/ +typedef struct io_port { + ushort iop_padir; + ushort iop_papar; + ushort iop_paodr; + ushort iop_padat; + char res1[8]; + ushort iop_pcdir; + ushort iop_pcpar; + ushort iop_pcso; + ushort iop_pcdat; + ushort iop_pcint; + char res2[6]; + ushort iop_pddir; + ushort iop_pdpar; + char res3[2]; + ushort iop_pddat; + uint utmode; + char res4[4]; +} iop8xx_t; + +/* Communication Processor Module Timers +*/ +typedef struct cpm_timers { + ushort cpmt_tgcr; + char res1[0xe]; + ushort cpmt_tmr1; + ushort cpmt_tmr2; + ushort cpmt_trr1; + ushort cpmt_trr2; + ushort cpmt_tcr1; + ushort cpmt_tcr2; + ushort cpmt_tcn1; + ushort cpmt_tcn2; + ushort cpmt_tmr3; + ushort cpmt_tmr4; + ushort cpmt_trr3; + ushort cpmt_trr4; + ushort cpmt_tcr3; + ushort cpmt_tcr4; + ushort cpmt_tcn3; + ushort cpmt_tcn4; + ushort cpmt_ter1; + ushort cpmt_ter2; + ushort cpmt_ter3; + ushort cpmt_ter4; + char res2[8]; +} cpmtimer8xx_t; + +/* Finally, the Communication Processor stuff..... +*/ +typedef struct scc { /* Serial communication channels */ + uint scc_gsmrl; + uint scc_gsmrh; + ushort scc_psmr; + char res1[2]; + ushort scc_todr; + ushort scc_dsr; + ushort scc_scce; + char res2[2]; + ushort scc_sccm; + char res3; + u_char scc_sccs; + char res4[8]; +} scc_t; + +typedef struct smc { /* Serial management channels */ + char res1[2]; + ushort smc_smcmr; + char res2[2]; + u_char smc_smce; + char res3[3]; + u_char smc_smcm; + char res4[5]; +} smc_t; + +/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but + * it fits within the address space. + */ + +typedef struct fec { + uint fec_addr_low; /* lower 32 bits of station address */ + ushort fec_addr_high; /* upper 16 bits of station address */ + ushort res1; /* reserved */ + uint fec_hash_table_high; /* upper 32-bits of hash table */ + uint fec_hash_table_low; /* lower 32-bits of hash table */ + uint fec_r_des_start; /* beginning of Rx descriptor ring */ + uint fec_x_des_start; /* beginning of Tx descriptor ring */ + uint fec_r_buff_size; /* Rx buffer size */ + uint res2[9]; /* reserved */ + uint fec_ecntrl; /* ethernet control register */ + uint fec_ievent; /* interrupt event register */ + uint fec_imask; /* interrupt mask register */ + uint fec_ivec; /* interrupt level and vector status */ + uint fec_r_des_active; /* Rx ring updated flag */ + uint fec_x_des_active; /* Tx ring updated flag */ + uint res3[10]; /* reserved */ + uint fec_mii_data; /* MII data register */ + uint fec_mii_speed; /* MII speed control register */ + uint res4[17]; /* reserved */ + uint fec_r_bound; /* end of RAM (read-only) */ + uint fec_r_fstart; /* Rx FIFO start address */ + uint res5[6]; /* reserved */ + uint fec_x_fstart; /* Tx FIFO start address */ + uint res6[17]; /* reserved */ + uint fec_fun_code; /* fec SDMA function code */ + uint res7[3]; /* reserved */ + uint fec_r_cntrl; /* Rx control register */ + uint fec_r_hash; /* Rx hash register */ + uint res8[14]; /* reserved */ + uint fec_x_cntrl; /* Tx control register */ + uint res9[0x1e]; /* reserved */ +} fec_t; + +typedef struct comm_proc { + /* General control and status registers. + */ + ushort cp_cpcr; + u_char res1[2]; + ushort cp_rccr; + u_char res2; + u_char cp_rmds; + u_char res3[4]; + ushort cp_cpmcr1; + ushort cp_cpmcr2; + ushort cp_cpmcr3; + ushort cp_cpmcr4; + u_char res4[2]; + ushort cp_rter; + u_char res5[2]; + ushort cp_rtmr; + u_char res6[0x14]; + + /* Baud rate generators. + */ + uint cp_brgc1; + uint cp_brgc2; + uint cp_brgc3; + uint cp_brgc4; + + /* Serial Communication Channels. + */ + scc_t cp_scc[4]; + + /* Serial Management Channels. + */ + smc_t cp_smc[2]; + + /* Serial Peripheral Interface. + */ + ushort cp_spmode; + u_char res7[4]; + u_char cp_spie; + u_char res8[3]; + u_char cp_spim; + u_char res9[2]; + u_char cp_spcom; + u_char res10[2]; + + /* Parallel Interface Port. + */ + u_char res11[2]; + ushort cp_pipc; + u_char res12[2]; + ushort cp_ptpr; + uint cp_pbdir; + uint cp_pbpar; + u_char res13[2]; + ushort cp_pbodr; + uint cp_pbdat; + + /* Port E - MPC87x/88x only. + */ + uint cp_pedir; + uint cp_pepar; + uint cp_peso; + uint cp_peodr; + uint cp_pedat; + + /* Communications Processor Timing Register - + Contains RMII Timing for the FECs on MPC87x/88x only. + */ + uint cp_cptr; + + /* Serial Interface and Time Slot Assignment. + */ + uint cp_simode; + u_char cp_sigmr; + u_char res15; + u_char cp_sistr; + u_char cp_sicmr; + u_char res16[4]; + uint cp_sicr; + uint cp_sirp; + u_char res17[0xc]; + + u_char res19[0x100]; + u_char cp_siram[0x200]; + + /* The fast ethernet controller is not really part of the CPM, + * but it resides in the address space. + */ + fec_t cp_fec; + char res18[0xE00]; + + /* The MPC885 family has a second FEC here */ + fec_t cp_fec2; +#define cp_fec1 cp_fec /* consistency macro */ + + /* Dual Ported RAM follows. + * There are many different formats for this memory area + * depending upon the devices used and options chosen. + * Some processors don't have all of it populated. + */ + u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ + + /* Parameter RAM */ + union { + u_char cp_dparam[0x400]; + u16 cp_dparam16[0x200]; + }; +} cpm8xx_t; + +/* Internal memory map. +*/ +typedef struct immap { + sysconf8xx_t im_siu_conf; /* SIU Configuration */ + pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ + memctl8xx_t im_memctl; /* Memory Controller */ + sit8xx_t im_sit; /* System integration timers */ + car8xx_t im_clkrst; /* Clocks and reset */ + sitk8xx_t im_sitk; /* Sys int timer keys */ + cark8xx_t im_clkrstk; /* Clocks and reset keys */ + char res[96]; + i2c8xx_t im_i2c; /* I2C control/status */ + sdma8xx_t im_sdma; /* SDMA control/status */ + cpic8xx_t im_cpic; /* CPM Interrupt Controller */ + iop8xx_t im_ioport; /* IO Port control/status */ + cpmtimer8xx_t im_cpmtimer; /* CPM timers */ + cpm8xx_t im_cpm; /* Communication processor */ +} immap_t; + +#endif /* __IMMAP_8XX__ */ diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index 20c52fcddc..d3a83910b6 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -7,7 +7,9 @@ #include <asm/processor.h> /* bytes per L1 cache line */ -#if defined(CONFIG_PPC64BRIDGE) +#if defined(CONFIG_8xx) +#define L1_CACHE_SHIFT 4 +#elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 #elif defined(CONFIG_E500MC) #define L1_CACHE_SHIFT 6 @@ -70,4 +72,41 @@ void disable_cpc_sram(void); #define L2CACHE_NONE 0x03 /* NONE */ #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ +#ifdef CONFIG_8xx +/* Cache control on the MPC8xx is provided through some additional + * special purpose registers. + */ +#define IC_CST 560 /* Instruction cache control/status */ +#define IC_ADR 561 /* Address needed for some commands */ +#define IC_DAT 562 /* Read-only data register */ +#define DC_CST 568 /* Data cache control/status */ +#define DC_ADR 569 /* Address needed for some commands */ +#define DC_DAT 570 /* Read-only data register */ + +/* Commands. Only the first few are available to the instruction cache. +*/ +#define IDC_ENABLE 0x02000000 /* Cache enable */ +#define IDC_DISABLE 0x04000000 /* Cache disable */ +#define IDC_LDLCK 0x06000000 /* Load and lock */ +#define IDC_UNLINE 0x08000000 /* Unlock line */ +#define IDC_UNALL 0x0a000000 /* Unlock all */ +#define IDC_INVALL 0x0c000000 /* Invalidate all */ + +#define DC_FLINE 0x0e000000 /* Flush data cache line */ +#define DC_SFWT 0x01000000 /* Set forced writethrough mode */ +#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ +#define DC_SLES 0x05000000 /* Set little endian swap mode */ +#define DC_CLES 0x07000000 /* Clear little endian swap mode */ + +/* Status. +*/ +#define IDC_ENABLED 0x80000000 /* Cache is enabled */ +#define IDC_CERR1 0x00200000 /* Cache error 1 */ +#define IDC_CERR2 0x00100000 /* Cache error 2 */ +#define IDC_CERR3 0x00080000 /* Cache error 3 */ + +#define DC_DFWT 0x40000000 /* Data cache is forced write through */ +#define DC_LES 0x20000000 /* Caches are little endian mode */ +#endif /* CONFIG_8xx */ + #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 1c4a82ca99..35a02b61a4 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -19,6 +19,9 @@ struct arch_global_data { u8 sdhc_adapter; #endif #endif +#if defined(CONFIG_8xx) + unsigned long brg_clk; +#endif #if defined(CONFIG_CPM2) /* There are many clocks on the MPC8260 - see page 9-5 */ unsigned long vco_out; diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h new file mode 100644 index 0000000000..8db0fa2a1c --- /dev/null +++ b/arch/powerpc/include/asm/iopin_8xx.h @@ -0,0 +1,379 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * MPC8xx I/O port pin manipulation functions + * Roughly based on iopin_8260.h + */ + +#ifndef _ASM_IOPIN_8XX_H_ +#define _ASM_IOPIN_8XX_H_ + +#include <linux/types.h> +#include <asm/8xx_immap.h> + +#ifdef __KERNEL__ + +typedef struct { + u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ + u_char pin:5; /* port pin (0-31) */ + u_char flag:1; /* for whatever */ +} iopin_t; + +#define IOPIN_PORTA 0 +#define IOPIN_PORTB 1 +#define IOPIN_PORTC 2 +#define IOPIN_PORTD 3 + +static __inline__ void +iopin_set_high(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; + *datp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; + *datp |= (1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; + *datp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; + *datp |= (1 << (15 - iopin->pin)); + } +} + +static __inline__ void +iopin_set_low(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; + *datp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; + *datp &= ~(1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; + *datp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; + *datp &= ~(1 << (15 - iopin->pin)); + } +} + +static __inline__ uint +iopin_is_high(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; + return (*datp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; + return (*datp >> (31 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; + return (*datp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; + return (*datp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +static __inline__ uint +iopin_is_low(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; + return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; + return ((*datp >> (31 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; + return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; + return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +static __inline__ void +iopin_set_out(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; + *dirp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; + *dirp |= (1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; + *dirp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; + *dirp |= (1 << (15 - iopin->pin)); + } +} + +static __inline__ void +iopin_set_in(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; + *dirp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; + *dirp &= ~(1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; + *dirp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; + *dirp &= ~(1 << (15 - iopin->pin)); + } +} + +static __inline__ uint +iopin_is_out(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; + return (*dirp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; + return (*dirp >> (31 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; + return (*dirp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; + return (*dirp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +static __inline__ uint +iopin_is_in(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; + return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; + return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; + return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; + return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +static __inline__ void +iopin_set_odr(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; + *odrp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; + *odrp |= (1 << (31 - iopin->pin)); + } +} + +static __inline__ void +iopin_set_act(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; + *odrp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; + *odrp &= ~(1 << (31 - iopin->pin)); + } +} + +static __inline__ uint +iopin_is_odr(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; + return (*odrp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; + return (*odrp >> (31 - iopin->pin)) & 1; + } + return 0; +} + +static __inline__ uint +iopin_is_act(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; + return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; + return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +static __inline__ void +iopin_set_ded(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; + *parp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; + *parp |= (1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; + *parp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; + *parp |= (1 << (15 - iopin->pin)); + } +} + +static __inline__ void +iopin_set_gen(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; + *parp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; + *parp &= ~(1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; + *parp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; + *parp &= ~(1 << (15 - iopin->pin)); + } +} + +static __inline__ uint +iopin_is_ded(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; + return (*parp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; + return (*parp >> (31 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; + return (*parp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; + return (*parp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +static __inline__ uint +iopin_is_gen(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; + return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; + return ((*parp >> (31 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; + return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; + return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +static __inline__ void +iopin_set_opt2(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; + *sorp |= (1 << (15 - iopin->pin)); + } +} + +static __inline__ void +iopin_set_opt1(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; + *sorp &= ~(1 << (15 - iopin->pin)); + } +} + +static __inline__ uint +iopin_is_opt2(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; + return (*sorp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +static __inline__ uint +iopin_is_opt1(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; + return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +static __inline__ void +iopin_set_falledge(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; + *intp |= (1 << (15 - iopin->pin)); + } +} + +static __inline__ void +iopin_set_anyedge(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; + *intp &= ~(1 << (15 - iopin->pin)); + } +} + +static __inline__ uint +iopin_is_falledge(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; + return (*intp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +static __inline__ uint +iopin_is_anyedge(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; + return ((*intp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +#endif /* __KERNEL__ */ + +#endif /* _ASM_IOPIN_8XX_H_ */ diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h index aa6c304d2d..9a8afe1132 100644 --- a/arch/powerpc/include/asm/ppc.h +++ b/arch/powerpc/include/asm/ppc.h @@ -13,6 +13,14 @@ #ifndef __ASSEMBLY__ +#if defined(CONFIG_8xx) +#include <asm/8xx_immap.h> +#if defined(CONFIG_MPC866) +# define CONFIG_MPC866_FAMILY 1 +#elif defined(CONFIG_MPC885) +# define CONFIG_MPC885_FAMILY 1 +#endif +#endif #ifdef CONFIG_MPC86xx #include <mpc86xx.h> #include <asm/immap_86xx.h> @@ -35,6 +43,9 @@ #include <asm/arch/immap_lsch2.h> #endif +#if defined(CONFIG_8xx) +uint get_immr(uint); +#endif uint get_pvr(void); uint get_svr(void); uint rd_ic_cst(void); diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig new file mode 100644 index 0000000000..7c8ea971c3 --- /dev/null +++ b/arch/powerpc/lib/Kconfig @@ -0,0 +1,7 @@ +config CMD_IMMAP + bool "Enable various commands to dump IMMR information" + help + This enables various commands such as: + + siuinfo - print System Interface Unit (SIU) registers + memcinfo - print Memory Controller registers diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 9a3043abf8..4aa41836a2 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_BAT_RW) += bat_rw.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += extable.o +obj-$(CONFIG_CMD_IMMAP) += immap.o obj-y += interrupts.o obj-$(CONFIG_CMD_KGDB) += kgdb.o obj-y += stack.o diff --git a/arch/powerpc/lib/immap.c b/arch/powerpc/lib/immap.c new file mode 100644 index 0000000000..1beed1fa40 --- /dev/null +++ b/arch/powerpc/lib/immap.c @@ -0,0 +1,397 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * MPC8xx Internal Memory Map Functions + */ + +#include <common.h> +#include <command.h> + +#if defined(CONFIG_8xx) + +#include <asm/8xx_immap.h> +#include <commproc.h> +#include <asm/iopin_8xx.h> + +DECLARE_GLOBAL_DATA_PTR; + +int +do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + volatile sysconf8xx_t *sc = &immap->im_siu_conf; + + printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr); + printf ("SWT = %08x\n", sc->sc_swt); + printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask); + printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec); + printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr); + return 0; +} + +int +do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + volatile memctl8xx_t *memctl = &immap->im_memctl; + int nbanks = 8; + volatile uint *p = &memctl->memc_br0; + int i; + + for (i = 0; i < nbanks; i++, p += 2) { + if (i < 10) { + printf ("BR%d = %08x OR%d = %08x\n", + i, p[0], i, p[1]); + } else { + printf ("BR%d = %08x OR%d = %08x\n", + i, p[0], i, p[1]); + } + } + + printf ("MAR = %08x", memctl->memc_mar); + printf (" MCR = %08x\n", memctl->memc_mcr); + printf ("MAMR = %08x MBMR = %08x", + memctl->memc_mamr, memctl->memc_mbmr); + printf ("\nMSTAT = %04x\n", memctl->memc_mstat); + printf ("MPTPR = %04x MDR = %08x\n", + memctl->memc_mptpr, memctl->memc_mdr); + return 0; +} + +int +do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + volatile car8xx_t *car = &immap->im_clkrst; + + printf ("SCCR = %08x\n", car->car_sccr); + printf ("PLPRCR= %08x\n", car->car_plprcr); + printf ("RSR = %08x\n", car->car_rsr); + return 0; +} + +static int counter; + +static void +header(void) +{ + char *data = "\ + -------------------------------- --------------------------------\ + 00000000001111111111222222222233 00000000001111111111222222222233\ + 01234567890123456789012345678901 01234567890123456789012345678901\ + -------------------------------- --------------------------------\ + "; + int i; + + if (counter % 2) + putc('\n'); + counter = 0; + + for (i = 0; i < 4; i++, data += 79) + printf("%.79s\n", data); +} + +static void binary (char *label, uint value, int nbits) +{ + uint mask = 1 << (nbits - 1); + int i, second = (counter++ % 2); + + if (second) + putc (' '); + puts (label); + for (i = 32 + 1; i != nbits; i--) + putc (' '); + + while (mask != 0) { + if (value & mask) + putc ('1'); + else + putc ('0'); + mask >>= 1; + } + + if (second) + putc ('\n'); +} + +#define PA_NBITS 16 +#define PA_NB_ODR 8 +#define PB_NBITS 18 +#define PB_NB_ODR 16 +#define PC_NBITS 12 +#define PD_NBITS 13 + +int +do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + volatile iop8xx_t *iop = &immap->im_ioport; + volatile ushort *l, *r; + volatile uint *R; + + counter = 0; + header (); + + /* + * Ports A & B + */ + + l = &iop->iop_padir; + R = &immap->im_cpm.cp_pbdir; + binary ("PA_DIR", *l++, PA_NBITS); + binary ("PB_DIR", *R++, PB_NBITS); + binary ("PA_PAR", *l++, PA_NBITS); + binary ("PB_PAR", *R++, PB_NBITS); + binary ("PA_ODR", *l++, PA_NB_ODR); + binary ("PB_ODR", *R++, PB_NB_ODR); + binary ("PA_DAT", *l++, PA_NBITS); + binary ("PB_DAT", *R++, PB_NBITS); + + header (); + + /* + * Ports C & D + */ + + l = &iop->iop_pcdir; + r = &iop->iop_pddir; + binary ("PC_DIR", *l++, PC_NBITS); + binary ("PD_DIR", *r++, PD_NBITS); + binary ("PC_PAR", *l++, PC_NBITS); + binary ("PD_PAR", *r++, PD_NBITS); + binary ("PC_SO ", *l++, PC_NBITS); + binary (" ", 0, 0); + r++; + binary ("PC_DAT", *l++, PC_NBITS); + binary ("PD_DAT", *r++, PD_NBITS); + binary ("PC_INT", *l++, PC_NBITS); + + header (); + return 0; +} + +/* + * set the io pins + * this needs a clean up for smaller tighter code + * use *uint and set the address based on cmd + port + */ +int +do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + uint rcode = 0; + iopin_t iopin; + static uint port = 0; + static uint pin = 0; + static uint value = 0; + static enum { + DIR, + PAR, + SOR, + ODR, + DAT, + INT + } cmd = DAT; + + if (argc != 5) { + puts ("iopset PORT PIN CMD VALUE\n"); + return 1; + } + port = argv[1][0] - 'A'; + if (port > 3) + port -= 0x20; + if (port > 3) + rcode = 1; + pin = simple_strtol (argv[2], NULL, 10); + if (pin > 31) + rcode = 1; + + + switch (argv[3][0]) { + case 'd': + if (argv[3][1] == 'a') + cmd = DAT; + else if (argv[3][1] == 'i') + cmd = DIR; + else + rcode = 1; + break; + case 'p': + cmd = PAR; + break; + case 'o': + cmd = ODR; + break; + case 's': + cmd = SOR; + break; + case 'i': + cmd = INT; + break; + default: + printf ("iopset: unknown command %s\n", argv[3]); + rcode = 1; + } + if (argv[4][0] == '1') + value = 1; + else if (argv[4][0] == '0') + value = 0; + else + rcode = 1; + if (rcode == 0) { + iopin.port = port; + iopin.pin = pin; + iopin.flag = 0; + switch (cmd) { + case DIR: + if (value) + iopin_set_out (&iopin); + else + iopin_set_in (&iopin); + break; + case PAR: + if (value) + iopin_set_ded (&iopin); + else + iopin_set_gen (&iopin); + break; + case SOR: + if (value) + iopin_set_opt2 (&iopin); + else + iopin_set_opt1 (&iopin); + break; + case ODR: + if (value) + iopin_set_odr (&iopin); + else + iopin_set_act (&iopin); + break; + case DAT: + if (value) + iopin_set_high (&iopin); + else + iopin_set_low (&iopin); + break; + case INT: + if (value) + iopin_set_falledge (&iopin); + else + iopin_set_anyedge (&iopin); + break; + } + + } + return rcode; +} + +static void prbrg (int n, uint val) +{ + uint extc = (val >> 14) & 3; + uint cd = (val & CPM_BRG_CD_MASK) >> 1; + uint div16 = (val & CPM_BRG_DIV16) != 0; + + ulong clock = gd->cpu_clk; + + printf ("BRG%d:", n); + + if (val & CPM_BRG_RST) + puts (" RESET"); + else + puts (" "); + + if (val & CPM_BRG_EN) + puts (" ENABLED"); + else + puts (" DISABLED"); + + printf (" EXTC=%d", extc); + + if (val & CPM_BRG_ATB) + puts (" ATB"); + else + puts (" "); + + printf (" DIVIDER=%4d", cd); + if (extc == 0 && cd != 0) { + uint baudrate; + + if (div16) + baudrate = (clock / 16) / (cd + 1); + else + baudrate = clock / (cd + 1); + + printf ("=%6d bps", baudrate); + } else { + puts (" "); + } + + if (val & CPM_BRG_DIV16) + puts (" DIV16"); + else + puts (" "); + + putc ('\n'); +} + +int +do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + volatile cpm8xx_t *cp = &immap->im_cpm; + volatile uint *p = &cp->cp_brgc1; + int i = 1; + + while (i <= 4) + prbrg (i++, *p++); + + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + siuinfo, 1, 1, do_siuinfo, + "print System Interface Unit (SIU) registers", + "" +); + +U_BOOT_CMD( + memcinfo, 1, 1, do_memcinfo, + "print Memory Controller registers", + "" +); + +U_BOOT_CMD( + carinfo, 1, 1, do_carinfo, + "print Clocks and Reset registers", + "" +); + +U_BOOT_CMD( + iopinfo, 1, 1, do_iopinfo, + "print I/O Port registers", + "" +); + +U_BOOT_CMD( + iopset, 5, 0, do_iopset, + "set I/O Port registers", + "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1" +); + +U_BOOT_CMD( + brginfo, 1, 1, do_brginfo, + "print Baud Rate Generator (BRG) registers", + "" +); +#endif diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c index 3a5ad4d8d2..4cbb65eb68 100644 --- a/arch/powerpc/lib/time.c +++ b/arch/powerpc/lib/time.c @@ -64,10 +64,21 @@ int timer_init(void) { unsigned long temp; +#if defined(CONFIG_8xx) + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + /* unlock */ + immap->im_sitk.sitk_tbk = KAPWR_KEY; +#endif + /* reset */ asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;" : "=&r"(temp) ); +#if defined(CONFIG_8xx) + /* enable */ + immap->im_sit.sit_tbscr |= TBSCR_TBE; +#endif return (0); } /* ------------------------------------------------------------------------- */ diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 89b73f4fb9..8bf10ee3c1 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -183,7 +183,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_flash(bd); print_num("sramstart", bd->bi_sramstart); print_num("sramsize", bd->bi_sramsize); -#if defined(CONFIG_E500) +#if defined(CONFIG_8xx) || defined(CONFIG_E500) print_num("immr_base", bd->bi_immr_base); #endif print_num("bootflags", bd->bi_bootflags); diff --git a/cmd/reginfo.c b/cmd/reginfo.c index 8e4bec8c4b..850f28cabc 100644 --- a/cmd/reginfo.c +++ b/cmd/reginfo.c @@ -7,7 +7,9 @@ #include <common.h> #include <command.h> -#if defined(CONFIG_MPC86xx) +#if defined(CONFIG_8xx) +#include <mpc8xx.h> +#elif defined(CONFIG_MPC86xx) extern void mpc86xx_reginfo(void); #elif defined(CONFIG_MPC85xx) extern void mpc85xx_reginfo(void); @@ -16,7 +18,60 @@ extern void mpc85xx_reginfo(void); static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { -#if defined(CONFIG_MPC86xx) +#if defined(CONFIG_8xx) + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; + volatile sit8xx_t *timers = &immap->im_sit; + + /* Hopefully more PowerPC knowledgable people will add code to display + * other useful registers + */ + + printf ("\nSystem Configuration registers\n" + + "\tIMMR\t0x%08X\n", get_immr(0)); + + printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr); + printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr); + + printf("\tSWT\t0x%08X", sysconf->sc_swt); + printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr); + + printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", + sysconf->sc_sipend, sysconf->sc_simask); + printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", + sysconf->sc_siel, sysconf->sc_sivec); + printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", + sysconf->sc_tesr, sysconf->sc_sdcr); + + printf ("Memory Controller Registers\n" + + "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); + printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); + printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); + printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); + printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4); + printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5); + printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6); + printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7); + printf ("\n" + "\tmamr\t0x%08X\tmbmr\t0x%08X \n", + memctl->memc_mamr, memctl->memc_mbmr ); + printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n", + memctl->memc_mstat, memctl->memc_mptpr ); + printf("\tmdr\t0x%08X \n", memctl->memc_mdr); + + printf ("\nSystem Integration Timers\n" + "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", + timers->sit_tbscr, timers->sit_rtcsc); + printf("\tPISCR\t0x%08X \n", timers->sit_piscr); + + /* + * May be some CPM info here? + */ + +#elif defined(CONFIG_MPC86xx) mpc86xx_reginfo(); #elif defined(CONFIG_MPC85xx) diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index b8f9c7aedb..4d83ffd470 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -41,7 +41,7 @@ typedef struct bd_info { unsigned long bi_dsp_freq; /* dsp core frequency */ unsigned long bi_ddr_freq; /* ddr frequency */ #endif -#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_M68K) diff --git a/include/commproc.h b/include/commproc.h new file mode 100644 index 0000000000..5518cb325d --- /dev/null +++ b/include/commproc.h @@ -0,0 +1,687 @@ +/* + * MPC8xx Communication Processor Module. + * Copyright (c) 1997 Dan Malek (dmalek(a)jlc.net) + * + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * This file contains structures and information for the communication + * processor channels. Some CPM control and status is available + * throught the MPC8xx internal memory map. See immap.h for details. + * This file only contains what I need for the moment, not the total + * CPM capabilities. I (or someone else) will add definitions as they + * are needed. -- Dan + * + */ +#ifndef __CPM_8XX__ +#define __CPM_8XX__ + +#include <asm/8xx_immap.h> + +/* CPM Command register. +*/ +#define CPM_CR_RST ((ushort)0x8000) +#define CPM_CR_OPCODE ((ushort)0x0f00) +#define CPM_CR_CHAN ((ushort)0x00f0) +#define CPM_CR_FLG ((ushort)0x0001) + +/* Some commands (there are more...later) +*/ +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_INIT_RX ((ushort)0x0001) +#define CPM_CR_INIT_TX ((ushort)0x0002) +#define CPM_CR_HUNT_MODE ((ushort)0x0003) +#define CPM_CR_STOP_TX ((ushort)0x0004) +#define CPM_CR_RESTART_TX ((ushort)0x0006) +#define CPM_CR_SET_GADDR ((ushort)0x0008) + +/* Channel numbers. +*/ +#define CPM_CR_CH_SCC1 ((ushort)0x0000) +#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ +#define CPM_CR_CH_SCC2 ((ushort)0x0004) +#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ +#define CPM_CR_CH_SCC3 ((ushort)0x0008) +#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ +#define CPM_CR_CH_SCC4 ((ushort)0x000c) +#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ + +#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) + +/* + * DPRAM defines and allocation functions + */ +#define CPM_SERIAL_BASE 0x0800 +#define CPM_I2C_BASE 0x0820 +#define CPM_SPI_BASE 0x0840 +#define CPM_FEC_BASE 0x0860 +#define CPM_SERIAL2_BASE 0x08E0 +#define CPM_SCC_BASE 0x0900 +#define CPM_POST_BASE 0x0980 +#define CPM_WLKBD_BASE 0x0a00 + +#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ + +/* Export the base address of the communication processor registers + * and dual port ram. + */ +extern cpm8xx_t *cpmp; /* Pointer to comm processor */ + +/* Buffer descriptors used by many of the CPM protocols. +*/ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ + +/* Parameter RAM offsets. +*/ +#define PROFF_SCC1 ((uint)0x0000) +#define PROFF_IIC ((uint)0x0080) +#define PROFF_REVNUM ((uint)0x00b0) +#define PROFF_SCC2 ((uint)0x0100) +#define PROFF_SPI ((uint)0x0180) +#define PROFF_SCC3 ((uint)0x0200) +#define PROFF_SMC1 ((uint)0x0280) +#define PROFF_SCC4 ((uint)0x0300) +#define PROFF_SMC2 ((uint)0x0380) + +/* Define enough so I can at least use the serial port as a UART. + */ +typedef struct smc_uart { + ushort smc_rbase; /* Rx Buffer descriptor base address */ + ushort smc_tbase; /* Tx Buffer descriptor base address */ + u_char smc_rfcr; /* Rx function code */ + u_char smc_tfcr; /* Tx function code */ + ushort smc_mrblr; /* Max receive buffer length */ + uint smc_rstate; /* Internal */ + uint smc_idp; /* Internal */ + ushort smc_rbptr; /* Internal */ + ushort smc_ibc; /* Internal */ + uint smc_rxtmp; /* Internal */ + uint smc_tstate; /* Internal */ + uint smc_tdp; /* Internal */ + ushort smc_tbptr; /* Internal */ + ushort smc_tbc; /* Internal */ + uint smc_txtmp; /* Internal */ + ushort smc_maxidl; /* Maximum idle characters */ + ushort smc_tmpidl; /* Temporary idle counter */ + ushort smc_brklen; /* Last received break length */ + ushort smc_brkec; /* rcv'd break condition counter */ + ushort smc_brkcr; /* xmt break count register */ + ushort smc_rmask; /* Temporary bit mask */ + u_char res1[8]; + ushort smc_rpbase; /* Relocation pointer */ +} smc_uart_t; + +/* Function code bits. +*/ +#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ + +/* SMC uart mode register. +*/ +#define SMCMR_REN ((ushort)0x0001) +#define SMCMR_TEN ((ushort)0x0002) +#define SMCMR_DM ((ushort)0x000c) +#define SMCMR_SM_GCI ((ushort)0x0000) +#define SMCMR_SM_UART ((ushort)0x0020) +#define SMCMR_SM_TRANS ((ushort)0x0030) +#define SMCMR_SM_MASK ((ushort)0x0030) +#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ +#define SMCMR_REVD SMCMR_PM_EVEN +#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ +#define SMCMR_BS SMCMR_PEN +#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ +#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ +#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) + +/* SMC2 as Centronics parallel printer. It is half duplex, in that + * it can only receive or transmit. The parameter ram values for + * each direction are either unique or properly overlap, so we can + * include them in one structure. + */ +typedef struct smc_centronics { + ushort scent_rbase; + ushort scent_tbase; + u_char scent_cfcr; + u_char scent_smask; + ushort scent_mrblr; + uint scent_rstate; + uint scent_r_ptr; + ushort scent_rbptr; + ushort scent_r_cnt; + uint scent_rtemp; + uint scent_tstate; + uint scent_t_ptr; + ushort scent_tbptr; + ushort scent_t_cnt; + uint scent_ttemp; + ushort scent_max_sl; + ushort scent_sl_cnt; + ushort scent_character1; + ushort scent_character2; + ushort scent_character3; + ushort scent_character4; + ushort scent_character5; + ushort scent_character6; + ushort scent_character7; + ushort scent_character8; + ushort scent_rccm; + ushort scent_rccr; +} smc_cent_t; + +/* Centronics Status Mask Register. +*/ +#define SMC_CENT_F ((u_char)0x08) +#define SMC_CENT_PE ((u_char)0x04) +#define SMC_CENT_S ((u_char)0x02) + +/* SMC Event and Mask register. +*/ +#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ +#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ +#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ +#define SMCM_BSY ((unsigned char)0x04) +#define SMCM_TX ((unsigned char)0x02) +#define SMCM_RX ((unsigned char)0x01) + +/* Baud rate generators. +*/ +#define CPM_BRG_RST ((uint)0x00020000) +#define CPM_BRG_EN ((uint)0x00010000) +#define CPM_BRG_EXTC_INT ((uint)0x00000000) +#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) +#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) +#define CPM_BRG_ATB ((uint)0x00002000) +#define CPM_BRG_CD_MASK ((uint)0x00001ffe) +#define CPM_BRG_DIV16 ((uint)0x00000001) + +/* SI Clock Route Register +*/ +#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) +#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) +#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) +#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) +#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) +#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) + +/* SCCs. +*/ +#define SCC_GSMRH_IRP ((uint)0x00040000) +#define SCC_GSMRH_GDE ((uint)0x00010000) +#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) +#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) +#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) +#define SCC_GSMRH_REVD ((uint)0x00002000) +#define SCC_GSMRH_TRX ((uint)0x00001000) +#define SCC_GSMRH_TTX ((uint)0x00000800) +#define SCC_GSMRH_CDP ((uint)0x00000400) +#define SCC_GSMRH_CTSP ((uint)0x00000200) +#define SCC_GSMRH_CDS ((uint)0x00000100) +#define SCC_GSMRH_CTSS ((uint)0x00000080) +#define SCC_GSMRH_TFL ((uint)0x00000040) +#define SCC_GSMRH_RFW ((uint)0x00000020) +#define SCC_GSMRH_TXSY ((uint)0x00000010) +#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) +#define SCC_GSMRH_SYNL8 ((uint)0x00000008) +#define SCC_GSMRH_SYNL4 ((uint)0x00000004) +#define SCC_GSMRH_RTSM ((uint)0x00000002) +#define SCC_GSMRH_RSYN ((uint)0x00000001) + +#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ +#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) +#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) +#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) +#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) +#define SCC_GSMRL_TCI ((uint)0x10000000) +#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) +#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) +#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) +#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) +#define SCC_GSMRL_RINV ((uint)0x02000000) +#define SCC_GSMRL_TINV ((uint)0x01000000) +#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) +#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) +#define SCC_GSMRL_TPL_48 ((uint)0x00800000) +#define SCC_GSMRL_TPL_32 ((uint)0x00600000) +#define SCC_GSMRL_TPL_16 ((uint)0x00400000) +#define SCC_GSMRL_TPL_8 ((uint)0x00200000) +#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) +#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) +#define SCC_GSMRL_TPP_01 ((uint)0x00100000) +#define SCC_GSMRL_TPP_10 ((uint)0x00080000) +#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) +#define SCC_GSMRL_TEND ((uint)0x00040000) +#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) +#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) +#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) +#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) +#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) +#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) +#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) +#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) +#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) +#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) +#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) +#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) +#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) +#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) +#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ +#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) +#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) +#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) +#define SCC_GSMRL_ENR ((uint)0x00000020) +#define SCC_GSMRL_ENT ((uint)0x00000010) +#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) +#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) +#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) +#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) +#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) +#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) +#define SCC_GSMRL_MODE_UART ((uint)0x00000004) +#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) +#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) +#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) + +#define SCC_TODR_TOD ((ushort)0x8000) + +/* SCC Event and Mask register. +*/ +#define SCCM_TXE ((unsigned char)0x10) +#define SCCM_BSY ((unsigned char)0x04) +#define SCCM_TX ((unsigned char)0x02) +#define SCCM_RX ((unsigned char)0x01) + +typedef struct scc_param { + ushort scc_rbase; /* Rx Buffer descriptor base address */ + ushort scc_tbase; /* Tx Buffer descriptor base address */ + u_char scc_rfcr; /* Rx function code */ + u_char scc_tfcr; /* Tx function code */ + ushort scc_mrblr; /* Max receive buffer length */ + uint scc_rstate; /* Internal */ + uint scc_idp; /* Internal */ + ushort scc_rbptr; /* Internal */ + ushort scc_ibc; /* Internal */ + uint scc_rxtmp; /* Internal */ + uint scc_tstate; /* Internal */ + uint scc_tdp; /* Internal */ + ushort scc_tbptr; /* Internal */ + ushort scc_tbc; /* Internal */ + uint scc_txtmp; /* Internal */ + uint scc_rcrc; /* Internal */ + uint scc_tcrc; /* Internal */ +} sccp_t; + +/* Function code bits. +*/ +#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ + +/* CPM Ethernet through SCCx. + */ +typedef struct scc_enet { + sccp_t sen_genscc; + uint sen_cpres; /* Preset CRC */ + uint sen_cmask; /* Constant mask for CRC */ + uint sen_crcec; /* CRC Error counter */ + uint sen_alec; /* alignment error counter */ + uint sen_disfc; /* discard frame counter */ + ushort sen_pads; /* Tx short frame pad character */ + ushort sen_retlim; /* Retry limit threshold */ + ushort sen_retcnt; /* Retry limit counter */ + ushort sen_maxflr; /* maximum frame length register */ + ushort sen_minflr; /* minimum frame length register */ + ushort sen_maxd1; /* maximum DMA1 length */ + ushort sen_maxd2; /* maximum DMA2 length */ + ushort sen_maxd; /* Rx max DMA */ + ushort sen_dmacnt; /* Rx DMA counter */ + ushort sen_maxb; /* Max BD byte count */ + ushort sen_gaddr1; /* Group address filter */ + ushort sen_gaddr2; + ushort sen_gaddr3; + ushort sen_gaddr4; + uint sen_tbuf0data0; /* Save area 0 - current frame */ + uint sen_tbuf0data1; /* Save area 1 - current frame */ + uint sen_tbuf0rba; /* Internal */ + uint sen_tbuf0crc; /* Internal */ + ushort sen_tbuf0bcnt; /* Internal */ + ushort sen_paddrh; /* physical address (MSB) */ + ushort sen_paddrm; + ushort sen_paddrl; /* physical address (LSB) */ + ushort sen_pper; /* persistence */ + ushort sen_rfbdptr; /* Rx first BD pointer */ + ushort sen_tfbdptr; /* Tx first BD pointer */ + ushort sen_tlbdptr; /* Tx last BD pointer */ + uint sen_tbuf1data0; /* Save area 0 - current frame */ + uint sen_tbuf1data1; /* Save area 1 - current frame */ + uint sen_tbuf1rba; /* Internal */ + uint sen_tbuf1crc; /* Internal */ + ushort sen_tbuf1bcnt; /* Internal */ + ushort sen_txlen; /* Tx Frame length counter */ + ushort sen_iaddr1; /* Individual address filter */ + ushort sen_iaddr2; + ushort sen_iaddr3; + ushort sen_iaddr4; + ushort sen_boffcnt; /* Backoff counter */ + + /* NOTE: Some versions of the manual have the following items + * incorrectly documented. Below is the proper order. + */ + ushort sen_taddrh; /* temp address (MSB) */ + ushort sen_taddrm; + ushort sen_taddrl; /* temp address (LSB) */ +} scc_enet_t; + +/*********************************************************************/ + +/* SCC Event register as used by Ethernet. +*/ +#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ +#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* SCC Mode Register (PSMR) as used by Ethernet. +*/ +#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ + +/* Buffer descriptor control/status used by Ethernet receive. +*/ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. +*/ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/* SCC as UART +*/ +typedef struct scc_uart { + sccp_t scc_genscc; + uint scc_res1; /* Reserved */ + uint scc_res2; /* Reserved */ + ushort scc_maxidl; /* Maximum idle chars */ + ushort scc_idlc; /* temp idle counter */ + ushort scc_brkcr; /* Break count register */ + ushort scc_parec; /* receive parity error counter */ + ushort scc_frmec; /* receive framing error counter */ + ushort scc_nosec; /* receive noise counter */ + ushort scc_brkec; /* receive break condition counter */ + ushort scc_brkln; /* last received break length */ + ushort scc_uaddr1; /* UART address character 1 */ + ushort scc_uaddr2; /* UART address character 2 */ + ushort scc_rtemp; /* Temp storage */ + ushort scc_toseq; /* Transmit out of sequence char */ + ushort scc_char1; /* control character 1 */ + ushort scc_char2; /* control character 2 */ + ushort scc_char3; /* control character 3 */ + ushort scc_char4; /* control character 4 */ + ushort scc_char5; /* control character 5 */ + ushort scc_char6; /* control character 6 */ + ushort scc_char7; /* control character 7 */ + ushort scc_char8; /* control character 8 */ + ushort scc_rccm; /* receive control character mask */ + ushort scc_rccr; /* receive control character register */ + ushort scc_rlbc; /* receive last break character */ +} scc_uart_t; + +/* SCC Event and Mask registers when it is used as a UART. +*/ +#define UART_SCCM_GLR ((ushort)0x1000) +#define UART_SCCM_GLT ((ushort)0x0800) +#define UART_SCCM_AB ((ushort)0x0200) +#define UART_SCCM_IDL ((ushort)0x0100) +#define UART_SCCM_GRA ((ushort)0x0080) +#define UART_SCCM_BRKE ((ushort)0x0040) +#define UART_SCCM_BRKS ((ushort)0x0020) +#define UART_SCCM_CCR ((ushort)0x0008) +#define UART_SCCM_BSY ((ushort)0x0004) +#define UART_SCCM_TX ((ushort)0x0002) +#define UART_SCCM_RX ((ushort)0x0001) + +/* The SCC PSMR when used as a UART. +*/ +#define SCU_PSMR_FLC ((ushort)0x8000) +#define SCU_PSMR_SL ((ushort)0x4000) +#define SCU_PSMR_CL ((ushort)0x3000) +#define SCU_PSMR_UM ((ushort)0x0c00) +#define SCU_PSMR_FRZ ((ushort)0x0200) +#define SCU_PSMR_RZS ((ushort)0x0100) +#define SCU_PSMR_SYN ((ushort)0x0080) +#define SCU_PSMR_DRT ((ushort)0x0040) +#define SCU_PSMR_PEN ((ushort)0x0010) +#define SCU_PSMR_RPM ((ushort)0x000c) +#define SCU_PSMR_REVP ((ushort)0x0008) +#define SCU_PSMR_TPM ((ushort)0x0003) +#define SCU_PSMR_TEVP ((ushort)0x0003) + +/* CPM Transparent mode SCC. + */ +typedef struct scc_trans { + sccp_t st_genscc; + uint st_cpres; /* Preset CRC */ + uint st_cmask; /* Constant mask for CRC */ +} scc_trans_t; + +#define BD_SCC_TX_LAST ((ushort)0x0800) + +/* IIC parameter RAM. +*/ +typedef struct iic { + ushort iic_rbase; /* Rx Buffer descriptor base address */ + ushort iic_tbase; /* Tx Buffer descriptor base address */ + u_char iic_rfcr; /* Rx function code */ + u_char iic_tfcr; /* Tx function code */ + ushort iic_mrblr; /* Max receive buffer length */ + uint iic_rstate; /* Internal */ + uint iic_rdp; /* Internal */ + ushort iic_rbptr; /* Internal */ + ushort iic_rbc; /* Internal */ + uint iic_rxtmp; /* Internal */ + uint iic_tstate; /* Internal */ + uint iic_tdp; /* Internal */ + ushort iic_tbptr; /* Internal */ + ushort iic_tbc; /* Internal */ + uint iic_txtmp; /* Internal */ + uint iic_res; /* reserved */ + ushort iic_rpbase; /* Relocation pointer */ + ushort iic_res2; /* reserved */ +} iic_t; + +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; + ushort spi_rpbase; /* Relocation pointer */ + ushort spi_res2; +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) +#define SPMODE_PM(x) ((x) &0xF) + +/* HDLC parameter RAM. +*/ + +typedef struct hdlc_pram_s { + /* + * SCC parameter RAM + */ + ushort rbase; /* Rx Buffer descriptor base address */ + ushort tbase; /* Tx Buffer descriptor base address */ + uchar rfcr; /* Rx function code */ + uchar tfcr; /* Tx function code */ + ushort mrblr; /* Rx buffer length */ + ulong rstate; /* Rx internal state */ + ulong rptr; /* Rx internal data pointer */ + ushort rbptr; /* rb BD Pointer */ + ushort rcount; /* Rx internal byte count */ + ulong rtemp; /* Rx temp */ + ulong tstate; /* Tx internal state */ + ulong tptr; /* Tx internal data pointer */ + ushort tbptr; /* Tx BD pointer */ + ushort tcount; /* Tx byte count */ + ulong ttemp; /* Tx temp */ + ulong rcrc; /* temp receive CRC */ + ulong tcrc; /* temp transmit CRC */ + /* + * HDLC specific parameter RAM + */ + uchar res[4]; /* reserved */ + ulong c_mask; /* CRC constant */ + ulong c_pres; /* CRC preset */ + ushort disfc; /* discarded frame counter */ + ushort crcec; /* CRC error counter */ + ushort abtsc; /* abort sequence counter */ + ushort nmarc; /* nonmatching address rx cnt */ + ushort retrc; /* frame retransmission cnt */ + ushort mflr; /* maximum frame length reg */ + ushort max_cnt; /* maximum length counter */ + ushort rfthr; /* received frames threshold */ + ushort rfcnt; /* received frames count */ + ushort hmask; /* user defined frm addr mask */ + ushort haddr1; /* user defined frm address 1 */ + ushort haddr2; /* user defined frm address 2 */ + ushort haddr3; /* user defined frm address 3 */ + ushort haddr4; /* user defined frm address 4 */ + ushort tmp; /* temp */ + ushort tmp_mb; /* temp */ +} hdlc_pram_t; + +/* CPM interrupts. There are nearly 32 interrupts generated by CPM + * channels or devices. All of these are presented to the PPC core + * as a single interrupt. The CPM interrupt handler dispatches its + * own handlers, in a similar fashion to the PPC core handler. We + * use the table as defined in the manuals (i.e. no special high + * priority and SCC1 == SCCa, etc...). + */ +#define CPMVEC_NR 32 +#define CPMVEC_OFFSET 0x00010000 +#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) +#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) +#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) +#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) +#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) +#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) +#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) +#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) +#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) +#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) +#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) +#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) +#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) +#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) +#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) +#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) +#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) +#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) + +extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); + +/* CPM interrupt configuration vector. +*/ +#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ +#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ +#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ +#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ +#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ +#define CICR_IEN ((uint)0x00000080) /* Int. enable */ +#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ +#endif /* __CPM_8XX__ */ diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 33a2cd8057..fc081ab756 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -145,20 +145,6 @@ PLPRCR_MFI_MSK | \ PLPRCR_PDF_MSK) -/* Older chips (MPC860/862 et al) defines */ -#define PLPRCR_MF_MSK 0xFFF00000 /* Multiplication factor bits */ -#define PLPRCR_MF_SHIFT 20 /* Multiplication factor shift value */ - -#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ -#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ - -#define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */ -#define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */ -#define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */ -#define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */ -#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */ -#define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */ - /* Common defines */ #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ #define PLPRCR_CSRC 0x00000400 /* Clock Source */ diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index ce71ee9bc9..18783340d9 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -81,6 +81,52 @@ #define r30 30 #define r31 31 +#if defined(CONFIG_8xx) + +/* Some special registers */ + +#define ICR 148 /* Interrupt Cause Register (37-44) */ +#define DER 149 +#define COUNTA 150 /* Breakpoint Counter (37-44) */ +#define COUNTB 151 /* Breakpoint Counter (37-44) */ +#define LCTRL1 156 /* Load/Store Support (37-40) */ +#define LCTRL2 157 /* Load/Store Support (37-41) */ +#define ICTRL 158 + +#endif /* CONFIG_8xx */ + + +#if defined(CONFIG_8xx) + +/* Registers in the processor's internal memory map that we use. +*/ +#define SYPCR 0x00000004 +#define BR0 0x00000100 +#define OR0 0x00000104 +#define BR1 0x00000108 +#define OR1 0x0000010c +#define BR2 0x00000110 +#define OR2 0x00000114 +#define BR3 0x00000118 +#define OR3 0x0000011c +#define BR4 0x00000120 +#define OR4 0x00000124 + +#define MAR 0x00000164 +#define MCR 0x00000168 +#define MAMR 0x00000170 +#define MBMR 0x00000174 +#define MSTAT 0x00000178 +#define MPTPR 0x0000017a +#define MDR 0x0000017c + +#define TBSCR 0x00000200 +#define TBREFF0 0x00000204 + +#define PLPRCR 0x00000284 + +#endif + #define curptr r2 #define SYNC \ diff --git a/include/watchdog.h b/include/watchdog.h index 52f4c506b0..a3a2eeaf1b 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -72,6 +72,11 @@ int init_func_watchdog_reset(void); * Prototypes from $(CPU)/cpu.c. */ +/* MPC 8xx */ +#if defined(CONFIG_8xx) && !defined(__ASSEMBLY__) + void reset_8xx_watchdog(volatile immap_t *immr); +#endif + #if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__) void hw_watchdog_init(void); #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 95f27b6ead..1a7bc674cc 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -12,6 +12,10 @@ CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES CONFIG_83XX_PCICLK CONFIG_83XX_PCI_STREAMING CONFIG_88F5182 +CONFIG_8xx_CONS_NONE +CONFIG_8xx_CONS_SMC1 +CONFIG_8xx_CONS_SMC2 +CONFIG_8xx_GCLK_FREQ CONFIG_A003399_NOR_WORKAROUND CONFIG_A008044_WORKAROUND CONFIG_ACX517AKN @@ -709,6 +713,8 @@ CONFIG_ETHER_ON_FCC CONFIG_ETHER_ON_FCC1 CONFIG_ETHER_ON_FCC2 CONFIG_ETHER_ON_FCC3 +CONFIG_ETHER_ON_FEC1 +CONFIG_ETHER_ON_FEC2 CONFIG_ETHPRIME CONFIG_ETH_BUFSIZE CONFIG_ETH_RXSIZE @@ -764,6 +770,8 @@ CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN CONFIG_FEATURE_SH_EXTRA_QUIET CONFIG_FEATURE_SH_FANCY_PROMPT CONFIG_FEATURE_SH_STANDALONE_SHELL +CONFIG_FEC1_PHY +CONFIG_FEC2_PHY CONFIG_FEC_ENET_DEV CONFIG_FEC_FIXED_SPEED CONFIG_FEC_MXC_25M_REF_CLK @@ -1535,6 +1543,10 @@ CONFIG_MPC83XX_PCI2 CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME CONFIG_MPC85XX_PCI2 +CONFIG_MPC866 +CONFIG_MPC866_FAMILY +CONFIG_MPC885 +CONFIG_MPC885_FAMILY CONFIG_MPC8XXX_SPI CONFIG_MPC8xxx_DISABLE_BPTR CONFIG_MPLL_FREQ @@ -2515,6 +2527,7 @@ CONFIG_SYS_BR6_64M CONFIG_SYS_BR6_8M CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR7_PRELIM +CONFIG_SYS_BRGCLK_PRESCALE CONFIG_SYS_BUSCLK CONFIG_SYS_CACHELINE_SHIFT CONFIG_SYS_CACHE_ACR0 @@ -2921,6 +2934,7 @@ CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DEFAULT_VIDEO_MODE CONFIG_SYS_DEF_EEPROM_ADDR +CONFIG_SYS_DER CONFIG_SYS_DEVICE_NULLDEV CONFIG_SYS_DFU_DATA_BUF_SIZE CONFIG_SYS_DFU_MAX_FILE_SIZE @@ -4494,6 +4508,7 @@ CONFIG_SYS_PIOC_PPUDR_VAL CONFIG_SYS_PIOD_PDR_VAL1 CONFIG_SYS_PIOD_PPUDR_VAL CONFIG_SYS_PIO_MODE +CONFIG_SYS_PISCR CONFIG_SYS_PIT_BASE CONFIG_SYS_PIT_PRESCALE CONFIG_SYS_PIXIS_VBOOT_ENABLE @@ -4515,6 +4530,7 @@ CONFIG_SYS_PLL_BYPASS CONFIG_SYS_PLL_FDR CONFIG_SYS_PLL_ODR CONFIG_SYS_PLL_SETTLING_TIME +CONFIG_SYS_PLPRCR CONFIG_SYS_PLUG_BASE CONFIG_SYS_PMAN CONFIG_SYS_PMC_BASE @@ -4671,6 +4687,7 @@ CONFIG_SYS_SDIO_BASE0 CONFIG_SYS_SDIO_BASE1 CONFIG_SYS_SDIO_BASE2 CONFIG_SYS_SDIO_BASE3 +CONFIG_SYS_SDMR CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE @@ -4716,6 +4733,7 @@ CONFIG_SYS_SDRC_MR_VAL5 CONFIG_SYS_SDRC_TR_VAL CONFIG_SYS_SDRC_TR_VAL1 CONFIG_SYS_SDRC_TR_VAL2 +CONFIG_SYS_SDSR CONFIG_SYS_SD_VOLTAGE CONFIG_SYS_SEC_MON_ADDR CONFIG_SYS_SEC_MON_OFFSET @@ -4742,12 +4760,14 @@ CONFIG_SYS_SH_SDHI_NR_CHANNEL CONFIG_SYS_SICRH CONFIG_SYS_SICRL CONFIG_SYS_SIL1178_I2C +CONFIG_SYS_SIUMCR CONFIG_SYS_SJA1000_BASE CONFIG_SYS_SMC0_CYCLE0_VAL CONFIG_SYS_SMC0_MODE0_VAL CONFIG_SYS_SMC0_PULSE0_VAL CONFIG_SYS_SMC0_SETUP0_VAL CONFIG_SYS_SMC_CSR0_VAL +CONFIG_SYS_SMC_RXBUFLEN CONFIG_SYS_SMI_BASE CONFIG_SYS_SPANSION_BASE CONFIG_SYS_SPANSION_BOOT @@ -4812,9 +4832,11 @@ CONFIG_SYS_STATUS_OK CONFIG_SYS_STMICRO_BOOT CONFIG_SYS_SUPPORT_64BIT_DATA CONFIG_SYS_SXCNFG_VAL +CONFIG_SYS_SYPCR CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_SYSTEMACE_WIDTH CONFIG_SYS_TBIPA_VALUE +CONFIG_SYS_TBSCR CONFIG_SYS_TCLK CONFIG_SYS_TEXT_ADDR CONFIG_SYS_TEXT_BASE_NOR -- 2.12.0

2 1

[U-Boot] UBOOT For R-Car/Boards/H3SK (Over Xen Hypervisor )
by CruiserAbhi 07 Jul '17

07 Jul '17

Host Build Machine: UBUNTU 14.04Board: R CAR H3SK (http://elinux.org/R-Car/Boards/H3SK)Build Environment: YOCTO (Process: https://wiki.xenproject.org/wiki/Xen_AR ... Salvator-X)Problem: UBOOT didn’t even boot and neither BL2 booted as well (there was no prompt at all). In other words neither first stage bootloader Bl2 booted nor 2nd Stage bootloader UBOOT booted. 1. Without hypervisor linux booted2. With hypervisor, neither BL2 nor UBOOT working. Blank screen is the behavior.I am unable to understand what changes need to be incorporated in order for UBOOT to boot in Hypervisor enviornment. What am I missing ? Please kindly help -- View this message in context: http://u-boot.10912.n7.nabble.com/UBOOT-For-R-Car-Boards-H3SK-Over-Xen-Hype… Sent from the U-Boot mailing list archive at Nabble.com.

1 0

[U-Boot] [PATCH] am335x: sl50: Enable CONFIG_AUTOBOOT_KEYED
by Enric Balletbo i Serra 07 Jul '17

07 Jul '17

On startup the SL50 board halt at U-Boot prompt. Use CONFIG_AUTOBOOT_KEYED to enable autoboot for this board and define the <SPACE> key to get the U-Boot prompt. Signed-off-by: Enric Balletbo i Serra <enric.balletbo(a)collabora.com> --- configs/am335x_sl50_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 02ce013..855e1ca 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -23,7 +23,10 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_AUTOBOOT is not set +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y -- 2.9.3

2 1

[U-Boot] [PATCH v2] board/BuR/brppt1: fix MMC boot
by Hannes Schmelzer 07 Jul '17

07 Jul '17

since commit 'd5abcf94c7123167725fc22ace342f0d455093c1' - ti: boot: Register the MMC controllers in SPL in the same way as in u-boot MMC boot on brppt1 board is broken, with this commit we make our board working again. Signed-off-by: Hannes Schmelzer <hannes.schmelzer(a)br-automation.com> --- Changes in v2: - fix also the 'altbootcmd' environment variable include/configs/brppt1.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 10e8f88..07e743a 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -110,24 +110,24 @@ #ifdef CONFIG_MMC #define MMCARGS \ "dtbdev=mmc\0" \ -"dtbpart=0:1\0" \ +"dtbpart=1:1\0" \ "mmcroot0=setenv bootargs ${optargs_rot} ${optargs} console=${console}\0" \ "mmcroot1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ "root=/dev/mmcblk0p2 rootfstype=ext4\0" \ "mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \ "setenv simplefb 1; " \ - "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \ - "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \ + "ext4load mmc 1:1 ${loadaddr} /${kernel}; " \ + "ext4load mmc 1:1 ${ramaddr} /${ramdisk}; " \ "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \ "mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \ "setenv simplefb 0; " \ - "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \ + "ext4load mmc 1:2 ${loadaddr} /boot/${kernel}; " \ "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \ -"defboot=ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \ - "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \ +"defboot=ext4load mmc 1:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \ + "ext4load mmc 1:1 ${dtbaddr} /$dtb && run mmcboot0; " \ "run ramboot; run usbscript;\0" \ "bootlimit=1\0" \ -"altbootcmd=run mmcboot0;\0" \ +"altbootcmd=mmc dev 1; run mmcboot0;\0" \ "upduboot=dhcp; " \ "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0" @@ -178,7 +178,7 @@ MMCARGS #endif /* !CONFIG_SPL_BUILD*/ #define CONFIG_BOOTCOMMAND \ - "run defboot;" + "mmc dev 1; run defboot;" #ifdef CONFIG_NAND /* @@ -253,7 +253,7 @@ MMCARGS #elif defined(CONFIG_EMMC_BOOT) #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -- 1.9.1

2 1

[U-Boot] [PATCH v1 1/3] wdt: Fix spelling Resettting -> Resetting
by Andy Shevchenko 07 Jul '17

07 Jul '17

Fix spelling Resettting -> Resetting. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- drivers/watchdog/wdt-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index ab8a64c354..bb9ae80866 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -48,7 +48,7 @@ int wdt_expire_now(struct udevice *dev, ulong flags) int ret = 0; const struct wdt_ops *ops; - debug("WDT Resettting: %lu\n", flags); + debug("WDT Resetting: %lu\n", flags); ops = device_get_ops(dev); if (ops->expire_now) { return ops->expire_now(dev, flags); -- 2.11.0

5 15

[U-Boot] [PATCH v3] avr32: Retire AVR32 for good
by Andy Shevchenko 07 Jul '17

07 Jul '17

AVR32 is gone. It's already more than two years for no support in Buildroot, even longer there is no support in GCC (last version is heavily patched 4.2.4). Linux kernel v4.12 got rid of it (and v4.11 didn't build successfully). There is no good point to keep this support in U-Boot either. Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Tom Rini <trini(a)konsulko.com> Reviewed-by: Heiko Schocher <hs(a)denx.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- In v3: - should have run script after removal all leftovers - add tag (Heiko) To check the change, the best way is to apply and run % git show --stat -p -M -C -D .travis.yml | 6 +- MAINTAINERS | 6 - README | 8 +- arch/Kconfig | 5 - arch/avr32/Kconfig | 30 --- arch/avr32/Makefile | 8 - arch/avr32/config.mk | 17 -- arch/avr32/cpu/Makefile | 21 -- arch/avr32/cpu/at32ap700x/Makefile | 7 - arch/avr32/cpu/at32ap700x/clk.c | 82 ------ arch/avr32/cpu/at32ap700x/mmu.c | 78 ------ arch/avr32/cpu/at32ap700x/portmux.c | 278 -------------------- arch/avr32/cpu/at32ap700x/sm.h | 204 --------------- arch/avr32/cpu/cache.c | 81 ------ arch/avr32/cpu/config.mk | 6 - arch/avr32/cpu/cpu.c | 73 ------ arch/avr32/cpu/exception.c | 108 -------- arch/avr32/cpu/hsdramc.c | 101 -------- arch/avr32/cpu/hsdramc1.h | 143 ----------- arch/avr32/cpu/hsmc3.h | 126 --------- arch/avr32/cpu/interrupts.c | 112 -------- arch/avr32/cpu/mmc.c | 16 -- arch/avr32/cpu/portmux-gpio.c | 91 ------- arch/avr32/cpu/portmux-pio.c | 76 ------ arch/avr32/cpu/start.S | 268 -------------------- arch/avr32/cpu/u-boot.lds | 58 ----- arch/avr32/include/asm/arch-at32ap700x/addrspace.h | 65 ----- .../avr32/include/asm/arch-at32ap700x/cacheflush.h | 65 ----- .../include/asm/arch-at32ap700x/chip-features.h | 24 -- arch/avr32/include/asm/arch-at32ap700x/clk.h | 175 ------------- arch/avr32/include/asm/arch-at32ap700x/gpio.h | 48 ---- arch/avr32/include/asm/arch-at32ap700x/hardware.h | 70 ----- arch/avr32/include/asm/arch-at32ap700x/hmatrix.h | 45 ---- arch/avr32/include/asm/arch-at32ap700x/mmu.h | 66 ----- arch/avr32/include/asm/arch-at32ap700x/portmux.h | 76 ------ arch/avr32/include/asm/arch-common/portmux-pio.h | 122 --------- arch/avr32/include/asm/bitops.h | 14 - arch/avr32/include/asm/byteorder.h | 21 -- arch/avr32/include/asm/cache.h | 25 -- arch/avr32/include/asm/config.h | 13 - arch/avr32/include/asm/dma-mapping.h | 55 ---- arch/avr32/include/asm/global_data.h | 18 -- arch/avr32/include/asm/hmatrix-common.h | 115 --------- arch/avr32/include/asm/io.h | 77 ------ arch/avr32/include/asm/linkage.h | 0 arch/avr32/include/asm/posix_types.h | 128 ---------- arch/avr32/include/asm/processor.h | 81 ------ arch/avr32/include/asm/ptrace.h | 132 ---------- arch/avr32/include/asm/sdram.h | 37 --- arch/avr32/include/asm/sections.h | 16 -- arch/avr32/include/asm/setup.h | 134 ---------- arch/avr32/include/asm/string.h | 12 - arch/avr32/include/asm/sysreg.h | 281 --------------------- arch/avr32/include/asm/types.h | 71 ------ arch/avr32/include/asm/u-boot.h | 18 -- arch/avr32/include/asm/unaligned.h | 1 - arch/avr32/lib/Makefile | 13 - arch/avr32/lib/bootm.c | 213 ---------------- arch/avr32/lib/dram_init.c | 17 -- arch/avr32/lib/interrupts.c | 35 --- arch/avr32/lib/memset.S | 65 ----- board/atmel/atngw100/Kconfig | 15 -- board/atmel/atngw100/MAINTAINERS | 6 - board/atmel/atngw100/Makefile | 6 - board/atmel/atngw100/atngw100.c | 109 -------- board/atmel/atngw100mkii/Kconfig | 15 -- board/atmel/atngw100mkii/MAINTAINERS | 6 - board/atmel/atngw100mkii/Makefile | 6 - board/atmel/atngw100mkii/atngw100mkii.c | 125 --------- board/atmel/atstk1000/Kconfig | 15 -- board/atmel/atstk1000/MAINTAINERS | 6 - board/atmel/atstk1000/Makefile | 9 - board/atmel/atstk1000/atstk1000.c | 89 ------- board/in-circuit/grasshopper/Kconfig | 15 -- board/in-circuit/grasshopper/MAINTAINERS | 6 - board/in-circuit/grasshopper/Makefile | 10 - board/in-circuit/grasshopper/grasshopper.c | 87 ------- cmd/bdinfo.c | 11 - common/board_r.c | 13 +- configs/atngw100_defconfig | 26 -- configs/atngw100mkii_defconfig | 26 -- configs/atstk1002_defconfig | 22 -- configs/grasshopper_defconfig | 18 -- doc/README.AVR32 | 25 -- doc/README.AVR32-port-muxing | 208 --------------- doc/README.atmel_mci | 3 +- doc/README.scrapyard | 6 - doc/git-mailrc | 3 +- drivers/i2c/soft_i2c.c | 5 +- drivers/spi/Kconfig | 4 +- drivers/usb/gadget/atmel_usba_udc.h | 5 - drivers/usb/musb-new/musb_io.h | 2 +- drivers/video/atmel_lcdfb.c | 4 - drivers/video/cfb_console.c | 2 +- examples/standalone/stubs.c | 13 - include/asm-generic/u-boot.h | 4 - include/configs/atngw100.h | 129 ---------- include/configs/atngw100mkii.h | 150 ----------- include/configs/atstk1002.h | 148 ----------- include/configs/grasshopper.h | 145 ----------- include/linux/fb.h | 2 +- include/linux/stat.h | 4 +- scripts/checkstack.pl | 5 - scripts/config_whitelist.txt | 29 --- tools/buildman/README | 11 +- tools/moveconfig.py | 1 - 106 files changed, 20 insertions(+), 5886 deletions(-) delete mode 100644 arch/avr32/Kconfig delete mode 100644 arch/avr32/Makefile delete mode 100644 arch/avr32/config.mk delete mode 100644 arch/avr32/cpu/Makefile delete mode 100644 arch/avr32/cpu/at32ap700x/Makefile delete mode 100644 arch/avr32/cpu/at32ap700x/clk.c delete mode 100644 arch/avr32/cpu/at32ap700x/mmu.c delete mode 100644 arch/avr32/cpu/at32ap700x/portmux.c delete mode 100644 arch/avr32/cpu/at32ap700x/sm.h delete mode 100644 arch/avr32/cpu/cache.c delete mode 100644 arch/avr32/cpu/config.mk delete mode 100644 arch/avr32/cpu/cpu.c delete mode 100644 arch/avr32/cpu/exception.c delete mode 100644 arch/avr32/cpu/hsdramc.c delete mode 100644 arch/avr32/cpu/hsdramc1.h delete mode 100644 arch/avr32/cpu/hsmc3.h delete mode 100644 arch/avr32/cpu/interrupts.c delete mode 100644 arch/avr32/cpu/mmc.c delete mode 100644 arch/avr32/cpu/portmux-gpio.c delete mode 100644 arch/avr32/cpu/portmux-pio.c delete mode 100644 arch/avr32/cpu/start.S delete mode 100644 arch/avr32/cpu/u-boot.lds delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/addrspace.h delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/cacheflush.h delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/chip-features.h delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/clk.h delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/gpio.h delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/hardware.h delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/hmatrix.h delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/mmu.h delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/portmux.h delete mode 100644 arch/avr32/include/asm/arch-common/portmux-pio.h delete mode 100644 arch/avr32/include/asm/bitops.h delete mode 100644 arch/avr32/include/asm/byteorder.h delete mode 100644 arch/avr32/include/asm/cache.h delete mode 100644 arch/avr32/include/asm/config.h delete mode 100644 arch/avr32/include/asm/dma-mapping.h delete mode 100644 arch/avr32/include/asm/global_data.h delete mode 100644 arch/avr32/include/asm/hmatrix-common.h delete mode 100644 arch/avr32/include/asm/io.h delete mode 100644 arch/avr32/include/asm/linkage.h delete mode 100644 arch/avr32/include/asm/posix_types.h delete mode 100644 arch/avr32/include/asm/processor.h delete mode 100644 arch/avr32/include/asm/ptrace.h delete mode 100644 arch/avr32/include/asm/sdram.h delete mode 100644 arch/avr32/include/asm/sections.h delete mode 100644 arch/avr32/include/asm/setup.h delete mode 100644 arch/avr32/include/asm/string.h delete mode 100644 arch/avr32/include/asm/sysreg.h delete mode 100644 arch/avr32/include/asm/types.h delete mode 100644 arch/avr32/include/asm/u-boot.h delete mode 100644 arch/avr32/include/asm/unaligned.h delete mode 100644 arch/avr32/lib/Makefile delete mode 100644 arch/avr32/lib/bootm.c delete mode 100644 arch/avr32/lib/dram_init.c delete mode 100644 arch/avr32/lib/interrupts.c delete mode 100644 arch/avr32/lib/memset.S delete mode 100644 board/atmel/atngw100/Kconfig delete mode 100644 board/atmel/atngw100/MAINTAINERS delete mode 100644 board/atmel/atngw100/Makefile delete mode 100644 board/atmel/atngw100/atngw100.c delete mode 100644 board/atmel/atngw100mkii/Kconfig delete mode 100644 board/atmel/atngw100mkii/MAINTAINERS delete mode 100644 board/atmel/atngw100mkii/Makefile delete mode 100644 board/atmel/atngw100mkii/atngw100mkii.c delete mode 100644 board/atmel/atstk1000/Kconfig delete mode 100644 board/atmel/atstk1000/MAINTAINERS delete mode 100644 board/atmel/atstk1000/Makefile delete mode 100644 board/atmel/atstk1000/atstk1000.c delete mode 100644 board/in-circuit/grasshopper/Kconfig delete mode 100644 board/in-circuit/grasshopper/MAINTAINERS delete mode 100644 board/in-circuit/grasshopper/Makefile delete mode 100644 board/in-circuit/grasshopper/grasshopper.c delete mode 100644 configs/atngw100_defconfig delete mode 100644 configs/atngw100mkii_defconfig delete mode 100644 configs/atstk1002_defconfig delete mode 100644 configs/grasshopper_defconfig delete mode 100644 doc/README.AVR32 delete mode 100644 doc/README.AVR32-port-muxing delete mode 100644 include/configs/atngw100.h delete mode 100644 include/configs/atngw100mkii.h delete mode 100644 include/configs/atstk1002.h delete mode 100644 include/configs/grasshopper.h diff --git a/.travis.yml b/.travis.yml index 6f14ec2396..f7287ae254 100644 --- a/.travis.yml +++ b/.travis.yml @@ -60,7 +60,6 @@ env: before_script: # install toolchains based on TOOLCHAIN} variable - - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi @@ -138,10 +137,7 @@ matrix: - env: - BUILDMAN="arm946es" - env: - - BUILDMAN="atmel -x avr32" - - env: - - BUILDMAN="avr32" - TOOLCHAIN="avr32" + - BUILDMAN="atmel" - env: - BUILDMAN="aries" - env: diff --git a/MAINTAINERS b/MAINTAINERS index 957e27c40d..e979cc8a2e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -221,12 +221,6 @@ S: Maintained F: arch/arm/cpu/armv8/zynqmp/ F: arch/arm/include/asm/arch-zynqmp/ -AVR32 -M: Andreas Bießmann <andreas(a)biessmann.org> -S: Maintained -T: git git://git.denx.de/u-boot-avr32.git -F: arch/avr32/ - BUILDMAN M: Simon Glass <sjg(a)chromium.org> S: Maintained diff --git a/README b/README index 5f4f97cb01..54978c3349 100644 --- a/README +++ b/README @@ -136,7 +136,6 @@ Directory Hierarchy: /arch Architecture specific files /arc Files generic to ARC architecture /arm Files generic to ARM architecture - /avr32 Files generic to AVR32 architecture /m68k Files generic to m68k architecture /microblaze Files generic to microblaze architecture /mips Files generic to MIPS architecture @@ -320,9 +319,6 @@ The following options need to be configured: - Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS. -- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined) - Define exactly one, e.g. CONFIG_ATSTK1002 - - Marvell Family Member CONFIG_SYS_MVFS - define it if you want to enable multiple fs option at one time @@ -4810,9 +4806,9 @@ details; basically, the header defines the following image properties: LynxOS, pSOS, QNX, RTEMS, INTEGRITY; Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS, INTEGRITY). -* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86, +* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86, IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; - Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC). + Currently supported: ARM, Intel x86, MIPS, NDS32, Nios II, PowerPC). * Compression Type (uncompressed, gzip, bzip2) * Load Address * Entry Point diff --git a/arch/Kconfig b/arch/Kconfig index d04ab9f177..fe1b991041 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -23,10 +23,6 @@ config ARM select HAVE_PRIVATE_LIBGCC if !ARM64 select SUPPORT_OF_CONTROL -config AVR32 - bool "AVR32 architecture" - select CREATE_ARCH_SYMLINK - config M68K bool "M68000 architecture" select HAVE_PRIVATE_LIBGCC @@ -166,7 +162,6 @@ config SYS_CONFIG_NAME source "arch/arc/Kconfig" source "arch/arm/Kconfig" -source "arch/avr32/Kconfig" source "arch/m68k/Kconfig" source "arch/microblaze/Kconfig" source "arch/mips/Kconfig" diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig deleted file mode 100644 index eb3377486f..0000000000 --- a/arch/avr32/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -menu "AVR32 architecture" - depends on AVR32 - -config SYS_ARCH - default "avr32" - -choice - prompt "Target select" - optional - -config TARGET_ATNGW100 - bool "Support atngw100" - -config TARGET_ATNGW100MKII - bool "Support atngw100mkii" - -config TARGET_ATSTK1002 - bool "Support atstk1002" - -config TARGET_GRASSHOPPER - bool "Support grasshopper" - -endchoice - -source "board/atmel/atngw100/Kconfig" -source "board/atmel/atngw100mkii/Kconfig" -source "board/atmel/atstk1000/Kconfig" -source "board/in-circuit/grasshopper/Kconfig" - -endmenu diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile deleted file mode 100644 index e9b3184379..0000000000 --- a/arch/avr32/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -head-y := arch/avr32/cpu/start.o - -libs-y += arch/avr32/cpu/ -libs-y += arch/avr32/lib/ diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk deleted file mode 100644 index 469185e8b4..0000000000 --- a/arch/avr32/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := avr32-linux- -endif - -CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 - -PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections - -LDFLAGS_u-boot = --gc-sections --relax diff --git a/arch/avr32/cpu/Makefile b/arch/avr32/cpu/Makefile deleted file mode 100644 index e111db3e75..0000000000 --- a/arch/avr32/cpu/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# Copyright (C) 2005-2006 Atmel Corporation. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y += start.o - -obj-y += cpu.o -obj-$(CONFIG_SYS_HSDRAMC) += hsdramc.o -obj-y += exception.o -obj-y += cache.o -obj-y += interrupts.o -obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o -obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o -obj-y += mmc.o - -obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/ diff --git a/arch/avr32/cpu/at32ap700x/Makefile b/arch/avr32/cpu/at32ap700x/Makefile deleted file mode 100644 index 06f18963e2..0000000000 --- a/arch/avr32/cpu/at32ap700x/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := portmux.o clk.o mmu.o diff --git a/arch/avr32/cpu/at32ap700x/clk.c b/arch/avr32/cpu/at32ap700x/clk.c deleted file mode 100644 index 0fc6088e3e..0000000000 --- a/arch/avr32/cpu/at32ap700x/clk.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2005-2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> - -#include <asm/arch/clk.h> -#include <asm/arch/hardware.h> -#include <asm/arch/portmux.h> - -#include "sm.h" - -void clk_init(void) -{ - uint32_t cksel; - - /* in case of soft resets, disable watchdog */ - sm_writel(WDT_CTRL, SM_BF(KEY, 0x55)); - sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa)); - -#ifdef CONFIG_PLL - /* Initialize the PLL */ - sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES) - | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1) - | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1) - | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT) - | SM_BF(PLLOSC, 0) - | SM_BIT(PLLEN))); - - /* Wait for lock */ - while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ; -#endif - - /* Set up clocks for the CPU and all peripheral buses */ - cksel = 0; - if (CONFIG_SYS_CLKDIV_CPU) - cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1); - if (CONFIG_SYS_CLKDIV_HSB) - cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1); - if (CONFIG_SYS_CLKDIV_PBA) - cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1); - if (CONFIG_SYS_CLKDIV_PBB) - cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1); - sm_writel(PM_CKSEL, cksel); - -#ifdef CONFIG_PLL - /* Use PLL0 as main clock */ - sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); - -#ifdef CONFIG_LCD - /* Set up pixel clock for the LCDC */ - sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN)); -#endif -#endif -} - -unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, - unsigned long rate, unsigned long parent_rate) -{ - unsigned long divider; - - if (rate == 0 || parent_rate == 0) { - sm_writel(PM_GCCTRL(id), 0); - return 0; - } - - divider = (parent_rate + rate / 2) / rate; - if (divider <= 1) { - sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN)); - rate = parent_rate; - } else { - divider = min(255UL, divider / 2 - 1); - sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN) - | SM_BF(DIV, divider)); - rate = parent_rate / (2 * (divider + 1)); - } - - return rate; -} diff --git a/arch/avr32/cpu/at32ap700x/mmu.c b/arch/avr32/cpu/at32ap700x/mmu.c deleted file mode 100644 index f5e62f27eb..0000000000 --- a/arch/avr32/cpu/at32ap700x/mmu.c +++ /dev/null @@ -1,78 +0,0 @@ -#include <common.h> -#include <asm/arch/mmu.h> -#include <asm/sysreg.h> - -void mmu_init_r(unsigned long dest_addr) -{ - uintptr_t vmr_table_addr; - - /* Round monitor address down to the nearest page boundary */ - dest_addr &= MMU_PAGE_ADDR_MASK; - - /* Initialize TLB entry 0 to cover the monitor, and lock it */ - sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V)); - sysreg_write(TLBELO, dest_addr | MMU_VMR_CACHE_WRBACK); - sysreg_write(MMUCR, SYSREG_BF(DRP, 0) | SYSREG_BF(DLA, 1) - | SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M)); - __builtin_tlbw(); - - /* - * Calculate the address of the VM range table in a PC-relative - * manner to make sure we hit the SDRAM and not the flash. - */ - vmr_table_addr = (uintptr_t)&mmu_vmr_table; - sysreg_write(PTBR, vmr_table_addr); - printf("VMR table @ 0x%08lx\n", vmr_table_addr); - - /* Enable paging */ - sysreg_write(MMUCR, SYSREG_BF(DRP, 1) | SYSREG_BF(DLA, 1) - | SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M) | SYSREG_BIT(E)); -} - -int mmu_handle_tlb_miss(void) -{ - const struct mmu_vm_range *vmr_table; - const struct mmu_vm_range *vmr; - unsigned int fault_pgno; - int first, last; - - fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT; - vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR); - - /* Do a binary search through the VM ranges */ - first = 0; - last = CONFIG_SYS_NR_VM_REGIONS; - while (first < last) { - unsigned int start; - int middle; - - /* Pick the entry in the middle of the remaining range */ - middle = (first + last) >> 1; - vmr = &vmr_table[middle]; - start = vmr->virt_pgno; - - /* Do the bisection thing */ - if (fault_pgno < start) { - last = middle; - } else if (fault_pgno >= (start + vmr->nr_pages)) { - first = middle + 1; - } else { - /* Got it; let's slam it into the TLB */ - uint32_t tlbelo; - - tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK; - tlbelo |= fault_pgno << MMU_PAGE_SHIFT; - sysreg_write(TLBELO, tlbelo); - __builtin_tlbw(); - - /* Zero means success */ - return 0; - } - } - - /* - * Didn't find any matching entries. Return a nonzero value to - * indicate that this should be treated as a fatal exception. - */ - return -1; -} diff --git a/arch/avr32/cpu/at32ap700x/portmux.c b/arch/avr32/cpu/at32ap700x/portmux.c deleted file mode 100644 index 58327bac87..0000000000 --- a/arch/avr32/cpu/at32ap700x/portmux.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> - -#include <asm/arch/chip-features.h> -#include <asm/arch/hardware.h> -#include <asm/arch/portmux.h> - -/* - * Lots of small functions here. We depend on --gc-sections getting - * rid of the ones we don't need. - */ -void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, - unsigned long flags, unsigned long drive_strength) -{ - unsigned long porte_mask = 0; - - if (bus_width > 16) - portmux_select_peripheral(PORTMUX_PORT_E, 0xffff, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); - if (addr_width > 23) - porte_mask |= (((1 << (addr_width - 23)) - 1) & 7) << 16; - if (flags & PORTMUX_EBI_CS(2)) - porte_mask |= 1 << 25; - if (flags & PORTMUX_EBI_CS(4)) - porte_mask |= 1 << 21; - if (flags & PORTMUX_EBI_CS(5)) - porte_mask |= 1 << 22; - if (flags & (PORTMUX_EBI_CF(0) | PORTMUX_EBI_CF(1))) - porte_mask |= (1 << 19) | (1 << 20) | (1 << 23); - - portmux_select_peripheral(PORTMUX_PORT_E, porte_mask, - PORTMUX_FUNC_A, 0); - - if (flags & PORTMUX_EBI_NWAIT) - portmux_select_peripheral(PORTMUX_PORT_E, 1 << 24, - PORTMUX_FUNC_A, PORTMUX_PULL_UP); -} - -#ifdef AT32AP700x_CHIP_HAS_MACB -void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength) -{ - unsigned long portc_mask; - - portc_mask = (1 << 3) /* TXD0 */ - | (1 << 4) /* TXD1 */ - | (1 << 7) /* TXEN */ - | (1 << 8) /* TXCK */ - | (1 << 9) /* RXD0 */ - | (1 << 10) /* RXD1 */ - | (1 << 13) /* RXER */ - | (1 << 15) /* RXDV */ - | (1 << 16) /* MDC */ - | (1 << 17); /* MDIO */ - - if (flags & PORTMUX_MACB_MII) - portc_mask |= (1 << 0) /* COL */ - | (1 << 1) /* CRS */ - | (1 << 2) /* TXER */ - | (1 << 5) /* TXD2 */ - | (1 << 6) /* TXD3 */ - | (1 << 11) /* RXD2 */ - | (1 << 12) /* RXD3 */ - | (1 << 14); /* RXCK */ - - if (flags & PORTMUX_MACB_SPEED) - portc_mask |= (1 << 18);/* SPD */ - - /* REVISIT: Some pins are probably pure outputs */ - portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); -} - -void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength) -{ - unsigned long portc_mask = 0; - unsigned long portd_mask; - - portd_mask = (1 << 13) /* TXD0 */ - | (1 << 14) /* TXD1 */ - | (1 << 11) /* TXEN */ - | (1 << 12) /* TXCK */ - | (1 << 10) /* RXD0 */ - | (1 << 6) /* RXD1 */ - | (1 << 5) /* RXER */ - | (1 << 4) /* RXDV */ - | (1 << 3) /* MDC */ - | (1 << 2); /* MDIO */ - - if (flags & PORTMUX_MACB_MII) - portc_mask = (1 << 19) /* COL */ - | (1 << 23) /* CRS */ - | (1 << 26) /* TXER */ - | (1 << 27) /* TXD2 */ - | (1 << 28) /* TXD3 */ - | (1 << 29) /* RXD2 */ - | (1 << 30) /* RXD3 */ - | (1 << 24); /* RXCK */ - - if (flags & PORTMUX_MACB_SPEED) - portd_mask |= (1 << 15);/* SPD */ - - /* REVISIT: Some pins are probably pure outputs */ - portmux_select_peripheral(PORTMUX_PORT_D, portd_mask, - PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); - portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, - PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_MMCI -void portmux_enable_mmci(unsigned int slot, unsigned long flags, - unsigned long drive_strength) -{ - unsigned long mask; - unsigned long portmux_flags = PORTMUX_PULL_UP; - - /* First, the common CLK signal. It doesn't need a pull-up */ - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 10, - PORTMUX_FUNC_A, 0); - - if (flags & PORTMUX_MMCI_EXT_PULLUP) - portmux_flags = 0; - - /* Then, the per-slot signals */ - switch (slot) { - case 0: - mask = (1 << 11) | (1 << 12); /* CMD and DATA0 */ - if (flags & PORTMUX_MMCI_4BIT) - /* DATA1..DATA3 */ - mask |= (1 << 13) | (1 << 14) | (1 << 15); - portmux_select_peripheral(PORTMUX_PORT_A, mask, - PORTMUX_FUNC_A, portmux_flags); - break; - case 1: - mask = (1 << 6) | (1 << 7); /* CMD and DATA0 */ - if (flags & PORTMUX_MMCI_4BIT) - /* DATA1..DATA3 */ - mask |= (1 << 8) | (1 << 9) | (1 << 10); - portmux_select_peripheral(PORTMUX_PORT_B, mask, - PORTMUX_FUNC_B, portmux_flags); - break; - } -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_SPI -void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength) -{ - unsigned long pin_mask; - - /* MOSI and SCK */ - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 1) | (1 << 2), - PORTMUX_FUNC_A, 0); - /* MISO may float */ - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 0, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); - - /* Set up NPCSx as GPIO outputs, initially high */ - pin_mask = (cs_mask & 7) << 3; - if (cs_mask & (1 << 3)) - pin_mask |= 1 << 20; - - portmux_select_gpio(PORTMUX_PORT_A, pin_mask, - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); -} - -void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength) -{ - /* MOSI and SCK */ - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 1) | (1 << 5), - PORTMUX_FUNC_B, 0); - /* MISO may float */ - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 0, - PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); - - /* Set up NPCSx as GPIO outputs, initially high */ - portmux_select_gpio(PORTMUX_PORT_B, (cs_mask & 7) << 2, - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); - portmux_select_gpio(PORTMUX_PORT_A, (cs_mask & 8) << (27 - 3), - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_LCDC -void portmux_enable_lcdc(int pin_config) -{ - unsigned long portc_mask = 0; - unsigned long portd_mask = 0; - unsigned long porte_mask = 0; - - switch (pin_config) { - case 0: - portc_mask = (1 << 19) /* CC */ - | (1 << 20) /* HSYNC */ - | (1 << 21) /* PCLK */ - | (1 << 22) /* VSYNC */ - | (1 << 23) /* DVAL */ - | (1 << 24) /* MODE */ - | (1 << 25) /* PWR */ - | (1 << 26) /* DATA0 */ - | (1 << 27) /* DATA1 */ - | (1 << 28) /* DATA2 */ - | (1 << 29) /* DATA3 */ - | (1 << 30) /* DATA4 */ - | (1 << 31); /* DATA5 */ - - portd_mask = (1 << 0) /* DATA6 */ - | (1 << 1) /* DATA7 */ - | (1 << 2) /* DATA8 */ - | (1 << 3) /* DATA9 */ - | (1 << 4) /* DATA10 */ - | (1 << 5) /* DATA11 */ - | (1 << 6) /* DATA12 */ - | (1 << 7) /* DATA13 */ - | (1 << 8) /* DATA14 */ - | (1 << 9) /* DATA15 */ - | (1 << 10) /* DATA16 */ - | (1 << 11) /* DATA17 */ - | (1 << 12) /* DATA18 */ - | (1 << 13) /* DATA19 */ - | (1 << 14) /* DATA20 */ - | (1 << 15) /* DATA21 */ - | (1 << 16) /* DATA22 */ - | (1 << 17); /* DATA23 */ - break; - - case 1: - portc_mask = (1 << 20) /* HSYNC */ - | (1 << 21) /* PCLK */ - | (1 << 22) /* VSYNC */ - | (1 << 25) /* PWR */ - | (1 << 31); /* DATA5 */ - - portd_mask = (1 << 0) /* DATA6 */ - | (1 << 1) /* DATA7 */ - | (1 << 7) /* DATA13 */ - | (1 << 8) /* DATA14 */ - | (1 << 9) /* DATA15 */ - | (1 << 16) /* DATA22 */ - | (1 << 17); /* DATA23 */ - - porte_mask = (1 << 0) /* CC */ - | (1 << 1) /* DVAL */ - | (1 << 2) /* MODE */ - | (1 << 3) /* DATA0 */ - | (1 << 4) /* DATA1 */ - | (1 << 5) /* DATA2 */ - | (1 << 6) /* DATA3 */ - | (1 << 7) /* DATA4 */ - | (1 << 8) /* DATA8 */ - | (1 << 9) /* DATA9 */ - | (1 << 10) /* DATA10 */ - | (1 << 11) /* DATA11 */ - | (1 << 12) /* DATA12 */ - | (1 << 13) /* DATA16 */ - | (1 << 14) /* DATA17 */ - | (1 << 15) /* DATA18 */ - | (1 << 16) /* DATA19 */ - | (1 << 17) /* DATA20 */ - | (1 << 18); /* DATA21 */ - break; - } - - /* REVISIT: Some pins are probably pure outputs */ - portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); - portmux_select_peripheral(PORTMUX_PORT_D, portd_mask, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); - portmux_select_peripheral(PORTMUX_PORT_E, porte_mask, - PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); -} -#endif diff --git a/arch/avr32/cpu/at32ap700x/sm.h b/arch/avr32/cpu/at32ap700x/sm.h deleted file mode 100644 index 9a3804efe4..0000000000 --- a/arch/avr32/cpu/at32ap700x/sm.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Register definitions for System Manager - */ -#ifndef __CPU_AT32AP_SM_H__ -#define __CPU_AT32AP_SM_H__ - -/* SM register offsets */ -#define SM_PM_MCCTRL 0x0000 -#define SM_PM_CKSEL 0x0004 -#define SM_PM_CPU_MASK 0x0008 -#define SM_PM_HSB_MASK 0x000c -#define SM_PM_PBA_MASK 0x0010 -#define SM_PM_PBB_MASK 0x0014 -#define SM_PM_PLL0 0x0020 -#define SM_PM_PLL1 0x0024 -#define SM_PM_VCTRL 0x0030 -#define SM_PM_VMREF 0x0034 -#define SM_PM_VMV 0x0038 -#define SM_PM_IER 0x0040 -#define SM_PM_IDR 0x0044 -#define SM_PM_IMR 0x0048 -#define SM_PM_ISR 0x004c -#define SM_PM_ICR 0x0050 -#define SM_PM_GCCTRL(x) (0x0060 + 4 * x) -#define SM_RTC_CTRL 0x0080 -#define SM_RTC_VAL 0x0084 -#define SM_RTC_TOP 0x0088 -#define SM_RTC_IER 0x0090 -#define SM_RTC_IDR 0x0094 -#define SM_RTC_IMR 0x0098 -#define SM_RTC_ISR 0x009c -#define SM_RTC_ICR 0x00a0 -#define SM_WDT_CTRL 0x00b0 -#define SM_WDT_CLR 0x00b4 -#define SM_WDT_EXT 0x00b8 -#define SM_RC_RCAUSE 0x00c0 -#define SM_EIM_IER 0x0100 -#define SM_EIM_IDR 0x0104 -#define SM_EIM_IMR 0x0108 -#define SM_EIM_ISR 0x010c -#define SM_EIM_ICR 0x0110 -#define SM_EIM_MODE 0x0114 -#define SM_EIM_EDGE 0x0118 -#define SM_EIM_LEVEL 0x011c -#define SM_EIM_TEST 0x0120 -#define SM_EIM_NMIC 0x0124 - -/* Bitfields in PM_CKSEL */ -#define SM_CPUSEL_OFFSET 0 -#define SM_CPUSEL_SIZE 3 -#define SM_CPUDIV_OFFSET 7 -#define SM_CPUDIV_SIZE 1 -#define SM_HSBSEL_OFFSET 8 -#define SM_HSBSEL_SIZE 3 -#define SM_HSBDIV_OFFSET 15 -#define SM_HSBDIV_SIZE 1 -#define SM_PBASEL_OFFSET 16 -#define SM_PBASEL_SIZE 3 -#define SM_PBADIV_OFFSET 23 -#define SM_PBADIV_SIZE 1 -#define SM_PBBSEL_OFFSET 24 -#define SM_PBBSEL_SIZE 3 -#define SM_PBBDIV_OFFSET 31 -#define SM_PBBDIV_SIZE 1 - -/* Bitfields in PM_PLL0 */ -#define SM_PLLEN_OFFSET 0 -#define SM_PLLEN_SIZE 1 -#define SM_PLLOSC_OFFSET 1 -#define SM_PLLOSC_SIZE 1 -#define SM_PLLOPT_OFFSET 2 -#define SM_PLLOPT_SIZE 3 -#define SM_PLLDIV_OFFSET 8 -#define SM_PLLDIV_SIZE 8 -#define SM_PLLMUL_OFFSET 16 -#define SM_PLLMUL_SIZE 8 -#define SM_PLLCOUNT_OFFSET 24 -#define SM_PLLCOUNT_SIZE 6 -#define SM_PLLTEST_OFFSET 31 -#define SM_PLLTEST_SIZE 1 - -/* Bitfields in PM_VCTRL */ -#define SM_VAUTO_OFFSET 0 -#define SM_VAUTO_SIZE 1 -#define SM_PM_VCTRL_VAL_OFFSET 8 -#define SM_PM_VCTRL_VAL_SIZE 7 - -/* Bitfields in PM_VMREF */ -#define SM_REFSEL_OFFSET 0 -#define SM_REFSEL_SIZE 4 - -/* Bitfields in PM_VMV */ -#define SM_PM_VMV_VAL_OFFSET 0 -#define SM_PM_VMV_VAL_SIZE 8 - -/* Bitfields in PM_ICR */ -#define SM_LOCK0_OFFSET 0 -#define SM_LOCK0_SIZE 1 -#define SM_LOCK1_OFFSET 1 -#define SM_LOCK1_SIZE 1 -#define SM_WAKE_OFFSET 2 -#define SM_WAKE_SIZE 1 -#define SM_VOK_OFFSET 3 -#define SM_VOK_SIZE 1 -#define SM_VMRDY_OFFSET 4 -#define SM_VMRDY_SIZE 1 -#define SM_CKRDY_OFFSET 5 -#define SM_CKRDY_SIZE 1 - -/* Bitfields in PM_GCCTRL */ -#define SM_OSCSEL_OFFSET 0 -#define SM_OSCSEL_SIZE 1 -#define SM_PLLSEL_OFFSET 1 -#define SM_PLLSEL_SIZE 1 -#define SM_CEN_OFFSET 2 -#define SM_CEN_SIZE 1 -#define SM_CPC_OFFSET 3 -#define SM_CPC_SIZE 1 -#define SM_DIVEN_OFFSET 4 -#define SM_DIVEN_SIZE 1 -#define SM_DIV_OFFSET 8 -#define SM_DIV_SIZE 8 - -/* Bitfields in RTC_CTRL */ -#define SM_PCLR_OFFSET 1 -#define SM_PCLR_SIZE 1 -#define SM_TOPEN_OFFSET 2 -#define SM_TOPEN_SIZE 1 -#define SM_CLKEN_OFFSET 3 -#define SM_CLKEN_SIZE 1 -#define SM_PSEL_OFFSET 8 -#define SM_PSEL_SIZE 16 - -/* Bitfields in RTC_VAL */ -#define SM_RTC_VAL_VAL_OFFSET 0 -#define SM_RTC_VAL_VAL_SIZE 31 - -/* Bitfields in RTC_TOP */ -#define SM_RTC_TOP_VAL_OFFSET 0 -#define SM_RTC_TOP_VAL_SIZE 32 - -/* Bitfields in RTC_ICR */ -#define SM_TOPI_OFFSET 0 -#define SM_TOPI_SIZE 1 - -/* Bitfields in WDT_CTRL */ -#define SM_KEY_OFFSET 24 -#define SM_KEY_SIZE 8 - -/* Bitfields in RC_RCAUSE */ -#define SM_POR_OFFSET 0 -#define SM_POR_SIZE 1 -#define SM_BOD_OFFSET 1 -#define SM_BOD_SIZE 1 -#define SM_EXT_OFFSET 2 -#define SM_EXT_SIZE 1 -#define SM_WDT_OFFSET 3 -#define SM_WDT_SIZE 1 -#define SM_NTAE_OFFSET 4 -#define SM_NTAE_SIZE 1 -#define SM_SERP_OFFSET 5 -#define SM_SERP_SIZE 1 - -/* Bitfields in EIM_EDGE */ -#define SM_INT0_OFFSET 0 -#define SM_INT0_SIZE 1 -#define SM_INT1_OFFSET 1 -#define SM_INT1_SIZE 1 -#define SM_INT2_OFFSET 2 -#define SM_INT2_SIZE 1 -#define SM_INT3_OFFSET 3 -#define SM_INT3_SIZE 1 - -/* Bitfields in EIM_LEVEL */ - -/* Bitfields in EIM_TEST */ -#define SM_TESTEN_OFFSET 31 -#define SM_TESTEN_SIZE 1 - -/* Bitfields in EIM_NMIC */ -#define SM_EN_OFFSET 0 -#define SM_EN_SIZE 1 - -/* Bit manipulation macros */ -#define SM_BIT(name) \ - (1 << SM_##name##_OFFSET) -#define SM_BF(name,value) \ - (((value) & ((1 << SM_##name##_SIZE) - 1)) \ - << SM_##name##_OFFSET) -#define SM_BFEXT(name,value) \ - (((value) >> SM_##name##_OFFSET) \ - & ((1 << SM_##name##_SIZE) - 1)) -#define SM_BFINS(name,value,old) \ - (((old) & ~(((1 << SM_##name##_SIZE) - 1) \ - << SM_##name##_OFFSET)) \ - | SM_BF(name,value)) - -/* Register access macros */ -#define sm_readl(reg) \ - readl((void *)ATMEL_BASE_SM + SM_##reg) -#define sm_writel(reg,value) \ - writel((value), (void *)ATMEL_BASE_SM + SM_##reg) - -#endif /* __CPU_AT32AP_SM_H__ */ diff --git a/arch/avr32/cpu/cache.c b/arch/avr32/cpu/cache.c deleted file mode 100644 index b3ffc3348b..0000000000 --- a/arch/avr32/cpu/cache.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#include <asm/arch/cacheflush.h> - -void dcache_clean_range(volatile void *start, size_t size) -{ - unsigned long v, begin, end, linesz; - - linesz = CONFIG_SYS_DCACHE_LINESZ; - - /* You asked for it, you got it */ - begin = (unsigned long)start & ~(linesz - 1); - end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); - - for (v = begin; v < end; v += linesz) - dcache_clean_line((void *)v); - - sync_write_buffer(); -} - -void invalidate_dcache_range(unsigned long start, unsigned long stop) -{ - unsigned long v, linesz; - - linesz = CONFIG_SYS_DCACHE_LINESZ; - - /* You asked for it, you got it */ - start = start & ~(linesz - 1); - stop = (stop + linesz - 1) & ~(linesz - 1); - - for (v = start; v < stop; v += linesz) - dcache_invalidate_line((void *)v); -} - -void flush_dcache_range(unsigned long start, unsigned long stop) -{ - unsigned long v, linesz; - - linesz = CONFIG_SYS_DCACHE_LINESZ; - - /* You asked for it, you got it */ - start = start & ~(linesz - 1); - stop = (stop + linesz - 1) & ~(linesz - 1); - - for (v = start; v < stop; v += linesz) - dcache_flush_line((void *)v); - - sync_write_buffer(); -} - -void icache_invalidate_range(volatile void *start, size_t size) -{ - unsigned long v, begin, end, linesz; - - linesz = CONFIG_SYS_ICACHE_LINESZ; - - /* You asked for it, you got it */ - begin = (unsigned long)start & ~(linesz - 1); - end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); - - for (v = begin; v < end; v += linesz) - icache_invalidate_line((void *)v); -} - -/* - * This is called after loading something into memory. We need to - * make sure that everything that was loaded is actually written to - * RAM, and that the icache will look for it. Cleaning the dcache and - * invalidating the icache will do the trick. - */ -void flush_cache (unsigned long start_addr, unsigned long size) -{ - dcache_clean_range((void *)start_addr, size); - icache_invalidate_range((void *)start_addr, size); -} diff --git a/arch/avr32/cpu/config.mk b/arch/avr32/cpu/config.mk deleted file mode 100644 index 3d2d817f8f..0000000000 --- a/arch/avr32/cpu/config.mk +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# -PLATFORM_RELFLAGS += -mcpu=ap7000 diff --git a/arch/avr32/cpu/cpu.c b/arch/avr32/cpu/cpu.c deleted file mode 100644 index cd226a6f71..0000000000 --- a/arch/avr32/cpu/cpu.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> - -#include <asm/io.h> -#include <asm/sections.h> -#include <asm/sysreg.h> - -#include <asm/arch/clk.h> -#include <asm/arch/hardware.h> - -#include "hsmc3.h" - -/* Sanity checks */ -#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \ - || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \ - || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB) -# error Constraint fCPU >= fHSB >= fPB{A,B} violated -#endif -#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1)) -# error Invalid PLL multiplier and/or divider -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int arch_cpu_init(void) -{ - extern void _evba(void); - - gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ; - - /* TODO: Move somewhere else, but needs to be run before we - * increase the clock frequency. */ - hsmc3_writel(MODE0, 0x00031103); - hsmc3_writel(CYCLE0, 0x000c000d); - hsmc3_writel(PULSE0, 0x0b0a0906); - hsmc3_writel(SETUP0, 0x00010002); - - clk_init(); - - /* Update the CPU speed according to the PLL configuration */ - gd->arch.cpu_hz = get_cpu_clk_rate(); - - /* Set up the exception handler table and enable exceptions */ - sysreg_write(EVBA, (unsigned long)&_evba); - asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); - - return 0; -} - -void prepare_to_boot(void) -{ - /* Flush both caches and the write buffer */ - asm volatile("cache %0[4], 010\n\t" - "cache %0[0], 000\n\t" - "sync 0" : : "r"(0) : "memory"); -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - /* This will reset the CPU core, caches, MMU and all internal busses */ - __builtin_mtdr(8, 1 << 13); /* set DC:DBE */ - __builtin_mtdr(8, 1 << 30); /* set DC:RES */ - - /* Flush the pipeline before we declare it a failure */ - asm volatile("sub pc, pc, -4"); - - return -1; -} diff --git a/arch/avr32/cpu/exception.c b/arch/avr32/cpu/exception.c deleted file mode 100644 index 22eab03b12..0000000000 --- a/arch/avr32/cpu/exception.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/sysreg.h> -#include <asm/ptrace.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define STACKSIZE 2048 - -static const char * const cpu_modes[8] = { - "Application", "Supervisor", "Interrupt level 0", "Interrupt level 1", - "Interrupt level 2", "Interrupt level 3", "Exception", "NMI" -}; - -static void dump_mem(const char *str, unsigned long bottom, unsigned long top) -{ - unsigned long p; - int i; - - printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); - - for (p = bottom & ~31; p < top; ) { - printf("%04lx: ", p & 0xffff); - - for (i = 0; i < 8; i++, p += 4) { - unsigned int val; - - if (p < bottom || p >= top) - printf(" "); - else { - val = *(unsigned long *)p; - printf("%08x ", val); - } - } - printf("\n"); - } -} - -void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) -{ - unsigned int mode; - - printf("\n *** Unhandled exception %u at PC=0x%08lx [%08lx]\n", - ecr, regs->pc, regs->pc - gd->reloc_off); - - switch (ecr) { - case ECR_BUS_ERROR_WRITE: - case ECR_BUS_ERROR_READ: - printf("Bus error at address 0x%08lx\n", - sysreg_read(BEAR)); - break; - case ECR_TLB_MULTIPLE: - case ECR_ADDR_ALIGN_X: - case ECR_PROTECTION_X: - case ECR_ADDR_ALIGN_R: - case ECR_ADDR_ALIGN_W: - case ECR_PROTECTION_R: - case ECR_PROTECTION_W: - case ECR_DTLB_MODIFIED: - case ECR_TLB_MISS_X: - case ECR_TLB_MISS_R: - case ECR_TLB_MISS_W: - printf("MMU exception at address 0x%08lx\n", - sysreg_read(TLBEAR)); - break; - } - - printf(" pc: %08lx lr: %08lx sp: %08lx r12: %08lx\n", - regs->pc, regs->lr, regs->sp, regs->r12); - printf(" r11: %08lx r10: %08lx r9: %08lx r8: %08lx\n", - regs->r11, regs->r10, regs->r9, regs->r8); - printf(" r7: %08lx r6: %08lx r5: %08lx r4: %08lx\n", - regs->r7, regs->r6, regs->r5, regs->r4); - printf(" r3: %08lx r2: %08lx r1: %08lx r0: %08lx\n", - regs->r3, regs->r2, regs->r1, regs->r0); - printf("Flags: %c%c%c%c%c\n", - regs->sr & SR_Q ? 'Q' : 'q', - regs->sr & SR_V ? 'V' : 'v', - regs->sr & SR_N ? 'N' : 'n', - regs->sr & SR_Z ? 'Z' : 'z', - regs->sr & SR_C ? 'C' : 'c'); - printf("Mode bits: %c%c%c%c%c%c%c%c%c\n", - regs->sr & SR_H ? 'H' : 'h', - regs->sr & SR_R ? 'R' : 'r', - regs->sr & SR_J ? 'J' : 'j', - regs->sr & SR_EM ? 'E' : 'e', - regs->sr & SR_I3M ? '3' : '.', - regs->sr & SR_I2M ? '2' : '.', - regs->sr & SR_I1M ? '1' : '.', - regs->sr & SR_I0M ? '0' : '.', - regs->sr & SR_GM ? 'G' : 'g'); - mode = (regs->sr >> SYSREG_M0_OFFSET) & 7; - printf("CPU Mode: %s\n", cpu_modes[mode]); - - /* Avoid exception loops */ - if (regs->sp < (gd->start_addr_sp - STACKSIZE) || - regs->sp >= gd->start_addr_sp) - printf("\nStack pointer seems bogus, won't do stack dump\n"); - else - dump_mem("\nStack: ", regs->sp, gd->start_addr_sp); - - panic("Unhandled exception\n"); -} diff --git a/arch/avr32/cpu/hsdramc.c b/arch/avr32/cpu/hsdramc.c deleted file mode 100644 index 7e48172038..0000000000 --- a/arch/avr32/cpu/hsdramc.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> -#include <asm/sdram.h> - -#include <asm/arch/clk.h> -#include <asm/arch/hardware.h> - -#include "hsdramc1.h" - -unsigned long sdram_init(void *sdram_base, const struct sdram_config *config) -{ - unsigned long sdram_size; - uint32_t cfgreg; - unsigned int i; - - cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8) - | HSDRAMC1_BF(NR, config->row_bits - 11) - | HSDRAMC1_BF(NB, config->bank_bits - 1) - | HSDRAMC1_BF(CAS, config->cas) - | HSDRAMC1_BF(TWR, config->twr) - | HSDRAMC1_BF(TRC, config->trc) - | HSDRAMC1_BF(TRP, config->trp) - | HSDRAMC1_BF(TRCD, config->trcd) - | HSDRAMC1_BF(TRAS, config->tras) - | HSDRAMC1_BF(TXSR, config->txsr)); - - if (config->data_bits == SDRAM_DATA_16BIT) - cfgreg |= HSDRAMC1_BIT(DBW); - - hsdramc1_writel(CR, cfgreg); - - /* Send a NOP to turn on the clock (necessary on some chips) */ - hsdramc1_writel(MR, HSDRAMC1_MODE_NOP); - hsdramc1_readl(MR); - writel(0, sdram_base); - - /* - * Initialization sequence for SDRAM, from the data sheet: - * - * 1. A minimum pause of 200 us is provided to precede any - * signal toggle. - */ - udelay(200); - - /* - * 2. A Precharge All command is issued to the SDRAM - */ - hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE); - hsdramc1_readl(MR); - writel(0, sdram_base); - - /* - * 3. Eight auto-refresh (CBR) cycles are provided - */ - hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH); - hsdramc1_readl(MR); - for (i = 0; i < 8; i++) - writel(0, sdram_base); - - /* - * 4. A mode register set (MRS) cycle is issued to program - * SDRAM parameters, in particular CAS latency and burst - * length. - * - * The address will be chosen by the SDRAMC automatically; we - * just have to make sure BA[1:0] are set to 0. - */ - hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE); - hsdramc1_readl(MR); - writel(0, sdram_base); - - /* - * 5. The application must go into Normal Mode, setting Mode - * to 0 in the Mode Register and performing a write access - * at any location in the SDRAM. - */ - hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL); - hsdramc1_readl(MR); - writel(0, sdram_base); - - /* - * 6. Write refresh rate into SDRAMC refresh timer count - * register (refresh rate = timing between refresh cycles). - */ - hsdramc1_writel(TR, config->refresh_period); - - if (config->data_bits == SDRAM_DATA_16BIT) - sdram_size = 1 << (config->row_bits + config->col_bits - + config->bank_bits + 1); - else - sdram_size = 1 << (config->row_bits + config->col_bits - + config->bank_bits + 2); - - return sdram_size; -} diff --git a/arch/avr32/cpu/hsdramc1.h b/arch/avr32/cpu/hsdramc1.h deleted file mode 100644 index e18e074a7a..0000000000 --- a/arch/avr32/cpu/hsdramc1.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Register definitions for SDRAM Controller - */ -#ifndef __ASM_AVR32_HSDRAMC1_H__ -#define __ASM_AVR32_HSDRAMC1_H__ - -/* HSDRAMC1 register offsets */ -#define HSDRAMC1_MR 0x0000 -#define HSDRAMC1_TR 0x0004 -#define HSDRAMC1_CR 0x0008 -#define HSDRAMC1_HSR 0x000c -#define HSDRAMC1_LPR 0x0010 -#define HSDRAMC1_IER 0x0014 -#define HSDRAMC1_IDR 0x0018 -#define HSDRAMC1_IMR 0x001c -#define HSDRAMC1_ISR 0x0020 -#define HSDRAMC1_MDR 0x0024 -#define HSDRAMC1_VERSION 0x00fc - -/* Bitfields in MR */ -#define HSDRAMC1_MODE_OFFSET 0 -#define HSDRAMC1_MODE_SIZE 3 - -/* Bitfields in TR */ -#define HSDRAMC1_COUNT_OFFSET 0 -#define HSDRAMC1_COUNT_SIZE 12 - -/* Bitfields in CR */ -#define HSDRAMC1_NC_OFFSET 0 -#define HSDRAMC1_NC_SIZE 2 -#define HSDRAMC1_NR_OFFSET 2 -#define HSDRAMC1_NR_SIZE 2 -#define HSDRAMC1_NB_OFFSET 4 -#define HSDRAMC1_NB_SIZE 1 -#define HSDRAMC1_CAS_OFFSET 5 -#define HSDRAMC1_CAS_SIZE 2 -#define HSDRAMC1_DBW_OFFSET 7 -#define HSDRAMC1_DBW_SIZE 1 -#define HSDRAMC1_TWR_OFFSET 8 -#define HSDRAMC1_TWR_SIZE 4 -#define HSDRAMC1_TRC_OFFSET 12 -#define HSDRAMC1_TRC_SIZE 4 -#define HSDRAMC1_TRP_OFFSET 16 -#define HSDRAMC1_TRP_SIZE 4 -#define HSDRAMC1_TRCD_OFFSET 20 -#define HSDRAMC1_TRCD_SIZE 4 -#define HSDRAMC1_TRAS_OFFSET 24 -#define HSDRAMC1_TRAS_SIZE 4 -#define HSDRAMC1_TXSR_OFFSET 28 -#define HSDRAMC1_TXSR_SIZE 4 - -/* Bitfields in HSR */ -#define HSDRAMC1_DA_OFFSET 0 -#define HSDRAMC1_DA_SIZE 1 - -/* Bitfields in LPR */ -#define HSDRAMC1_LPCB_OFFSET 0 -#define HSDRAMC1_LPCB_SIZE 2 -#define HSDRAMC1_PASR_OFFSET 4 -#define HSDRAMC1_PASR_SIZE 3 -#define HSDRAMC1_TCSR_OFFSET 8 -#define HSDRAMC1_TCSR_SIZE 2 -#define HSDRAMC1_DS_OFFSET 10 -#define HSDRAMC1_DS_SIZE 2 -#define HSDRAMC1_TIMEOUT_OFFSET 12 -#define HSDRAMC1_TIMEOUT_SIZE 2 - -/* Bitfields in IDR */ -#define HSDRAMC1_RES_OFFSET 0 -#define HSDRAMC1_RES_SIZE 1 - -/* Bitfields in MDR */ -#define HSDRAMC1_MD_OFFSET 0 -#define HSDRAMC1_MD_SIZE 2 - -/* Bitfields in VERSION */ -#define HSDRAMC1_VERSION_OFFSET 0 -#define HSDRAMC1_VERSION_SIZE 12 -#define HSDRAMC1_MFN_OFFSET 16 -#define HSDRAMC1_MFN_SIZE 3 - -/* Constants for MODE */ -#define HSDRAMC1_MODE_NORMAL 0 -#define HSDRAMC1_MODE_NOP 1 -#define HSDRAMC1_MODE_BANKS_PRECHARGE 2 -#define HSDRAMC1_MODE_LOAD_MODE 3 -#define HSDRAMC1_MODE_AUTO_REFRESH 4 -#define HSDRAMC1_MODE_EXT_LOAD_MODE 5 -#define HSDRAMC1_MODE_POWER_DOWN 6 - -/* Constants for NC */ -#define HSDRAMC1_NC_8_COLUMN_BITS 0 -#define HSDRAMC1_NC_9_COLUMN_BITS 1 -#define HSDRAMC1_NC_10_COLUMN_BITS 2 -#define HSDRAMC1_NC_11_COLUMN_BITS 3 - -/* Constants for NR */ -#define HSDRAMC1_NR_11_ROW_BITS 0 -#define HSDRAMC1_NR_12_ROW_BITS 1 -#define HSDRAMC1_NR_13_ROW_BITS 2 - -/* Constants for NB */ -#define HSDRAMC1_NB_TWO_BANKS 0 -#define HSDRAMC1_NB_FOUR_BANKS 1 - -/* Constants for CAS */ -#define HSDRAMC1_CAS_ONE_CYCLE 1 -#define HSDRAMC1_CAS_TWO_CYCLES 2 - -/* Constants for DBW */ -#define HSDRAMC1_DBW_32_BITS 0 -#define HSDRAMC1_DBW_16_BITS 1 - -/* Constants for TIMEOUT */ -#define HSDRAMC1_TIMEOUT_AFTER_END 0 -#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END 1 -#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END 2 - -/* Constants for MD */ -#define HSDRAMC1_MD_SDRAM 0 -#define HSDRAMC1_MD_LOW_POWER_SDRAM 1 - -/* Bit manipulation macros */ -#define HSDRAMC1_BIT(name) \ - (1 << HSDRAMC1_##name##_OFFSET) -#define HSDRAMC1_BF(name,value) \ - (((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) \ - << HSDRAMC1_##name##_OFFSET) -#define HSDRAMC1_BFEXT(name,value) \ - (((value) >> HSDRAMC1_##name##_OFFSET) \ - & ((1 << HSDRAMC1_##name##_SIZE) - 1)) -#define HSDRAMC1_BFINS(name,value,old) \ - (((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1) \ - << HSDRAMC1_##name##_OFFSET)) \ - | HSDRAMC1_BF(name,value)) - -/* Register access macros */ -#define hsdramc1_readl(reg) \ - readl((void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg) -#define hsdramc1_writel(reg,value) \ - writel((value), (void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg) - -#endif /* __ASM_AVR32_HSDRAMC1_H__ */ diff --git a/arch/avr32/cpu/hsmc3.h b/arch/avr32/cpu/hsmc3.h deleted file mode 100644 index ac472952a2..0000000000 --- a/arch/avr32/cpu/hsmc3.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Register definitions for Static Memory Controller - */ -#ifndef __CPU_AT32AP_HSMC3_H__ -#define __CPU_AT32AP_HSMC3_H__ - -/* HSMC3 register offsets */ -#define HSMC3_SETUP0 0x0000 -#define HSMC3_PULSE0 0x0004 -#define HSMC3_CYCLE0 0x0008 -#define HSMC3_MODE0 0x000c -#define HSMC3_SETUP1 0x0010 -#define HSMC3_PULSE1 0x0014 -#define HSMC3_CYCLE1 0x0018 -#define HSMC3_MODE1 0x001c -#define HSMC3_SETUP2 0x0020 -#define HSMC3_PULSE2 0x0024 -#define HSMC3_CYCLE2 0x0028 -#define HSMC3_MODE2 0x002c -#define HSMC3_SETUP3 0x0030 -#define HSMC3_PULSE3 0x0034 -#define HSMC3_CYCLE3 0x0038 -#define HSMC3_MODE3 0x003c -#define HSMC3_SETUP4 0x0040 -#define HSMC3_PULSE4 0x0044 -#define HSMC3_CYCLE4 0x0048 -#define HSMC3_MODE4 0x004c -#define HSMC3_SETUP5 0x0050 -#define HSMC3_PULSE5 0x0054 -#define HSMC3_CYCLE5 0x0058 -#define HSMC3_MODE5 0x005c - -/* Bitfields in SETUP0 */ -#define HSMC3_NWE_SETUP_OFFSET 0 -#define HSMC3_NWE_SETUP_SIZE 6 -#define HSMC3_NCS_WR_SETUP_OFFSET 8 -#define HSMC3_NCS_WR_SETUP_SIZE 6 -#define HSMC3_NRD_SETUP_OFFSET 16 -#define HSMC3_NRD_SETUP_SIZE 6 -#define HSMC3_NCS_RD_SETUP_OFFSET 24 -#define HSMC3_NCS_RD_SETUP_SIZE 6 - -/* Bitfields in PULSE0 */ -#define HSMC3_NWE_PULSE_OFFSET 0 -#define HSMC3_NWE_PULSE_SIZE 7 -#define HSMC3_NCS_WR_PULSE_OFFSET 8 -#define HSMC3_NCS_WR_PULSE_SIZE 7 -#define HSMC3_NRD_PULSE_OFFSET 16 -#define HSMC3_NRD_PULSE_SIZE 7 -#define HSMC3_NCS_RD_PULSE_OFFSET 24 -#define HSMC3_NCS_RD_PULSE_SIZE 7 - -/* Bitfields in CYCLE0 */ -#define HSMC3_NWE_CYCLE_OFFSET 0 -#define HSMC3_NWE_CYCLE_SIZE 9 -#define HSMC3_NRD_CYCLE_OFFSET 16 -#define HSMC3_NRD_CYCLE_SIZE 9 - -/* Bitfields in MODE0 */ -#define HSMC3_READ_MODE_OFFSET 0 -#define HSMC3_READ_MODE_SIZE 1 -#define HSMC3_WRITE_MODE_OFFSET 1 -#define HSMC3_WRITE_MODE_SIZE 1 -#define HSMC3_EXNW_MODE_OFFSET 4 -#define HSMC3_EXNW_MODE_SIZE 2 -#define HSMC3_BAT_OFFSET 8 -#define HSMC3_BAT_SIZE 1 -#define HSMC3_DBW_OFFSET 12 -#define HSMC3_DBW_SIZE 2 -#define HSMC3_TDF_CYCLES_OFFSET 16 -#define HSMC3_TDF_CYCLES_SIZE 4 -#define HSMC3_TDF_MODE_OFFSET 20 -#define HSMC3_TDF_MODE_SIZE 1 -#define HSMC3_PMEN_OFFSET 24 -#define HSMC3_PMEN_SIZE 1 -#define HSMC3_PS_OFFSET 28 -#define HSMC3_PS_SIZE 2 - -/* Bitfields in MODE1 */ -#define HSMC3_PD_OFFSET 28 -#define HSMC3_PD_SIZE 2 - -/* Constants for READ_MODE */ -#define HSMC3_READ_MODE_NCS_CONTROLLED 0 -#define HSMC3_READ_MODE_NRD_CONTROLLED 1 - -/* Constants for WRITE_MODE */ -#define HSMC3_WRITE_MODE_NCS_CONTROLLED 0 -#define HSMC3_WRITE_MODE_NWE_CONTROLLED 1 - -/* Constants for EXNW_MODE */ -#define HSMC3_EXNW_MODE_DISABLED 0 -#define HSMC3_EXNW_MODE_RESERVED 1 -#define HSMC3_EXNW_MODE_FROZEN 2 -#define HSMC3_EXNW_MODE_READY 3 - -/* Constants for BAT */ -#define HSMC3_BAT_BYTE_SELECT 0 -#define HSMC3_BAT_BYTE_WRITE 1 - -/* Constants for DBW */ -#define HSMC3_DBW_8_BITS 0 -#define HSMC3_DBW_16_BITS 1 -#define HSMC3_DBW_32_BITS 2 - -/* Bit manipulation macros */ -#define HSMC3_BIT(name) \ - (1 << HSMC3_##name##_OFFSET) -#define HSMC3_BF(name,value) \ - (((value) & ((1 << HSMC3_##name##_SIZE) - 1)) \ - << HSMC3_##name##_OFFSET) -#define HSMC3_BFEXT(name,value) \ - (((value) >> HSMC3_##name##_OFFSET) \ - & ((1 << HSMC3_##name##_SIZE) - 1)) -#define HSMC3_BFINS(name,value,old)\ - (((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) \ - << HSMC3_##name##_OFFSET)) \ - | HSMC3_BF(name,value)) - -/* Register access macros */ -#define hsmc3_readl(reg) \ - readl((void *)ATMEL_BASE_HSMC + HSMC3_##reg) -#define hsmc3_writel(reg,value) \ - writel((value), (void *)ATMEL_BASE_HSMC + HSMC3_##reg) - -#endif /* __CPU_AT32AP_HSMC3_H__ */ diff --git a/arch/avr32/cpu/interrupts.c b/arch/avr32/cpu/interrupts.c deleted file mode 100644 index de202207ce..0000000000 --- a/arch/avr32/cpu/interrupts.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <div64.h> - -#include <linux/errno.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/sysreg.h> - -#include <asm/arch/hardware.h> - -#define HANDLER_MASK 0x00ffffff -#define INTLEV_SHIFT 30 -#define INTLEV_MASK 0x00000003 - -DECLARE_GLOBAL_DATA_PTR; - -/* Incremented whenever COUNT reaches 0xffffffff by timer_interrupt_handler */ -volatile unsigned long timer_overflow; - -/* - * Instead of dividing by get_tbclk(), multiply by this constant and - * right-shift the result by 32 bits. - */ -static unsigned long tb_factor; - -unsigned long get_tbclk(void) -{ - return gd->arch.cpu_hz; -} - -unsigned long long get_ticks(void) -{ - unsigned long lo, hi_now, hi_prev; - - do { - hi_prev = timer_overflow; - lo = sysreg_read(COUNT); - hi_now = timer_overflow; - } while (hi_prev != hi_now); - - return ((unsigned long long)hi_now << 32) | lo; -} - -unsigned long get_timer(unsigned long base) -{ - u64 now = get_ticks(); - - now *= tb_factor; - return (unsigned long)(now >> 32) - base; -} - -/* - * For short delays only. It will overflow after a few seconds. - */ -void __udelay(unsigned long usec) -{ - unsigned long cycles; - unsigned long base; - unsigned long now; - - base = sysreg_read(COUNT); - cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100; - - do { - now = sysreg_read(COUNT); - } while ((now - base) < cycles); -} - -static int set_interrupt_handler(unsigned int nr, void (*handler)(void), - unsigned int priority) -{ - extern void _evba(void); - unsigned long intpr; - unsigned long handler_addr = (unsigned long)handler; - - handler_addr -= (unsigned long)&_evba; - - if ((handler_addr & HANDLER_MASK) != handler_addr - || (priority & INTLEV_MASK) != priority) - return -EINVAL; - - intpr = (handler_addr & HANDLER_MASK); - intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT; - writel(intpr, (void *)ATMEL_BASE_INTC + 4 * nr); - - return 0; -} - -int timer_init(void) -{ - extern void timer_interrupt_handler(void); - u64 tmp; - - sysreg_write(COUNT, 0); - - tmp = (u64)CONFIG_SYS_HZ << 32; - tmp += gd->arch.cpu_hz / 2; - do_div(tmp, gd->arch.cpu_hz); - tb_factor = (u32)tmp; - - if (set_interrupt_handler(0, &timer_interrupt_handler, 3)) - return -EINVAL; - - /* For all practical purposes, this gives us an overflow interrupt */ - sysreg_write(COMPARE, 0xffffffff); - return 0; -} diff --git a/arch/avr32/cpu/mmc.c b/arch/avr32/cpu/mmc.c deleted file mode 100644 index 26ba3a24e4..0000000000 --- a/arch/avr32/cpu/mmc.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * Copyright (C) 2015 Andreas Bießmann <andreas(a)biessmann.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <atmel_mci.h> -#include <asm/arch/hardware.h> - -/* provide cpu_mmc_init, to overwrite provide board_mmc_init */ -int cpu_mmc_init(bd_t *bd) -{ - /* This calls the atmel_mci_init in gen_atmel_mci.c */ - return atmel_mci_init((void *)ATMEL_BASE_MMCI); -} diff --git a/arch/avr32/cpu/portmux-gpio.c b/arch/avr32/cpu/portmux-gpio.c deleted file mode 100644 index 640852c2c0..0000000000 --- a/arch/avr32/cpu/portmux-gpio.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/gpio.h> - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags) -{ - /* Both pull-up and pull-down set means buskeeper */ - if (flags & PORTMUX_PULL_DOWN) - gpio_writel(port, PDERS, pin_mask); - else - gpio_writel(port, PDERC, pin_mask); - if (flags & PORTMUX_PULL_UP) - gpio_writel(port, PUERS, pin_mask); - else - gpio_writel(port, PUERC, pin_mask); - - /* Select drive strength */ - if (flags & PORTMUX_DRIVE_LOW) - gpio_writel(port, ODCR0S, pin_mask); - else - gpio_writel(port, ODCR0C, pin_mask); - if (flags & PORTMUX_DRIVE_HIGH) - gpio_writel(port, ODCR1S, pin_mask); - else - gpio_writel(port, ODCR1C, pin_mask); - - /* Select function */ - if (func & PORTMUX_FUNC_B) - gpio_writel(port, PMR0S, pin_mask); - else - gpio_writel(port, PMR0C, pin_mask); - if (func & PORTMUX_FUNC_C) - gpio_writel(port, PMR1S, pin_mask); - else - gpio_writel(port, PMR1C, pin_mask); - - /* Disable GPIO (i.e. enable peripheral) */ - gpio_writel(port, GPERC, pin_mask); -} - -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags) -{ - /* Both pull-up and pull-down set means buskeeper */ - if (flags & PORTMUX_PULL_DOWN) - gpio_writel(port, PDERS, pin_mask); - else - gpio_writel(port, PDERC, pin_mask); - if (flags & PORTMUX_PULL_UP) - gpio_writel(port, PUERS, pin_mask); - else - gpio_writel(port, PUERC, pin_mask); - - /* Enable open-drain mode if requested */ - if (flags & PORTMUX_OPEN_DRAIN) - gpio_writel(port, ODMERS, pin_mask); - else - gpio_writel(port, ODMERC, pin_mask); - - /* Select drive strength */ - if (flags & PORTMUX_DRIVE_LOW) - gpio_writel(port, ODCR0S, pin_mask); - else - gpio_writel(port, ODCR0C, pin_mask); - if (flags & PORTMUX_DRIVE_HIGH) - gpio_writel(port, ODCR1S, pin_mask); - else - gpio_writel(port, ODCR1C, pin_mask); - - /* Select direction and initial pin state */ - if (flags & PORTMUX_DIR_OUTPUT) { - if (flags & PORTMUX_INIT_HIGH) - gpio_writel(port, OVRS, pin_mask); - else - gpio_writel(port, OVRC, pin_mask); - gpio_writel(port, ODERS, pin_mask); - } else { - gpio_writel(port, ODERC, pin_mask); - } - - /* Enable GPIO */ - gpio_writel(port, GPERS, pin_mask); -} diff --git a/arch/avr32/cpu/portmux-pio.c b/arch/avr32/cpu/portmux-pio.c deleted file mode 100644 index 8ce51e64df..0000000000 --- a/arch/avr32/cpu/portmux-pio.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/gpio.h> - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags) -{ - if (flags & PORTMUX_PULL_UP) - pio_writel(port, PUER, pin_mask); - else - pio_writel(port, PUDR, pin_mask); - - switch (func) { - case PORTMUX_FUNC_A: - pio_writel(port, ASR, pin_mask); - break; - case PORTMUX_FUNC_B: - pio_writel(port, BSR, pin_mask); - break; - } - - pio_writel(port, PDR, pin_mask); -} - -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags) -{ - if (flags & PORTMUX_PULL_UP) - pio_writel(port, PUER, pin_mask); - else - pio_writel(port, PUDR, pin_mask); - - if (flags & PORTMUX_OPEN_DRAIN) - pio_writel(port, MDER, pin_mask); - else - pio_writel(port, MDDR, pin_mask); - - if (flags & PORTMUX_DIR_OUTPUT) { - if (flags & PORTMUX_INIT_HIGH) - pio_writel(port, SODR, pin_mask); - else - pio_writel(port, CODR, pin_mask); - pio_writel(port, OER, pin_mask); - } else { - pio_writel(port, ODR, pin_mask); - } - - pio_writel(port, PER, pin_mask); -} - -void pio_set_output_value(unsigned int pin, int value) -{ - void *port = pio_pin_to_port(pin); - - if (!port) - panic("Invalid GPIO pin %u\n", pin); - - __pio_set_output_value(port, pin & 0x1f, value); -} - -int pio_get_input_value(unsigned int pin) -{ - void *port = pio_pin_to_port(pin); - - if (!port) - panic("Invalid GPIO pin %u\n", pin); - - return __pio_get_input_value(port, pin & 0x1f); -} diff --git a/arch/avr32/cpu/start.S b/arch/avr32/cpu/start.S deleted file mode 100644 index 14a0269a54..0000000000 --- a/arch/avr32/cpu/start.S +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (C) 2005-2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <asm-offsets.h> -#include <config.h> -#include <asm/ptrace.h> -#include <asm/sysreg.h> - -#define SYSREG_MMUCR_I_OFFSET 2 -#define SYSREG_MMUCR_S_OFFSET 4 - -#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0)) -/* due to errata (unreliable branch folding) clear FE bit explicitly */ -#define CPUCR_INIT ((SYSREG_BIT(BI) | SYSREG_BIT(BE) \ - | SYSREG_BIT(RE) | SYSREG_BIT(IBE) \ - | SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE)) - - /* - * To save some space, we use the same entry point for - * exceptions and reset. This avoids lots of alignment padding - * since the reset vector is always suitably aligned. - */ - .section .exception.text, "ax", @progbits - .global _start - .global _evba - .type _start, @function - .type _evba, @function -_start: - .size _start, 0 -_evba: - .org 0x00 - rjmp unknown_exception /* Unrecoverable exception */ - .org 0x04 - rjmp unknown_exception /* TLB multiple hit */ - .org 0x08 - rjmp unknown_exception /* Bus error data fetch */ - .org 0x0c - rjmp unknown_exception /* Bus error instruction fetch */ - .org 0x10 - rjmp unknown_exception /* NMI */ - .org 0x14 - rjmp unknown_exception /* Instruction address */ - .org 0x18 - rjmp unknown_exception /* ITLB protection */ - .org 0x1c - rjmp unknown_exception /* Breakpoint */ - .org 0x20 - rjmp unknown_exception /* Illegal opcode */ - .org 0x24 - rjmp unknown_exception /* Unimplemented instruction */ - .org 0x28 - rjmp unknown_exception /* Privilege violation */ - .org 0x2c - rjmp unknown_exception /* Floating-point */ - .org 0x30 - rjmp unknown_exception /* Coprocessor absent */ - .org 0x34 - rjmp unknown_exception /* Data Address (read) */ - .org 0x38 - rjmp unknown_exception /* Data Address (write) */ - .org 0x3c - rjmp unknown_exception /* DTLB Protection (read) */ - .org 0x40 - rjmp unknown_exception /* DTLB Protection (write) */ - .org 0x44 - rjmp unknown_exception /* DTLB Modified */ - - .org 0x50 /* ITLB Miss */ - pushm r8-r12,lr - rjmp 1f - .org 0x60 /* DTLB Miss (read) */ - pushm r8-r12,lr - rjmp 1f - .org 0x70 /* DTLB Miss (write) */ - pushm r8-r12,lr -1: mov r12, sp - rcall mmu_handle_tlb_miss - popm r8-r12,lr - brne unknown_exception - rete - - .size _evba, . - _evba - - .align 2 - .type unknown_exception, @function -unknown_exception: - /* Figure out whether we're handling an exception (Exception - * mode) or just booting (Supervisor mode). */ - csrfcz SYSREG_M1_OFFSET - brcc at32ap_cpu_bootstrap - - /* This is an exception. Complain. */ - pushm r0-r12 - sub r8, sp, REG_R12 - REG_R0 - 4 - mov r9, lr - mfsr r10, SYSREG_RAR_EX - mfsr r11, SYSREG_RSR_EX - pushm r8-r11 - mfsr r12, SYSREG_ECR - mov r11, sp - rcall do_unknown_exception -1: rjmp 1b - - /* The COUNT/COMPARE timer interrupt handler */ - .global timer_interrupt_handler - .type timer_interrupt_handler,@function - .align 2 -timer_interrupt_handler: - /* - * Increment timer_overflow and re-write COMPARE with 0xffffffff. - * - * We're running at interrupt level 3, so we don't need to save - * r8-r12 or lr to the stack. - */ - lda.w r8, timer_overflow - ld.w r9, r8[0] - mov r10, -1 - mtsr SYSREG_COMPARE, r10 - sub r9, -1 - st.w r8[0], r9 - rete - - /* - * CPU bootstrap after reset is handled here. SoC code may - * override this in case they need to initialize oscillators, - * etc. - */ - .section .text.at32ap_cpu_bootstrap, "ax", @progbits - .global at32ap_cpu_bootstrap - .weak at32ap_cpu_bootstrap - .type at32ap_cpu_bootstrap, @function - .align 2 -at32ap_cpu_bootstrap: - /* Reset the Status Register */ - mov r0, lo(SR_INIT) - orh r0, hi(SR_INIT) - mtsr SYSREG_SR, r0 - - /* Reset CPUCR and invalidate the BTB */ - mov r2, CPUCR_INIT - mtsr SYSREG_CPUCR, r2 - - /* Flush the caches */ - mov r1, 0 - cache r1[4], 8 - cache r1[0], 0 - sync 0 - - /* Reset the MMU to default settings */ - mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I) - mtsr SYSREG_MMUCR, r0 - - /* Internal RAM should not need any initialization. We might - have to initialize external RAM here if the part doesn't - have internal RAM (or we may use the data cache) */ - - /* Jump to cacheable segment */ - lddpc pc, 1f - - .align 2 -1: .long at32ap_low_level_init - .size _start, . - _start - - /* Common CPU bootstrap code after oscillator/cache/etc. init */ - .section .text.avr32ap_low_level_init, "ax", @progbits - .global at32ap_low_level_init - .type at32ap_low_level_init, @function - .align 2 -at32ap_low_level_init: - lddpc sp, sp_init - - /* Initialize the GOT pointer */ - lddpc r6, got_init -3: rsub r6, pc - - /* Let's go */ - rjmp board_init_f - - .align 2 - .type sp_init,@object -sp_init: - .long CONFIG_SYS_INIT_SP_ADDR -got_init: - .long 3b - _GLOBAL_OFFSET_TABLE_ - - /* - * void relocate_code(new_sp, new_gd, monitor_addr) - * - * Relocate the u-boot image into RAM and continue from there. - * Does not return. - */ - .section .text.relocate_code,"ax",@progbits - .global relocate_code - .type relocate_code,@function -relocate_code: - mov sp, r12 /* use new stack */ - mov r12, r11 /* save new_gd */ - mov r11, r10 /* save destination address */ - - /* copy .text section and flush the cache along the way */ - lda.w r8, _text - lda.w r9, _etext - sub lr, r10, r8 /* relocation offset */ - -1: ldm r8++, r0-r3 - stm r10, r0-r3 - sub r10, -16 - ldm r8++, r0-r3 - stm r10, r0-r3 - sub r10, -16 - cp.w r8, r9 - cache r10[-4], 0x0d /* dcache clean/invalidate */ - cache r10[-4], 0x01 /* icache invalidate */ - brlt 1b - - /* flush write buffer */ - sync 0 - - /* copy data sections */ - lda.w r9, _edata -1: ld.d r0, r8++ - st.d r10++, r0 - cp.w r8, r9 - brlt 1b - - /* zero out .bss */ - mov r0, 0 - mov r1, 0 - lda.w r9, __bss_end - sub r9, r8 -1: st.d r10++, r0 - sub r9, 8 - brgt 1b - - /* jump to RAM */ - sub r0, pc, . - in_ram - add pc, r0, lr - - .align 2 -in_ram: - /* find the new GOT and relocate it */ - lddpc r6, got_init_reloc -3: rsub r6, pc - mov r8, r6 - lda.w r9, _egot - lda.w r10, _got - sub r9, r10 -1: ld.w r0, r8[0] - add r0, lr - st.w r8++, r0 - sub r9, 4 - brgt 1b - - /* Move the exception handlers */ - mfsr r2, SYSREG_EVBA - add r2, lr - mtsr SYSREG_EVBA, r2 - - /* Do the rest of the initialization sequence */ - call board_init_r - - .align 2 -got_init_reloc: - .long 3b - _GLOBAL_OFFSET_TABLE_ - - .size relocate_code, . - relocate_code diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds deleted file mode 100644 index b0180e3534..0000000000 --- a/arch/avr32/cpu/u-boot.lds +++ /dev/null @@ -1,58 +0,0 @@ -/* -*- Fundamental -*- - * - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") -OUTPUT_ARCH(avr32) -ENTRY(_start) - -SECTIONS -{ - . = 0; - _text = .; - .text : { - *(.exception.text) - *(.text) - *(.text.*) - } - _etext = .; - - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - . = ALIGN(8); - _data = .; - .data : { - *(.data) - *(.data.*) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - _got = .; - .got : { - *(.got) - } - _egot = .; - - . = ALIGN(8); - _edata = .; - - .bss (NOLOAD) : { - __bss_start = .; - *(.bss) - *(.bss.*) - } - . = ALIGN(8); - __bss_end = .; - __init_end = .; -} diff --git a/arch/avr32/include/asm/arch-at32ap700x/addrspace.h b/arch/avr32/include/asm/arch-at32ap700x/addrspace.h deleted file mode 100644 index 7b25e2efe6..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/addrspace.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ADDRSPACE_H -#define __ASM_AVR32_ADDRSPACE_H - -#include <asm/types.h> - -/* Memory segments when segmentation is enabled */ -#define P0SEG 0x00000000 -#define P1SEG 0x80000000 -#define P2SEG 0xa0000000 -#define P3SEG 0xc0000000 -#define P4SEG 0xe0000000 - -/* Returns the privileged segment base of a given address */ -#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) - -/* Returns the physical address of a PnSEG (n=1,2) address */ -#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) - -/* - * Map an address to a certain privileged segment - */ -#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) -#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) -#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) -#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) - -/* virt_to_phys will only work when address is in P1 or P2 */ -static inline unsigned long virt_to_phys(volatile void *address) -{ - return PHYSADDR(address); -} - -static inline void * phys_to_virt(unsigned long address) -{ - return (void *)P1SEGADDR(address); -} - -#define cached(addr) ((void *)P1SEGADDR(addr)) -#define uncached(addr) ((void *)P2SEGADDR(addr)) - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - * - * This implementation works for memory below 512MiB (flash, etc.) as - * well as above 3.5GiB (internal peripherals.) - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (1 << 7) -#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) -#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0)) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -#endif /* __ASM_AVR32_ADDRSPACE_H */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h b/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h deleted file mode 100644 index e08cd9de6d..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_CACHEFLUSH_H -#define __ASM_AVR32_CACHEFLUSH_H - -/* - * Invalidate any cacheline containing virtual address vaddr without - * writing anything back to memory. - * - * Note that this function may corrupt unrelated data structures when - * applied on buffers that are not cacheline aligned in both ends. - */ -static inline void dcache_invalidate_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory"); -} - -/* - * Make sure any cacheline containing virtual address vaddr is written - * to memory. - */ -static inline void dcache_clean_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory"); -} - -/* - * Make sure any cacheline containing virtual address vaddr is written - * to memory and then invalidate it. - */ -static inline void dcache_flush_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory"); -} - -/* - * Invalidate any instruction cacheline containing virtual address - * vaddr. - */ -static inline void icache_invalidate_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory"); -} - -/* - * Applies the above functions on all lines that are touched by the - * specified virtual address range. - */ -void dcache_clean_range(volatile void *start, size_t len); -void icache_invalidate_range(volatile void *start, size_t len); - -static inline void dcache_flush_unlocked(void) -{ - asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory"); -} - -/* - * Make sure any pending writes are completed before continuing. - */ -#define sync_write_buffer() asm volatile("sync 0" : : : "memory") - -#endif /* __ASM_AVR32_CACHEFLUSH_H */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/chip-features.h b/arch/avr32/include/asm/arch-at32ap700x/chip-features.h deleted file mode 100644 index 822286df5f..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/chip-features.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2007 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__ -#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__ - -/* Currently, all the AP700x chips have these */ -#define AT32AP700x_CHIP_HAS_USART -#define AT32AP700x_CHIP_HAS_MMCI -#define AT32AP700x_CHIP_HAS_SPI - -/* Only AP7000 has ethernet interface */ -#ifdef CONFIG_AT32AP7000 -#define AT32AP700x_CHIP_HAS_MACB -#endif - -/* AP7000 and AP7002 have LCD controller, but AP7001 does not */ -#if defined(CONFIG_AT32AP7000) || defined(CONFIG_AT32AP7002) -#define AT32AP700x_CHIP_HAS_LCDC -#endif - -#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/clk.h b/arch/avr32/include/asm/arch-at32ap700x/clk.h deleted file mode 100644 index 0721899fde..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/clk.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_CLK_H__ -#define __ASM_AVR32_ARCH_CLK_H__ - -#include <asm/arch/chip-features.h> -#include <asm/arch/portmux.h> - -#ifdef CONFIG_PLL -#define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \ - * CONFIG_SYS_PLL0_MUL) -#define MAIN_CLK_RATE PLL0_RATE -#else -#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ) -#endif - -static inline unsigned long get_cpu_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU; -} -static inline unsigned long get_hsb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB; -} -static inline unsigned long get_pba_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA; -} -static inline unsigned long get_pbb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB; -} - -/* Accessors for specific devices. More will be added as needed. */ -static inline unsigned long get_sdram_clk_rate(void) -{ - return get_hsb_clk_rate(); -} -#ifdef AT32AP700x_CHIP_HAS_USART -static inline unsigned long get_usart_clk_rate(unsigned int dev_id) -{ - return get_pba_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_MACB -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return get_pbb_clk_rate(); -} -static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) -{ - return get_hsb_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_MMCI -static inline unsigned long get_mci_clk_rate(void) -{ - return get_pbb_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_SPI -static inline unsigned long get_spi_clk_rate(unsigned int dev_id) -{ - return get_pba_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_LCDC -static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) -{ - return get_hsb_clk_rate(); -} -#endif - -extern void clk_init(void); - -/* Board code may need the SDRAM base clock as a compile-time constant */ -#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB) - -/* Generic clock control */ -enum gclk_parent { - GCLK_PARENT_OSC0 = 0, - GCLK_PARENT_OSC1 = 1, - GCLK_PARENT_PLL0 = 2, - GCLK_PARENT_PLL1 = 3, -}; - -/* Some generic clocks have specific roles */ -#define GCLK_DAC_SAMPLE_CLK 6 -#define GCLK_LCDC_PIXCLK 7 - -extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, - unsigned long rate, unsigned long parent_rate); - -/** - * gclk_set_rate - configure and enable a generic clock - * @id: Which GCLK[id] to enable - * @parent: Parent clock feeding the GCLK - * @rate: Target rate of the GCLK in Hz - * - * Returns the actual GCLK rate in Hz, after rounding to the nearest - * supported rate. - * - * All three parameters are usually constant, hence the inline. - */ -static inline unsigned long gclk_set_rate(unsigned int id, - enum gclk_parent parent, unsigned long rate) -{ - unsigned long parent_rate; - - if (id > 7) - return 0; - - switch (parent) { - case GCLK_PARENT_OSC0: - parent_rate = CONFIG_SYS_OSC0_HZ; - break; -#ifdef CONFIG_SYS_OSC1_HZ - case GCLK_PARENT_OSC1: - parent_rate = CONFIG_SYS_OSC1_HZ; - break; -#endif -#ifdef PLL0_RATE - case GCLK_PARENT_PLL0: - parent_rate = PLL0_RATE; - break; -#endif -#ifdef PLL1_RATE - case GCLK_PARENT_PLL1: - parent_rate = PLL1_RATE; - break; -#endif - default: - parent_rate = 0; - break; - } - - return __gclk_set_rate(id, parent, rate, parent_rate); -} - -/** - * gclk_enable_output - enable output on a GCLK pin - * @id: Which GCLK[id] pin to enable - * @drive_strength: Drive strength of external GCLK pin, if applicable - */ -static inline void gclk_enable_output(unsigned int id, - unsigned long drive_strength) -{ - switch (id) { - case 0: - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, - PORTMUX_FUNC_A, drive_strength); - break; - case 1: - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31, - PORTMUX_FUNC_A, drive_strength); - break; - case 2: - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19, - PORTMUX_FUNC_A, drive_strength); - break; - case 3: - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29, - PORTMUX_FUNC_A, drive_strength); - break; - case 4: - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30, - PORTMUX_FUNC_A, drive_strength); - break; - } -} - -#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/gpio.h b/arch/avr32/include/asm/arch-at32ap700x/gpio.h deleted file mode 100644 index b5808c5d45..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/gpio.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_GPIO_H__ -#define __ASM_AVR32_ARCH_GPIO_H__ - -#include <asm/arch/chip-features.h> -#include <asm/arch/hardware.h> - -#define NR_GPIO_CONTROLLERS 5 - -/* - * Pin numbers identifying specific GPIO pins on the chip. - */ -#define GPIO_PIOA_BASE (0) -#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) -#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) -#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) -#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) -#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x)) -#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x)) -#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x)) -#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x)) -#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x)) - -static inline void *pio_pin_to_port(unsigned int pin) -{ - switch (pin >> 5) { - case 0: - return (void *)ATMEL_BASE_PIOA; - case 1: - return (void *)ATMEL_BASE_PIOB; - case 2: - return (void *)ATMEL_BASE_PIOC; - case 3: - return (void *)ATMEL_BASE_PIOD; - case 4: - return (void *)ATMEL_BASE_PIOE; - default: - return NULL; - } -} - -#include <asm/arch-common/portmux-pio.h> - -#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/hardware.h b/arch/avr32/include/asm/arch-at32ap700x/hardware.h deleted file mode 100644 index 58ae965259..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/hardware.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __AT32AP7000_HARDWARE_H__ -#define __AT32AP7000_HARDWARE_H__ - -/* Internal and external memories */ -#define EBI_SRAM_CS0_BASE 0x00000000 -#define EBI_SRAM_CS0_SIZE 0x04000000 -#define EBI_SRAM_CS4_BASE 0x04000000 -#define EBI_SRAM_CS4_SIZE 0x04000000 -#define EBI_SRAM_CS2_BASE 0x08000000 -#define EBI_SRAM_CS2_SIZE 0x04000000 -#define EBI_SRAM_CS3_BASE 0x0c000000 -#define EBI_SRAM_CS3_SIZE 0x04000000 -#define EBI_SRAM_CS1_BASE 0x10000000 -#define EBI_SRAM_CS1_SIZE 0x10000000 -#define EBI_SRAM_CS5_BASE 0x20000000 -#define EBI_SRAM_CS5_SIZE 0x04000000 - -#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE -#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE - -#define INTERNAL_SRAM_BASE 0x24000000 -#define INTERNAL_SRAM_SIZE 0x00008000 - -/* Devices on the High Speed Bus (HSB) */ -#define LCDC_BASE 0xFF000000 -#define DMAC_BASE 0xFF200000 -#define USB_FIFO 0xFF300000 - -/* Devices on Peripheral Bus A (PBA) */ -#define ATMEL_BASE_SPI0 0xFFE00000 -#define ATMEL_BASE_SPI1 0xFFE00400 -#define ATMEL_BASE_TWI0 0xFFE00800 -#define ATMEL_BASE_USART0 0xFFE00C00 -#define ATMEL_BASE_USART1 0xFFE01000 -#define ATMEL_BASE_USART2 0xFFE01400 -#define ATMEL_BASE_USART3 0xFFE01800 -#define ATMEL_BASE_SSC0 0xFFE01C00 -#define ATMEL_BASE_SSC1 0xFFE02000 -#define ATMEL_BASE_SSC2 0xFFE02400 -#define ATMEL_BASE_PIOA 0xFFE02800 -#define ATMEL_BASE_PIOB 0xFFE02C00 -#define ATMEL_BASE_PIOC 0xFFE03000 -#define ATMEL_BASE_PIOD 0xFFE03400 -#define ATMEL_BASE_PIOE 0xFFE03800 -#define ATMEL_BASE_PSIF 0xFFE03C00 - -/* Devices on Peripheral Bus B (PBB) */ -#define ATMEL_BASE_SM 0xFFF00000 -#define ATMEL_BASE_INTC 0xFFF00400 -#define ATMEL_BASE_HMATRIX 0xFFF00800 -#define ATMEL_BASE_TIMER0 0xFFF00C00 -#define ATMEL_BASE_TIMER1 0xFFF01000 -#define ATMEL_BASE_PWM 0xFFF01400 -#define ATMEL_BASE_MACB0 0xFFF01800 -#define ATMEL_BASE_MACB1 0xFFF01C00 -#define ATMEL_BASE_DAC 0xFFF02000 -#define ATMEL_BASE_MMCI 0xFFF02400 -#define ATMEL_BASE_AUDIOC 0xFFF02800 -#define ATMEL_BASE_HISI 0xFFF02C00 -#define ATMEL_BASE_USB 0xFFF03000 -#define ATMEL_BASE_HSMC 0xFFF03400 -#define ATMEL_BASE_HSDRAMC 0xFFF03800 -#define ATMEL_BASE_ECC 0xFFF03C00 - -#endif /* __AT32AP7000_HARDWARE_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h b/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h deleted file mode 100644 index d2a733fa40..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_HMATRIX_H__ -#define __ASM_AVR32_ARCH_HMATRIX_H__ - -#include <asm/hmatrix-common.h> - -/* Bitfields in SFR4 (EBI) */ -#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET 1 -#define HMATRIX_EBI_SDRAM_ENABLE_SIZE 1 -#define HMATRIX_EBI_NAND_ENABLE_OFFSET 3 -#define HMATRIX_EBI_NAND_ENABLE_SIZE 1 -#define HMATRIX_EBI_CF0_ENABLE_OFFSET 4 -#define HMATRIX_EBI_CF0_ENABLE_SIZE 1 -#define HMATRIX_EBI_CF1_ENABLE_OFFSET 5 -#define HMATRIX_EBI_CF1_ENABLE_SIZE 1 -#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET 8 -#define HMATRIX_EBI_PULLUP_DISABLE_SIZE 1 - -/* HSB masters */ -#define HMATRIX_MASTER_CPU_DCACHE 0 -#define HMATRIX_MASTER_CPU_ICACHE 1 -#define HMATRIX_MASTER_PDC 2 -#define HMATRIX_MASTER_ISI 3 -#define HMATRIX_MASTER_USBA 4 -#define HMATRIX_MASTER_LCDC 5 -#define HMATRIX_MASTER_MACB0 6 -#define HMATRIX_MASTER_MACB1 7 -#define HMATRIX_MASTER_DMACA_M0 8 -#define HMATRIX_MASTER_DMACA_M1 9 - -/* HSB slaves */ -#define HMATRIX_SLAVE_SRAM0 0 -#define HMATRIX_SLAVE_SRAM1 1 -#define HMATRIX_SLAVE_PBA 2 -#define HMATRIX_SLAVE_PBB 3 -#define HMATRIX_SLAVE_EBI 4 -#define HMATRIX_SLAVE_USBA 5 -#define HMATRIX_SLAVE_LCDC 6 -#define HMATRIX_SLAVE_DMACA 7 - -#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/mmu.h b/arch/avr32/include/asm/arch-at32ap700x/mmu.h deleted file mode 100644 index 4736312f5d..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/mmu.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * In order to deal with the hardcoded u-boot requirement that virtual - * addresses are always mapped 1:1 with physical addresses, we implement - * a small virtual memory manager so that we can use the MMU hardware in - * order to get the caching properties right. - * - * A few pages (or possibly just one) are locked in the TLB permanently - * in order to avoid recursive TLB misses, but most pages are faulted in - * on demand. - */ -#ifndef __ASM_ARCH_MMU_H -#define __ASM_ARCH_MMU_H - -#include <asm/sysreg.h> - -#define MMU_PAGE_SHIFT 20 -#define MMU_PAGE_SIZE (1UL << MMU_PAGE_SHIFT) -#define MMU_PAGE_ADDR_MASK (~(MMU_PAGE_SIZE - 1)) - -#define MMU_VMR_CACHE_NONE \ - (SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D)) -#define MMU_VMR_CACHE_WBUF \ - (MMU_VMR_CACHE_NONE | SYSREG_BIT(B)) -#define MMU_VMR_CACHE_WRTHRU \ - (MMU_VMR_CACHE_NONE | SYSREG_BIT(TLBELO_C) | SYSREG_BIT(W)) -#define MMU_VMR_CACHE_WRBACK \ - (MMU_VMR_CACHE_WBUF | SYSREG_BIT(TLBELO_C)) - -/* - * This structure is used in our "page table". Instead of the usual - * x86-inspired radix tree, we let each entry cover an arbitrary-sized - * virtual address range and store them in a binary search tree. This is - * somewhat slower, but should use significantly less RAM, and we - * shouldn't get many TLB misses when using 1 MB pages anyway. - * - * With 1 MB pages, we need 12 bits to store the page number. In - * addition, we stick an Invalid bit in the high bit of virt_pgno (if - * set, it cannot possibly match any faulting page), and all the bits - * that need to be written to TLBELO in phys_pgno. - */ -struct mmu_vm_range { - uint16_t virt_pgno; - uint16_t nr_pages; - uint32_t phys; -}; - -/* - * An array of mmu_vm_range objects describing all pageable addresses. - * The array is sorted by virt_pgno so that the TLB miss exception - * handler can do a binary search to find the correct entry. - */ -extern struct mmu_vm_range mmu_vmr_table[]; - -/* - * Initialize the MMU. This will set up a fixed TLB entry for the static - * u-boot image at dest_addr and enable paging. - */ -void mmu_init_r(unsigned long dest_addr); - -/* - * Handle a TLB miss exception. This function is called directly from - * the exception vector table written in assembly. - */ -int mmu_handle_tlb_miss(void); - -#endif /* __ASM_ARCH_MMU_H */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/portmux.h b/arch/avr32/include/asm/arch-at32ap700x/portmux.h deleted file mode 100644 index 7ae05408c0..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/portmux.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_PORTMUX_H__ -#define __ASM_AVR32_ARCH_PORTMUX_H__ - -#include <asm/arch/gpio.h> - -#define PORTMUX_PORT_A ((void *)ATMEL_BASE_PIOA) -#define PORTMUX_PORT_B ((void *)ATMEL_BASE_PIOB) -#define PORTMUX_PORT_C ((void *)ATMEL_BASE_PIOC) -#define PORTMUX_PORT_D ((void *)ATMEL_BASE_PIOD) -#define PORTMUX_PORT_E ((void *)ATMEL_BASE_PIOE) - -void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, - unsigned long flags, unsigned long drive_strength); - -#define PORTMUX_EBI_CS(x) (1 << (x)) -#define PORTMUX_EBI_NAND (1 << 6) -#define PORTMUX_EBI_CF(x) (1 << ((x) + 7)) -#define PORTMUX_EBI_NWAIT (1 << 9) - -#ifdef AT32AP700x_CHIP_HAS_USART -static inline void portmux_enable_usart0(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9), - PORTMUX_FUNC_B, 0); -} - -static inline void portmux_enable_usart1(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18), - PORTMUX_FUNC_A, 0); -} - -static inline void portmux_enable_usart2(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27), - PORTMUX_FUNC_B, 0); -} - -static inline void portmux_enable_usart3(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18), - PORTMUX_FUNC_B, 0); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_MACB -void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength); -void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength); - -#define PORTMUX_MACB_RMII (0) -#define PORTMUX_MACB_MII (1 << 0) -#define PORTMUX_MACB_SPEED (1 << 1) - -#endif -#ifdef AT32AP700x_CHIP_HAS_MMCI -void portmux_enable_mmci(unsigned int slot, unsigned long flags, - unsigned long drive_strength); - -#define PORTMUX_MMCI_4BIT (1 << 0) -#define PORTMUX_MMCI_8BIT (PORTMUX_MMCI_4BIT | (1 << 1)) -#define PORTMUX_MMCI_EXT_PULLUP (1 << 2) - -#endif -#ifdef AT32AP700x_CHIP_HAS_SPI -void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength); -void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength); -#endif -#ifdef AT32AP700x_CHIP_HAS_LCDC -void portmux_enable_lcdc(int pin_config); -#endif - -#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */ diff --git a/arch/avr32/include/asm/arch-common/portmux-pio.h b/arch/avr32/include/asm/arch-common/portmux-pio.h deleted file mode 100644 index 0d4d6e01e5..0000000000 --- a/arch/avr32/include/asm/arch-common/portmux-pio.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __AVR32_PORTMUX_PIO_H__ -#define __AVR32_PORTMUX_PIO_H__ - -#include <asm/io.h> - -/* PIO register offsets */ -#define PIO_PER 0x0000 -#define PIO_PDR 0x0004 -#define PIO_PSR 0x0008 -#define PIO_OER 0x0010 -#define PIO_ODR 0x0014 -#define PIO_OSR 0x0018 -#define PIO_IFER 0x0020 -#define PIO_IFDR 0x0024 -#define PIO_ISFR 0x0028 -#define PIO_SODR 0x0030 -#define PIO_CODR 0x0034 -#define PIO_ODSR 0x0038 -#define PIO_PDSR 0x003c -#define PIO_IER 0x0040 -#define PIO_IDR 0x0044 -#define PIO_IMR 0x0048 -#define PIO_ISR 0x004c -#define PIO_MDER 0x0050 -#define PIO_MDDR 0x0054 -#define PIO_MDSR 0x0058 -#define PIO_PUDR 0x0060 -#define PIO_PUER 0x0064 -#define PIO_PUSR 0x0068 -#define PIO_ASR 0x0070 -#define PIO_BSR 0x0074 -#define PIO_ABSR 0x0078 -#define PIO_OWER 0x00a0 -#define PIO_OWDR 0x00a4 -#define PIO_OWSR 0x00a8 - -/* Hardware register access */ -#define pio_readl(base, reg) \ - __raw_readl((void *)base + PIO_##reg) -#define pio_writel(base, reg, value) \ - __raw_writel((value), (void *)base + PIO_##reg) - -/* Portmux API starts here. See doc/README.AVR32-port-muxing */ - -enum portmux_function { - PORTMUX_FUNC_A, - PORTMUX_FUNC_B, -}; - -/* Pull-down, buskeeper and drive strength are not supported */ -#define PORTMUX_DIR_INPUT (0 << 0) -#define PORTMUX_DIR_OUTPUT (1 << 0) -#define PORTMUX_INIT_LOW (0 << 1) -#define PORTMUX_INIT_HIGH (1 << 1) -#define PORTMUX_PULL_UP (1 << 2) -#define PORTMUX_PULL_DOWN (0) -#define PORTMUX_BUSKEEPER PORTMUX_PULL_UP -#define PORTMUX_DRIVE_MIN (0) -#define PORTMUX_DRIVE_LOW (0) -#define PORTMUX_DRIVE_HIGH (0) -#define PORTMUX_DRIVE_MAX (0) -#define PORTMUX_OPEN_DRAIN (1 << 3) - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags); -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags); - -/* Internal helper functions */ - -static inline void __pio_set_output_value(void *port, unsigned int pin, - int value) -{ - /* - * value will usually be constant, but it's pretty cheap - * either way. - */ - if (value) - pio_writel(port, SODR, 1 << pin); - else - pio_writel(port, CODR, 1 << pin); -} - -static inline int __pio_get_input_value(void *port, unsigned int pin) -{ - return (pio_readl(port, PDSR) >> pin) & 1; -} - -void pio_set_output_value(unsigned int pin, int value); -int pio_get_input_value(unsigned int pin); - -/* GPIO API starts here */ - -/* - * GCC doesn't realize that the constant case is extremely trivial, - * so we need to help it make the right decision by using - * always_inline. - */ -__attribute__((always_inline)) -static inline void gpio_set_value(unsigned int pin, int value) -{ - if (__builtin_constant_p(pin)) - __pio_set_output_value(pio_pin_to_port(pin), pin & 0x1f, value); - else - pio_set_output_value(pin, value); -} - -__attribute__((always_inline)) -static inline int gpio_get_value(unsigned int pin) -{ - if (__builtin_constant_p(pin)) - return __pio_get_input_value(pio_pin_to_port(pin), pin & 0x1f); - else - return pio_get_input_value(pin); -} - -#endif /* __AVR32_PORTMUX_PIO_H__ */ diff --git a/arch/avr32/include/asm/bitops.h b/arch/avr32/include/asm/bitops.h deleted file mode 100644 index 0d425c20f9..0000000000 --- a/arch/avr32/include/asm/bitops.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_BITOPS_H -#define __ASM_AVR32_BITOPS_H - -#include <asm-generic/bitops/fls.h> -#include <asm-generic/bitops/__fls.h> -#include <asm-generic/bitops/fls64.h> -#include <asm-generic/bitops/__ffs.h> - -#endif /* __ASM_AVR32_BITOPS_H */ diff --git a/arch/avr32/include/asm/byteorder.h b/arch/avr32/include/asm/byteorder.h deleted file mode 100644 index 25e9aff425..0000000000 --- a/arch/avr32/include/asm/byteorder.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_BYTEORDER_H -#define __ASM_AVR32_BYTEORDER_H - -#include <asm/types.h> - -#define __arch__swab32(x) __builtin_bswap_32(x) -#define __arch__swab16(x) __builtin_bswap_16(x) - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#include <linux/byteorder/big_endian.h> - -#endif /* __ASM_AVR32_BYTEORDER_H */ diff --git a/arch/avr32/include/asm/cache.h b/arch/avr32/include/asm/cache.h deleted file mode 100644 index 486284398e..0000000000 --- a/arch/avr32/include/asm/cache.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AVR32_CACHE_H__ -#define __AVR32_CACHE_H__ - -/* - * Since the AVR32 architecture has a queryable cacheline size with a maximum - * value of 256 we set the DMA buffer alignemnt requirement to this maximum - * value. The board config can override this if it knows that the cacheline - * size is a smaller value. AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ - * macro to specify cache line size, so if it is set we use it instead. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#elif defined(CONFIG_SYS_DCACHE_LINESZ) -#define ARCH_DMA_MINALIGN CONFIG_SYS_DCACHE_LINESZ -#else -#define ARCH_DMA_MINALIGN 256 -#endif - -#endif /* __AVR32_CACHE_H__ */ diff --git a/arch/avr32/include/asm/config.h b/arch/avr32/include/asm/config.h deleted file mode 100644 index 529fe227a6..0000000000 --- a/arch/avr32/include/asm/config.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#define CONFIG_NEEDS_MANUAL_RELOC -#define CONFIG_SYS_GENERIC_GLOBAL_DATA - -#endif diff --git a/arch/avr32/include/asm/dma-mapping.h b/arch/avr32/include/asm/dma-mapping.h deleted file mode 100644 index 1cde8275f4..0000000000 --- a/arch/avr32/include/asm/dma-mapping.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_DMA_MAPPING_H -#define __ASM_AVR32_DMA_MAPPING_H - -#include <asm/io.h> -#include <asm/arch/cacheflush.h> - -enum dma_data_direction { - DMA_BIDIRECTIONAL = 0, - DMA_TO_DEVICE = 1, - DMA_FROM_DEVICE = 2, -}; - -static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) -{ - *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); - return (void *)*handle; -} - -static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, - enum dma_data_direction dir) -{ - extern void __bad_dma_data_direction(void); - - switch (dir) { - case DMA_BIDIRECTIONAL: - flush_dcache_range((unsigned long)vaddr, - (unsigned long)vaddr + len); - break; - case DMA_TO_DEVICE: - dcache_clean_range(vaddr, len); - break; - case DMA_FROM_DEVICE: - invalidate_dcache_range((unsigned long)vaddr, - (unsigned long)vaddr + len); - break; - default: - /* This will cause a linker error */ - __bad_dma_data_direction(); - } - - return virt_to_phys(vaddr); -} - -static inline void dma_unmap_single(volatile void *vaddr, size_t len, - unsigned long paddr) -{ - -} - -#endif /* __ASM_AVR32_DMA_MAPPING_H */ diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h deleted file mode 100644 index 60abd00782..0000000000 --- a/arch/avr32/include/asm/global_data.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_GLOBAL_DATA_H__ -#define __ASM_GLOBAL_DATA_H__ - -/* Architecture-specific global data */ -struct arch_global_data { - unsigned long cpu_hz; /* cpu core clock frequency */ -}; - -#include <asm-generic/global_data.h> - -#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5") - -#endif /* __ASM_GLOBAL_DATA_H__ */ diff --git a/arch/avr32/include/asm/hmatrix-common.h b/arch/avr32/include/asm/hmatrix-common.h deleted file mode 100644 index 66ea43a88b..0000000000 --- a/arch/avr32/include/asm/hmatrix-common.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_HMATRIX_COMMON_H__ -#define __ASM_AVR32_HMATRIX_COMMON_H__ - -/* HMATRIX register offsets */ -struct hmatrix_regs { - u32 MCFG[16]; - u32 SCFG[16]; - struct { - u32 A; - u32 B; - } PRS[16]; - u32 MRCR; - u32 __reserved[3]; - u32 SFR[16]; -}; - -/* Bitfields in MCFG */ -#define HMATRIX_ULBT_OFFSET 0 -#define HMATRIX_ULBT_SIZE 3 - -/* Bitfields in SCFG */ -#define HMATRIX_SLOT_CYCLE_OFFSET 0 -#define HMATRIX_SLOT_CYCLE_SIZE 8 -#define HMATRIX_DEFMSTR_TYPE_OFFSET 16 -#define HMATRIX_DEFMSTR_TYPE_SIZE 2 -#define HMATRIX_FIXED_DEFMSTR_OFFSET 18 -#define HMATRIX_FIXED_DEFMSTR_SIZE 4 -#define HMATRIX_ARBT_OFFSET 24 -#define HMATRIX_ARBT_SIZE 1 - -/* Bitfields in PRS.A */ -#define HMATRIX_M0PR_OFFSET 0 -#define HMATRIX_M0PR_SIZE 4 -#define HMATRIX_M1PR_OFFSET 4 -#define HMATRIX_M1PR_SIZE 4 -#define HMATRIX_M2PR_OFFSET 8 -#define HMATRIX_M2PR_SIZE 4 -#define HMATRIX_M3PR_OFFSET 12 -#define HMATRIX_M3PR_SIZE 4 -#define HMATRIX_M4PR_OFFSET 16 -#define HMATRIX_M4PR_SIZE 4 -#define HMATRIX_M5PR_OFFSET 20 -#define HMATRIX_M5PR_SIZE 4 -#define HMATRIX_M6PR_OFFSET 24 -#define HMATRIX_M6PR_SIZE 4 -#define HMATRIX_M7PR_OFFSET 28 -#define HMATRIX_M7PR_SIZE 4 - -/* Bitfields in PRS.B */ -#define HMATRIX_M8PR_OFFSET 0 -#define HMATRIX_M8PR_SIZE 4 -#define HMATRIX_M9PR_OFFSET 4 -#define HMATRIX_M9PR_SIZE 4 -#define HMATRIX_M10PR_OFFSET 8 -#define HMATRIX_M10PR_SIZE 4 -#define HMATRIX_M11PR_OFFSET 12 -#define HMATRIX_M11PR_SIZE 4 -#define HMATRIX_M12PR_OFFSET 16 -#define HMATRIX_M12PR_SIZE 4 -#define HMATRIX_M13PR_OFFSET 20 -#define HMATRIX_M13PR_SIZE 4 -#define HMATRIX_M14PR_OFFSET 24 -#define HMATRIX_M14PR_SIZE 4 -#define HMATRIX_M15PR_OFFSET 28 -#define HMATRIX_M15PR_SIZE 4 - -/* Constants for ULBT */ -#define HMATRIX_ULBT_INFINITE 0 -#define HMATRIX_ULBT_SINGLE 1 -#define HMATRIX_ULBT_FOUR_BEAT 2 -#define HMATRIX_ULBT_EIGHT_BEAT 3 -#define HMATRIX_ULBT_SIXTEEN_BEAT 4 - -/* Constants for DEFMSTR_TYPE */ -#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT 0 -#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT 1 -#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT 2 - -/* Constants for ARBT */ -#define HMATRIX_ARBT_ROUND_ROBIN 0 -#define HMATRIX_ARBT_FIXED_PRIORITY 1 - -/* Bit manipulation macros */ -#define HMATRIX_BIT(name) \ - (1 << HMATRIX_##name##_OFFSET) -#define HMATRIX_BF(name,value) \ - (((value) & ((1 << HMATRIX_##name##_SIZE) - 1)) \ - << HMATRIX_##name##_OFFSET) -#define HMATRIX_BFEXT(name,value) \ - (((value) >> HMATRIX_##name##_OFFSET) \ - & ((1 << HMATRIX_##name##_SIZE) - 1)) -#define HMATRIX_BFINS(name,value,old) \ - (((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1) \ - << HMATRIX_##name##_OFFSET)) \ - | HMATRIX_BF(name,value)) - -/* Register access macros */ -#define __hmatrix_reg(reg) \ - (((volatile struct hmatrix_regs *)ATMEL_BASE_HMATRIX)->reg) -#define hmatrix_read(reg) \ - (__hmatrix_reg(reg)) -#define hmatrix_write(reg, value) \ - do { __hmatrix_reg(reg) = (value); } while (0) - -#define hmatrix_slave_read(slave, reg) \ - hmatrix_read(reg[HMATRIX_SLAVE_##slave]) -#define hmatrix_slave_write(slave, reg, value) \ - hmatrix_write(reg[HMATRIX_SLAVE_##slave], value) - -#endif /* __ASM_AVR32_HMATRIX_COMMON_H__ */ diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h deleted file mode 100644 index c8d6933613..0000000000 --- a/arch/avr32/include/asm/io.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_IO_H -#define __ASM_AVR32_IO_H - -#include <asm/types.h> - -#ifdef __KERNEL__ - -/* - * Generic IO read/write. These perform native-endian accesses. Note - * that some architectures will want to re-define __raw_{read,write}w. - */ -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -/* As long as I/O is only performed in P4 (or possibly P3), we're safe */ -#define writeb(v,a) __raw_writeb(v,a) -#define writew(v,a) __raw_writew(v,a) -#define writel(v,a) __raw_writel(v,a) - -#define readb(a) __raw_readb(a) -#define readw(a) __raw_readw(a) -#define readl(a) __raw_readl(a) - -/* - * Bad read/write accesses... - */ -extern void __readwrite_bug(const char *fn); - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * All I/O is memory mapped, so these macros doesn't make very much sense - */ -#define outb(v,p) __raw_writeb(v, p) -#define outw(v,p) __raw_writew(cpu_to_le16(v),p) -#define outl(v,p) __raw_writel(cpu_to_le32(v),p) - -#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) -#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) -#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) - -#include <asm/arch/addrspace.h> -/* Provides virt_to_phys, phys_to_virt, cached, uncached, map_physmem */ - -#endif /* __KERNEL__ */ - -static inline void sync(void) -{ -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long len) -{ - -} - -#endif /* __ASM_AVR32_IO_H */ diff --git a/arch/avr32/include/asm/linkage.h b/arch/avr32/include/asm/linkage.h deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/arch/avr32/include/asm/posix_types.h b/arch/avr32/include/asm/posix_types.h deleted file mode 100644 index c65f4ecb6b..0000000000 --- a/arch/avr32/include/asm/posix_types.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_POSIX_TYPES_H -#define __ASM_AVR32_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned long __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; -typedef unsigned long __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -typedef unsigned short __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); -} - - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *__p) -{ - unsigned long *__tmp = __p->fds_bits; - int __i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 16: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - __tmp[ 8] = 0; __tmp[ 9] = 0; - __tmp[10] = 0; __tmp[11] = 0; - __tmp[12] = 0; __tmp[13] = 0; - __tmp[14] = 0; __tmp[15] = 0; - return; - - case 8: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - return; - - case 4: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - return; - } - } - __i = __FDSET_LONGS; - while (__i) { - __i--; - *__tmp = 0; - __tmp++; - } -} - -#endif /* defined(__KERNEL__) */ - -#endif /* __ASM_AVR32_POSIX_TYPES_H */ diff --git a/arch/avr32/include/asm/processor.h b/arch/avr32/include/asm/processor.h deleted file mode 100644 index 74d868cdc8..0000000000 --- a/arch/avr32/include/asm/processor.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_PROCESSOR_H -#define __ASM_AVR32_PROCESSOR_H - -#ifndef __ASSEMBLY__ - -#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; }) - -struct avr32_cpuinfo { - unsigned long loops_per_jiffy; -}; - -extern struct avr32_cpuinfo boot_cpu_data; - -#ifdef CONFIG_SMP -extern struct avr32_cpuinfo cpu_data[]; -#define current_cpu_data cpu_data[smp_processor_id()] -#else -#define cpu_data (&boot_cpu_data) -#define current_cpu_data boot_cpu_data -#endif - -/* TODO: Make configurable (2GB will serve as a reasonable default) */ -#define TASK_SIZE 0x80000000 - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) - -#define cpu_relax() barrier() -#define cpu_sync_pipeline() asm volatile("sub pc, -2" : : : "memory") - -/* This struct contains the CPU context as stored by switch_to() */ -struct thread_struct { - unsigned long pc; - unsigned long ksp; /* Kernel stack pointer */ - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; -}; - -#define INIT_THREAD { \ - .ksp = sizeof(init_stack) + (long)&init_stack, \ -} - -/* - * Do necessary setup to start up a newly executed thread. - */ -#define start_thread(regs, new_pc, new_sp) \ - set_fs(USER_DS); \ - regs->sr = 0; /* User mode. */ \ - regs->gr[REG_PC] = new_pc; \ - regs->gr[REG_SP] = new_sp - -struct task_struct; - -/* Free all resources held by a thread */ -extern void release_thread(struct task_struct *); - -/* Create a kernel thread without removing it from tasklists */ -extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while(0) - -/* Return saved PC of a blocked thread */ -#define thread_saved_pc(tsk) (tsk->thread.pc) - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_AVR32_PROCESSOR_H */ diff --git a/arch/avr32/include/asm/ptrace.h b/arch/avr32/include/asm/ptrace.h deleted file mode 100644 index a32969b5a4..0000000000 --- a/arch/avr32/include/asm/ptrace.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_PTRACE_H -#define __ASM_AVR32_PTRACE_H - -/* - * Status Register bits - */ -#define SR_H 0x40000000 -#define SR_R 0x20000000 -#define SR_J 0x10000000 -#define SR_DM 0x08000000 -#define SR_D 0x04000000 -#define MODE_NMI 0x01c00000 -#define MODE_EXCEPTION 0x01800000 -#define MODE_INT3 0x01400000 -#define MODE_INT2 0x01000000 -#define MODE_INT1 0x00c00000 -#define MODE_INT0 0x00800000 -#define MODE_SUPERVISOR 0x00400000 -#define MODE_USER 0x00000000 -#define MODE_MASK 0x01c00000 -#define SR_EM 0x00200000 -#define SR_I3M 0x00100000 -#define SR_I2M 0x00080000 -#define SR_I1M 0x00040000 -#define SR_I0M 0x00020000 -#define SR_GM 0x00010000 - -#define MODE_SHIFT 22 -#define SR_EM_BIT 21 -#define SR_I3M_BIT 20 -#define SR_I2M_BIT 19 -#define SR_I1M_BIT 18 -#define SR_I0M_BIT 17 -#define SR_GM_BIT 16 - -/* The user-visible part */ -#define SR_Q 0x00000010 -#define SR_V 0x00000008 -#define SR_N 0x00000004 -#define SR_Z 0x00000002 -#define SR_C 0x00000001 - -/* - * The order is defined by the stdsp instruction. r0 is stored first, so it - * gets the highest address. - * - * Registers 0-12 are general-purpose registers (r12 is normally used for - * the function return value). - * Register 13 is the stack pointer - * Register 14 is the link register - * Register 15 is the program counter - */ -#define FRAME_SIZE_FULL 72 -#define REG_R12_ORIG 68 -#define REG_R0 64 -#define REG_R1 60 -#define REG_R2 56 -#define REG_R3 52 -#define REG_R4 48 -#define REG_R5 44 -#define REG_R6 40 -#define REG_R7 36 -#define REG_R8 32 -#define REG_R9 28 -#define REG_R10 34 -#define REG_R11 20 -#define REG_R12 16 -#define REG_SP 12 -#define REG_LR 8 - -#define FRAME_SIZE_MIN 8 -#define REG_PC 4 -#define REG_SR 0 - -#ifndef __ASSEMBLY__ -struct pt_regs { - /* These are always saved */ - unsigned long sr; - unsigned long pc; - - /* These are sometimes saved */ - unsigned long lr; - unsigned long sp; - unsigned long r12; - unsigned long r11; - unsigned long r10; - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - - /* Only saved on system call */ - unsigned long r12_orig; -}; - -#ifdef __KERNEL__ -# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) -# define instruction_pointer(regs) ((regs)->pc) -extern void show_regs (struct pt_regs *); - -static __inline__ int valid_user_regs(struct pt_regs *regs) -{ - /* - * Some of the Java bits might be acceptable if/when we - * implement some support for that stuff... - */ - if ((regs->sr & 0xffff0000) == 0) - return 1; - - /* - * Force status register flags to be sane and report this - * illegal behaviour... - */ - regs->sr &= 0x0000ffff; - return 0; -} -#endif - -#endif /* ! __ASSEMBLY__ */ - -#endif /* __ASM_AVR32_PTRACE_H */ diff --git a/arch/avr32/include/asm/sdram.h b/arch/avr32/include/asm/sdram.h deleted file mode 100644 index 83d515bda2..0000000000 --- a/arch/avr32/include/asm/sdram.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_SDRAM_H -#define __ASM_AVR32_SDRAM_H - -struct sdram_config { - /* Number of data bits. */ - enum { - SDRAM_DATA_16BIT = 16, - SDRAM_DATA_32BIT = 32, - } data_bits; - - /* Number of address bits */ - uint8_t row_bits, col_bits, bank_bits; - - /* SDRAM timings in cycles */ - uint8_t cas, twr, trc, trp, trcd, tras, txsr; - - /* SDRAM refresh period in cycles */ - unsigned long refresh_period; -}; - -/* - * Attempt to initialize the SDRAM controller using the specified - * parameters. Return the expected size of the memory area based on - * the number of address and data bits. - * - * The caller should verify that the configuration is correct by - * running a memory test, e.g. get_ram_size(). - */ -extern unsigned long sdram_init(void *sdram_base, - const struct sdram_config *config); - -#endif /* __ASM_AVR32_SDRAM_H */ diff --git a/arch/avr32/include/asm/sections.h b/arch/avr32/include/asm/sections.h deleted file mode 100644 index 6b7804fe02..0000000000 --- a/arch/avr32/include/asm/sections.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_SECTIONS_H -#define __ASM_AVR32_SECTIONS_H - -#include <asm-generic/sections.h> - -/* References to section boundaries */ - -extern char __data_lma[], __edata_lma[]; -extern char __got_start[], __got_lma[], __got_end[]; - -#endif /* __ASM_AVR32_SECTIONS_H */ diff --git a/arch/avr32/include/asm/setup.h b/arch/avr32/include/asm/setup.h deleted file mode 100644 index e05e65ebc5..0000000000 --- a/arch/avr32/include/asm/setup.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * Based on linux/include/asm-arm/setup.h - * Copyright (C) 1997-1999 Russel King - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_SETUP_H__ -#define __ASM_AVR32_SETUP_H__ - -#define COMMAND_LINE_SIZE 256 - -/* Magic number indicating that a tag table is present */ -#define ATAG_MAGIC 0xa2a25441 - -#ifndef __ASSEMBLY__ - -/* - * Generic memory range, used by several tags. - * - * addr is always physical. - * size is measured in bytes. - * next is for use by the OS, e.g. for grouping regions into - * linked lists. - */ -struct tag_mem_range { - u32 addr; - u32 size; - struct tag_mem_range * next; -}; - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 -/* ATAG_MEM uses tag_mem_range */ - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410003 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* Ramdisk image (may be compressed) */ -#define ATAG_RDIMG 0x54410004 -/* ATAG_RDIMG uses tag_mem_range */ - -/* Information about various clocks present in the system */ -#define ATAG_CLOCK 0x54410005 - -struct tag_clock { - u32 clock_id; /* Which clock are we talking about? */ - u32 clock_flags; /* Special features */ - u64 clock_hz; /* Clock speed in Hz */ -}; - -/* The clock types we know about */ -#define ACLOCK_BOOTCPU 0 /* The CPU we're booting from */ -#define ACLOCK_HSB 1 /* Deprecated */ - -/* Memory reserved for the system (e.g. the bootloader) */ -#define ATAG_RSVD_MEM 0x54410006 -/* ATAG_RSVD_MEM uses tag_mem_range */ - -/* Ethernet information */ - -#define ATAG_ETHERNET 0x54410007 - -struct tag_ethernet { - u8 mac_index; - u8 mii_phy_addr; - u8 hw_address[6]; -}; - -#define AETH_INVALID_PHY 0xff - -/* board information information */ -#define ATAG_BOARDINFO 0x54410008 - -struct tag_boardinfo { - u32 board_number; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem_range mem_range; - struct tag_cmdline cmdline; - struct tag_clock clock; - struct tag_ethernet ethernet; - struct tag_boardinfo boardinfo; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(struct tag *); -}; - -#define __tag __attribute_used__ __attribute__((__section__(".taglist"))) -#define __tagtable(tag, fn) \ - static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -#endif /* !__ASSEMBLY__ */ - -#endif /* __ASM_AVR32_SETUP_H__ */ diff --git a/arch/avr32/include/asm/string.h b/arch/avr32/include/asm/string.h deleted file mode 100644 index dba0219fb3..0000000000 --- a/arch/avr32/include/asm/string.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_STRING_H -#define __ASM_AVR32_STRING_H - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *s, int c, __kernel_size_t n); - -#endif /* __ASM_AVR32_STRING_H */ diff --git a/arch/avr32/include/asm/sysreg.h b/arch/avr32/include/asm/sysreg.h deleted file mode 100644 index 4f6970448b..0000000000 --- a/arch/avr32/include/asm/sysreg.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * System registers for AVR32 - */ -#ifndef __ASM_AVR32_SYSREG_H__ -#define __ASM_AVR32_SYSREG_H__ - -/* system register offsets */ -#define SYSREG_SR 0x0000 -#define SYSREG_EVBA 0x0004 -#define SYSREG_ACBA 0x0008 -#define SYSREG_CPUCR 0x000c -#define SYSREG_ECR 0x0010 -#define SYSREG_RSR_SUP 0x0014 -#define SYSREG_RSR_INT0 0x0018 -#define SYSREG_RSR_INT1 0x001c -#define SYSREG_RSR_INT2 0x0020 -#define SYSREG_RSR_INT3 0x0024 -#define SYSREG_RSR_EX 0x0028 -#define SYSREG_RSR_NMI 0x002c -#define SYSREG_RSR_DBG 0x0030 -#define SYSREG_RAR_SUP 0x0034 -#define SYSREG_RAR_INT0 0x0038 -#define SYSREG_RAR_INT1 0x003c -#define SYSREG_RAR_INT2 0x0040 -#define SYSREG_RAR_INT3 0x0044 -#define SYSREG_RAR_EX 0x0048 -#define SYSREG_RAR_NMI 0x004c -#define SYSREG_RAR_DBG 0x0050 -#define SYSREG_JECR 0x0054 -#define SYSREG_JOSP 0x0058 -#define SYSREG_JAVA_LV0 0x005c -#define SYSREG_JAVA_LV1 0x0060 -#define SYSREG_JAVA_LV2 0x0064 -#define SYSREG_JAVA_LV3 0x0068 -#define SYSREG_JAVA_LV4 0x006c -#define SYSREG_JAVA_LV5 0x0070 -#define SYSREG_JAVA_LV6 0x0074 -#define SYSREG_JAVA_LV7 0x0078 -#define SYSREG_JTBA 0x007c -#define SYSREG_JBCR 0x0080 -#define SYSREG_CONFIG0 0x0100 -#define SYSREG_CONFIG1 0x0104 -#define SYSREG_COUNT 0x0108 -#define SYSREG_COMPARE 0x010c -#define SYSREG_TLBEHI 0x0110 -#define SYSREG_TLBELO 0x0114 -#define SYSREG_PTBR 0x0118 -#define SYSREG_TLBEAR 0x011c -#define SYSREG_MMUCR 0x0120 -#define SYSREG_TLBARLO 0x0124 -#define SYSREG_TLBARHI 0x0128 -#define SYSREG_PCCNT 0x012c -#define SYSREG_PCNT0 0x0130 -#define SYSREG_PCNT1 0x0134 -#define SYSREG_PCCR 0x0138 -#define SYSREG_BEAR 0x013c -#define SYSREG_SABAL 0x0300 -#define SYSREG_SABAH 0x0304 -#define SYSREG_SABD 0x0308 - -/* Bitfields in SR */ -#define SYSREG_SR_C_OFFSET 0 -#define SYSREG_SR_C_SIZE 1 -#define SYSREG_Z_OFFSET 1 -#define SYSREG_Z_SIZE 1 -#define SYSREG_SR_N_OFFSET 2 -#define SYSREG_SR_N_SIZE 1 -#define SYSREG_SR_V_OFFSET 3 -#define SYSREG_SR_V_SIZE 1 -#define SYSREG_Q_OFFSET 4 -#define SYSREG_Q_SIZE 1 -#define SYSREG_L_OFFSET 5 -#define SYSREG_L_SIZE 1 -#define SYSREG_T_OFFSET 14 -#define SYSREG_T_SIZE 1 -#define SYSREG_SR_R_OFFSET 15 -#define SYSREG_SR_R_SIZE 1 -#define SYSREG_GM_OFFSET 16 -#define SYSREG_GM_SIZE 1 -#define SYSREG_I0M_OFFSET 17 -#define SYSREG_I0M_SIZE 1 -#define SYSREG_I1M_OFFSET 18 -#define SYSREG_I1M_SIZE 1 -#define SYSREG_I2M_OFFSET 19 -#define SYSREG_I2M_SIZE 1 -#define SYSREG_I3M_OFFSET 20 -#define SYSREG_I3M_SIZE 1 -#define SYSREG_EM_OFFSET 21 -#define SYSREG_EM_SIZE 1 -#define SYSREG_M0_OFFSET 22 -#define SYSREG_M0_SIZE 1 -#define SYSREG_M1_OFFSET 23 -#define SYSREG_M1_SIZE 1 -#define SYSREG_M2_OFFSET 24 -#define SYSREG_M2_SIZE 1 -#define SYSREG_SR_D_OFFSET 26 -#define SYSREG_SR_D_SIZE 1 -#define SYSREG_DM_OFFSET 27 -#define SYSREG_DM_SIZE 1 -#define SYSREG_SR_J_OFFSET 28 -#define SYSREG_SR_J_SIZE 1 -#define SYSREG_H_OFFSET 29 -#define SYSREG_H_SIZE 1 - -/* Bitfields in CPUCR */ -#define SYSREG_BI_OFFSET 0 -#define SYSREG_BI_SIZE 1 -#define SYSREG_BE_OFFSET 1 -#define SYSREG_BE_SIZE 1 -#define SYSREG_FE_OFFSET 2 -#define SYSREG_FE_SIZE 1 -#define SYSREG_RE_OFFSET 3 -#define SYSREG_RE_SIZE 1 -#define SYSREG_IBE_OFFSET 4 -#define SYSREG_IBE_SIZE 1 -#define SYSREG_IEE_OFFSET 5 -#define SYSREG_IEE_SIZE 1 - -/* Bitfields in ECR */ -#define SYSREG_ECR_OFFSET 0 -#define SYSREG_ECR_SIZE 32 - -/* Bitfields in CONFIG0 */ -#define SYSREG_CONFIG0_R_OFFSET 0 -#define SYSREG_CONFIG0_R_SIZE 1 -#define SYSREG_CONFIG0_D_OFFSET 1 -#define SYSREG_CONFIG0_D_SIZE 1 -#define SYSREG_CONFIG0_S_OFFSET 2 -#define SYSREG_CONFIG0_S_SIZE 1 -#define SYSREG_O_OFFSET 3 -#define SYSREG_O_SIZE 1 -#define SYSREG_P_OFFSET 4 -#define SYSREG_P_SIZE 1 -#define SYSREG_CONFIG0_J_OFFSET 5 -#define SYSREG_CONFIG0_J_SIZE 1 -#define SYSREG_F_OFFSET 6 -#define SYSREG_F_SIZE 1 -#define SYSREG_MMUT_OFFSET 7 -#define SYSREG_MMUT_SIZE 3 -#define SYSREG_AR_OFFSET 10 -#define SYSREG_AR_SIZE 3 -#define SYSREG_AT_OFFSET 13 -#define SYSREG_AT_SIZE 3 -#define SYSREG_PROCESSORREVISION_OFFSET 16 -#define SYSREG_PROCESSORREVISION_SIZE 8 -#define SYSREG_PROCESSORID_OFFSET 24 -#define SYSREG_PROCESSORID_SIZE 8 - -/* Bitfields in CONFIG1 */ -#define SYSREG_DASS_OFFSET 0 -#define SYSREG_DASS_SIZE 3 -#define SYSREG_DLSZ_OFFSET 3 -#define SYSREG_DLSZ_SIZE 3 -#define SYSREG_DSET_OFFSET 6 -#define SYSREG_DSET_SIZE 4 -#define SYSREG_IASS_OFFSET 10 -#define SYSREG_IASS_SIZE 3 -#define SYSREG_ILSZ_OFFSET 13 -#define SYSREG_ILSZ_SIZE 3 -#define SYSREG_ISET_OFFSET 16 -#define SYSREG_ISET_SIZE 4 -#define SYSREG_DMMUSZ_OFFSET 20 -#define SYSREG_DMMUSZ_SIZE 6 -#define SYSREG_IMMUSZ_OFFSET 26 -#define SYSREG_IMMUSZ_SIZE 6 - -/* Bitfields in TLBEHI */ -#define SYSREG_ASID_OFFSET 0 -#define SYSREG_ASID_SIZE 8 -#define SYSREG_TLBEHI_I_OFFSET 8 -#define SYSREG_TLBEHI_I_SIZE 1 -#define SYSREG_TLBEHI_V_OFFSET 9 -#define SYSREG_TLBEHI_V_SIZE 1 -#define SYSREG_VPN_OFFSET 10 -#define SYSREG_VPN_SIZE 22 - -/* Bitfields in TLBELO */ -#define SYSREG_W_OFFSET 0 -#define SYSREG_W_SIZE 1 -#define SYSREG_TLBELO_D_OFFSET 1 -#define SYSREG_TLBELO_D_SIZE 1 -#define SYSREG_SZ_OFFSET 2 -#define SYSREG_SZ_SIZE 2 -#define SYSREG_AP_OFFSET 4 -#define SYSREG_AP_SIZE 3 -#define SYSREG_B_OFFSET 7 -#define SYSREG_B_SIZE 1 -#define SYSREG_G_OFFSET 8 -#define SYSREG_G_SIZE 1 -#define SYSREG_TLBELO_C_OFFSET 9 -#define SYSREG_TLBELO_C_SIZE 1 -#define SYSREG_PFN_OFFSET 10 -#define SYSREG_PFN_SIZE 22 - -/* Bitfields in MMUCR */ -#define SYSREG_E_OFFSET 0 -#define SYSREG_E_SIZE 1 -#define SYSREG_M_OFFSET 1 -#define SYSREG_M_SIZE 1 -#define SYSREG_MMUCR_I_OFFSET 2 -#define SYSREG_MMUCR_I_SIZE 1 -#define SYSREG_MMUCR_N_OFFSET 3 -#define SYSREG_MMUCR_N_SIZE 1 -#define SYSREG_MMUCR_S_OFFSET 4 -#define SYSREG_MMUCR_S_SIZE 1 -#define SYSREG_DLA_OFFSET 8 -#define SYSREG_DLA_SIZE 6 -#define SYSREG_DRP_OFFSET 14 -#define SYSREG_DRP_SIZE 6 -#define SYSREG_ILA_OFFSET 20 -#define SYSREG_ILA_SIZE 6 -#define SYSREG_IRP_OFFSET 26 -#define SYSREG_IRP_SIZE 6 - -/* Bitfields in PCCR */ -#define SYSREG_PCCR_R_OFFSET 1 -#define SYSREG_PCCR_R_SIZE 1 -#define SYSREG_PCCR_C_OFFSET 2 -#define SYSREG_PCCR_C_SIZE 1 -#define SYSREG_PCCR_S_OFFSET 3 -#define SYSREG_PCCR_S_SIZE 1 -#define SYSREG_IEC_OFFSET 4 -#define SYSREG_IEC_SIZE 1 -#define SYSREG_IE0_OFFSET 5 -#define SYSREG_IE0_SIZE 1 -#define SYSREG_IE1_OFFSET 6 -#define SYSREG_IE1_SIZE 1 -#define SYSREG_FC_OFFSET 8 -#define SYSREG_FC_SIZE 1 -#define SYSREG_F0_OFFSET 9 -#define SYSREG_F0_SIZE 1 -#define SYSREG_F1_OFFSET 10 -#define SYSREG_F1_SIZE 1 -#define SYSREG_CONF0_OFFSET 12 -#define SYSREG_CONF0_SIZE 6 -#define SYSREG_CONF1_OFFSET 18 -#define SYSREG_CONF1_SIZE 6 - -/* Constants for ECR */ -#define ECR_UNRECOVERABLE 0 -#define ECR_TLB_MULTIPLE 1 -#define ECR_BUS_ERROR_WRITE 2 -#define ECR_BUS_ERROR_READ 3 -#define ECR_NMI 4 -#define ECR_ADDR_ALIGN_X 5 -#define ECR_PROTECTION_X 6 -#define ECR_DEBUG 7 -#define ECR_ILLEGAL_OPCODE 8 -#define ECR_UNIMPL_INSTRUCTION 9 -#define ECR_PRIVILEGE_VIOLATION 10 -#define ECR_FPE 11 -#define ECR_COPROC_ABSENT 12 -#define ECR_ADDR_ALIGN_R 13 -#define ECR_ADDR_ALIGN_W 14 -#define ECR_PROTECTION_R 15 -#define ECR_PROTECTION_W 16 -#define ECR_DTLB_MODIFIED 17 -#define ECR_TLB_MISS_X 20 -#define ECR_TLB_MISS_R 24 -#define ECR_TLB_MISS_W 28 - -/* Bit manipulation macros */ -#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) -#define SYSREG_BF(name,value) \ - (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \ - << SYSREG_##name##_OFFSET) -#define SYSREG_BFEXT(name,value) \ - (((value) >> SYSREG_##name##_OFFSET) \ - & ((1 << SYSREG_##name##_SIZE) - 1)) -#define SYSREG_BFINS(name,value,old) \ - (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \ - << SYSREG_##name##_OFFSET)) \ - | SYSREG_BF(name,value)) - -/* Register access macros */ -#define sysreg_read(reg) \ - ((unsigned long)__builtin_mfsr(SYSREG_##reg)) -#define sysreg_write(reg, value) \ - __builtin_mtsr(SYSREG_##reg, value) - -#endif /* __ASM_AVR32_SYSREG_H__ */ diff --git a/arch/avr32/include/asm/types.h b/arch/avr32/include/asm/types.h deleted file mode 100644 index 65de677ece..0000000000 --- a/arch/avr32/include/asm/types.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_TYPES_H -#define __ASM_AVR32_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -typedef __signed__ char s8; -typedef unsigned char u8; - -typedef __signed__ short s16; -typedef unsigned short u16; - -typedef __signed__ int s32; -typedef unsigned int u32; - -typedef __signed__ long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#ifdef CONFIG_LBD -typedef u64 sector_t; -#define HAVE_SECTOR_T -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - - -#endif /* __ASM_AVR32_TYPES_H */ diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h deleted file mode 100644 index 7d48e9a46b..0000000000 --- a/arch/avr32/include/asm/u-boot.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_U_BOOT_H__ -#define __ASM_U_BOOT_H__ 1 - -/* Use the generic board which requires a unified bd_info */ -#include <asm-generic/u-boot.h> - -/* For image.h:image_check_target_arch() */ -#define IH_ARCH_DEFAULT IH_ARCH_AVR32 - -int arch_cpu_init(void); -int dram_init(void); - -#endif /* __ASM_U_BOOT_H__ */ diff --git a/arch/avr32/include/asm/unaligned.h b/arch/avr32/include/asm/unaligned.h deleted file mode 100644 index 6cecbbb211..0000000000 --- a/arch/avr32/include/asm/unaligned.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/unaligned.h> diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile deleted file mode 100644 index 8108ae5272..0000000000 --- a/arch/avr32/lib/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# (C) Copyright 2004-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += memset.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o -obj-y += interrupts.o -obj-y += dram_init.o diff --git a/arch/avr32/lib/bootm.c b/arch/avr32/lib/bootm.c deleted file mode 100644 index 342b9e2c1c..0000000000 --- a/arch/avr32/lib/bootm.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <image.h> -#include <u-boot/zlib.h> -#include <asm/byteorder.h> -#include <asm/arch/addrspace.h> -#include <asm/io.h> -#include <asm/setup.h> -#include <asm/arch/clk.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* CPU-specific hook to allow flushing of caches, etc. */ -extern void prepare_to_boot(void); - -static struct tag *setup_start_tag(struct tag *params) -{ - params->hdr.tag = ATAG_CORE; - params->hdr.size = tag_size(tag_core); - - params->u.core.flags = 0; - params->u.core.pagesize = 4096; - params->u.core.rootdev = 0; - - return tag_next(params); -} - -static struct tag *setup_memory_tags(struct tag *params) -{ - bd_t *bd = gd->bd; - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - params->hdr.tag = ATAG_MEM; - params->hdr.size = tag_size(tag_mem_range); - - params->u.mem_range.addr = bd->bi_dram[i].start; - params->u.mem_range.size = bd->bi_dram[i].size; - - params = tag_next(params); - } - - return params; -} - -static struct tag *setup_commandline_tag(struct tag *params, char *cmdline) -{ - if (!cmdline) - return params; - - /* eat leading white space */ - while (*cmdline == ' ') cmdline++; - - /* - * Don't include tags for empty command lines; let the kernel - * use its default command line. - */ - if (*cmdline == '\0') - return params; - - params->hdr.tag = ATAG_CMDLINE; - params->hdr.size = - (sizeof (struct tag_header) + strlen(cmdline) + 1 + 3) >> 2; - strcpy(params->u.cmdline.cmdline, cmdline); - - return tag_next(params); -} - -static struct tag *setup_ramdisk_tag(struct tag *params, - unsigned long rd_start, - unsigned long rd_end) -{ - if (rd_start == rd_end) - return params; - - params->hdr.tag = ATAG_RDIMG; - params->hdr.size = tag_size(tag_mem_range); - - params->u.mem_range.addr = rd_start; - params->u.mem_range.size = rd_end - rd_start; - - return tag_next(params); -} - -static struct tag *setup_clock_tags(struct tag *params) -{ - params->hdr.tag = ATAG_CLOCK; - params->hdr.size = tag_size(tag_clock); - params->u.clock.clock_id = ACLOCK_BOOTCPU; - params->u.clock.clock_flags = 0; - params->u.clock.clock_hz = gd->arch.cpu_hz; - -#ifdef CONFIG_AT32AP7000 - /* - * New kernels don't need this, but we should be backwards - * compatible for a while... - */ - params = tag_next(params); - - params->hdr.tag = ATAG_CLOCK; - params->hdr.size = tag_size(tag_clock); - params->u.clock.clock_id = ACLOCK_HSB; - params->u.clock.clock_flags = 0; - params->u.clock.clock_hz = get_hsb_clk_rate(); -#endif - - return tag_next(params); -} - -static struct tag *setup_ethernet_tag(struct tag *params, - char *addr, int index) -{ - char *s, *e; - int i; - - params->hdr.tag = ATAG_ETHERNET; - params->hdr.size = tag_size(tag_ethernet); - - params->u.ethernet.mac_index = index; - params->u.ethernet.mii_phy_addr = gd->bd->bi_phy_id[index]; - - s = addr; - for (i = 0; i < 6; i++) { - params->u.ethernet.hw_address[i] = simple_strtoul(s, &e, 16); - s = e + 1; - } - - return tag_next(params); -} - -static struct tag *setup_ethernet_tags(struct tag *params) -{ - char name[16] = "ethaddr"; - char *addr; - int i = 0; - - do { - addr = getenv(name); - if (addr) - params = setup_ethernet_tag(params, addr, i); - sprintf(name, "eth%daddr", ++i); - } while (i < 4); - - return params; -} - -static struct tag *setup_boardinfo_tag(struct tag *params) -{ - params->hdr.tag = ATAG_BOARDINFO; - params->hdr.size = tag_size(tag_boardinfo); - - params->u.boardinfo.board_number = gd->bd->bi_board_number; - - return tag_next(params); -} - -static void setup_end_tag(struct tag *params) -{ - params->hdr.tag = ATAG_NONE; - params->hdr.size = 0; -} - -int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) -{ - void (*theKernel)(int magic, void *tagtable); - struct tag *params, *params_start; - char *commandline = getenv("bootargs"); - - /* - * allow the PREP bootm subcommand, it is required for bootm to work - * - * TODO: Andreas Bießmann <andreas(a)biessmann.org> refactor the - * do_bootm_linux() for avr32 - */ - if (flag & BOOTM_STATE_OS_PREP) - return 0; - - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - - theKernel = (void *)images->ep; - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - - params = params_start = (struct tag *)gd->bd->bi_boot_params; - params = setup_start_tag(params); - params = setup_memory_tags(params); - if (images->rd_start) { - params = setup_ramdisk_tag(params, - PHYSADDR(images->rd_start), - PHYSADDR(images->rd_end)); - } - params = setup_commandline_tag(params, commandline); - params = setup_clock_tags(params); - params = setup_ethernet_tags(params); - params = setup_boardinfo_tag(params); - setup_end_tag(params); - - printf("\nStarting kernel at %p (params at %p)...\n\n", - theKernel, params_start); - - prepare_to_boot(); - - theKernel(ATAG_MAGIC, params_start); - /* does not return */ - - return 1; -} diff --git a/arch/avr32/lib/dram_init.c b/arch/avr32/lib/dram_init.c deleted file mode 100644 index 79c2455bd6..0000000000 --- a/arch/avr32/lib/dram_init.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2015 Andreas Bießmann <andreas(a)biessmann.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* check for the maximum amount of memory possible on AP7000 devices */ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - (256<<20)); - return 0; -} diff --git a/arch/avr32/lib/interrupts.c b/arch/avr32/lib/interrupts.c deleted file mode 100644 index 5f3a49e152..0000000000 --- a/arch/avr32/lib/interrupts.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/sysreg.h> - -int interrupt_init(void) -{ - return 0; -} - -void enable_interrupts(void) -{ - asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET)); -} - -int disable_interrupts(void) -{ - unsigned long sr; - - sr = sysreg_read(SR); - asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET)); - -#ifdef CONFIG_AT32UC3A0xxx - /* Two NOPs are required after masking interrupts on the - * AT32UC3A0512ES. See errata 41.4.5.5. */ - asm("nop"); - asm("nop"); -#endif - - return !SYSREG_BFEXT(GM, sr); -} diff --git a/arch/avr32/lib/memset.S b/arch/avr32/lib/memset.S deleted file mode 100644 index ac2d38860e..0000000000 --- a/arch/avr32/lib/memset.S +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - /* - * r12: void *b - * r11: int c - * r10: size_t len - * - * Returns b in r12 - */ - .section .text.memset, "ax", @progbits - - .global memset - .type memset, @function - .align 2 -memset: - mov r9, r12 - mov r8, r12 - or r11, r11, r11 << 8 - andl r9, 3, COH - brne 1f - -2: or r11, r11, r11 << 16 - sub r10, 4 - brlt 5f - - /* Let's do some real work */ -4: st.w r8++, r11 - sub r10, 4 - brge 4b - - /* - * When we get here, we've got less than 4 bytes to set. r10 - * might be negative. - */ -5: sub r10, -4 - reteq r12 - - /* Fastpath ends here, exactly 32 bytes from memset */ - - /* Handle unaligned count or pointer */ - bld r10, 1 - brcc 6f - st.b r8++, r11 - st.b r8++, r11 - bld r10, 0 - retcc r12 -6: st.b r8++, r11 - mov pc, lr - - /* Handle unaligned pointer */ -1: sub r10, 4 - brlt 5b - add r10, r9 - lsl r9, 1 - add pc, r9 - st.b r8++, r11 - st.b r8++, r11 - st.b r8++, r11 - rjmp 2b - - .size memset, . - memset diff --git a/board/atmel/atngw100/Kconfig b/board/atmel/atngw100/Kconfig deleted file mode 100644 index 28037b67b4..0000000000 --- a/board/atmel/atngw100/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ATNGW100 - -config SYS_BOARD - default "atngw100" - -config SYS_VENDOR - default "atmel" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "atngw100" - -endif diff --git a/board/atmel/atngw100/MAINTAINERS b/board/atmel/atngw100/MAINTAINERS deleted file mode 100644 index 1c319f66b4..0000000000 --- a/board/atmel/atngw100/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ATNGW100 BOARD -#M: Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> -S: Orphan (since 2014-06) -F: board/atmel/atngw100/ -F: include/configs/atngw100.h -F: configs/atngw100_defconfig diff --git a/board/atmel/atngw100/Makefile b/board/atmel/atngw100/Makefile deleted file mode 100644 index f9b93c9738..0000000000 --- a/board/atmel/atngw100/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := atngw100.o diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c deleted file mode 100644 index dacd427831..0000000000 --- a/board/atmel/atngw100/atngw100.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -static const struct sdram_config sdram_config = { - .data_bits = SDRAM_DATA_16BIT, - .row_bits = 13, - .col_bits = 9, - .bank_bits = 2, - .cas = 3, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 5, - .txsr = 5, - /* 7.81 us */ - .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, -}; - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - - portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH); - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart1(PORTMUX_DRIVE_MIN); - -#if defined(CONFIG_MACB) - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); - portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); -#endif -#if defined(CONFIG_MMC) - portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); -#endif -#if defined(CONFIG_ATMEL_SPI) - portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x01; - gd->bd->bi_phy_id[1] = 0x03; - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bi) -{ - macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); - macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); - return 0; -} -#endif - -/* SPI chip select control */ -#ifdef CONFIG_ATMEL_SPI -#include <spi.h> - -#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3) - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1); -} -#endif /* CONFIG_ATMEL_SPI */ diff --git a/board/atmel/atngw100mkii/Kconfig b/board/atmel/atngw100mkii/Kconfig deleted file mode 100644 index ca04269080..0000000000 --- a/board/atmel/atngw100mkii/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ATNGW100MKII - -config SYS_BOARD - default "atngw100mkii" - -config SYS_VENDOR - default "atmel" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "atngw100mkii" - -endif diff --git a/board/atmel/atngw100mkii/MAINTAINERS b/board/atmel/atngw100mkii/MAINTAINERS deleted file mode 100644 index 54eb1da4c2..0000000000 --- a/board/atmel/atngw100mkii/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ATNGW100MKII BOARD -M: Andreas Bießmann <andreas(a)biessmann.org> -S: Maintained -F: board/atmel/atngw100mkii/ -F: include/configs/atngw100mkii.h -F: configs/atngw100mkii_defconfig diff --git a/board/atmel/atngw100mkii/Makefile b/board/atmel/atngw100mkii/Makefile deleted file mode 100644 index 90bf5bc84e..0000000000 --- a/board/atmel/atngw100mkii/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := atngw100mkii.o diff --git a/board/atmel/atngw100mkii/atngw100mkii.c b/board/atmel/atngw100mkii/atngw100mkii.c deleted file mode 100644 index 68662c4045..0000000000 --- a/board/atmel/atngw100mkii/atngw100mkii.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (C) 2010 Atmel Corporation - * - * Copyright (C) 2012 Andreas Bießmann <andreas(a)biessmann.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <spi.h> -#include <netdev.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */ - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */ - .virt_pgno = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT, - .phys = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */ - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -static const struct sdram_config sdram_config = { - .data_bits = SDRAM_DATA_32BIT, - .row_bits = 13, - .col_bits = 10, - .bank_bits = 2, - .cas = 3, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 5, - .txsr = 6, - /* 7.81 us */ - .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, -}; - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE) - | HMATRIX_BIT(EBI_NAND_ENABLE)); - - portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND, - PORTMUX_DRIVE_HIGH); - portmux_select_gpio(PORTMUX_PORT_E, 1 << 23, - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH - | PORTMUX_DRIVE_MIN); - - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart1(PORTMUX_DRIVE_MIN); - -#if defined(CONFIG_MACB) - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); - portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); -#endif -#if defined(CONFIG_MMC) - portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); -#endif -#if defined(CONFIG_ATMEL_SPI) - portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x01; - gd->bd->bi_phy_id[1] = 0x03; - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bi) -{ - macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); - macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); - return 0; -} -#endif - -/* SPI chip select control */ -#ifdef CONFIG_ATMEL_SPI -#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3) - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1); -} -#endif /* CONFIG_ATMEL_SPI */ diff --git a/board/atmel/atstk1000/Kconfig b/board/atmel/atstk1000/Kconfig deleted file mode 100644 index b4fa9a2b38..0000000000 --- a/board/atmel/atstk1000/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ATSTK1002 - -config SYS_BOARD - default "atstk1000" - -config SYS_VENDOR - default "atmel" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "atstk1002" - -endif diff --git a/board/atmel/atstk1000/MAINTAINERS b/board/atmel/atstk1000/MAINTAINERS deleted file mode 100644 index 1070f98e53..0000000000 --- a/board/atmel/atstk1000/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ATSTK1000 BOARD -M: Andreas Bießmann <andreas.biessmann(a)corscience.de> -S: Maintained -F: board/atmel/atstk1000/ -F: include/configs/atstk1002.h -F: configs/atstk1002_defconfig diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile deleted file mode 100644 index ad76631b97..0000000000 --- a/board/atmel/atstk1000/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y += atstk1000.o diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c deleted file mode 100644 index 679b67432c..0000000000 --- a/board/atmel/atstk1000/atstk1000.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -static const struct sdram_config sdram_config = { - .data_bits = SDRAM_DATA_32BIT, -#ifdef CONFIG_ATSTK1000_16MB_SDRAM - /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */ - .row_bits = 12, -#else - /* MT48LC2M32B2P-5 (8 MB) on motherboard */ - .row_bits = 11, -#endif - .col_bits = 8, - .bank_bits = 2, - .cas = 3, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 5, - .txsr = 5, - /* 15.6 us */ - .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, -}; - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - - portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH); - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart1(PORTMUX_DRIVE_MIN); - -#if defined(CONFIG_MACB) - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW); - portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW); -#endif -#if defined(CONFIG_MMC) - portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x10; - gd->bd->bi_phy_id[1] = 0x11; - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bi) -{ - macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); - macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); - return 0; -} -#endif diff --git a/board/in-circuit/grasshopper/Kconfig b/board/in-circuit/grasshopper/Kconfig deleted file mode 100644 index 30e3855ae0..0000000000 --- a/board/in-circuit/grasshopper/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_GRASSHOPPER - -config SYS_BOARD - default "grasshopper" - -config SYS_VENDOR - default "in-circuit" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "grasshopper" - -endif diff --git a/board/in-circuit/grasshopper/MAINTAINERS b/board/in-circuit/grasshopper/MAINTAINERS deleted file mode 100644 index 4abdea8da8..0000000000 --- a/board/in-circuit/grasshopper/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GRASSHOPPER BOARD -M: Andreas Bießmann <andreas(a)biessmann.org> -S: Maintained -F: board/in-circuit/grasshopper/ -F: include/configs/grasshopper.h -F: configs/grasshopper_defconfig diff --git a/board/in-circuit/grasshopper/Makefile b/board/in-circuit/grasshopper/Makefile deleted file mode 100644 index 04576358fd..0000000000 --- a/board/in-circuit/grasshopper/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# Copyright (C) 2011 -# Corscience GmbH & Co.KG, Andreas Bießmann <biessmann(a)corscience.de> -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y += grasshopper.o diff --git a/board/in-circuit/grasshopper/grasshopper.c b/board/in-circuit/grasshopper/grasshopper.c deleted file mode 100644 index 91b41162de..0000000000 --- a/board/in-circuit/grasshopper/grasshopper.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2011 - * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann(a)corscience.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -static const struct sdram_config sdram_config = { - /* Dual MT48LC16M16A2-7E (or equal) */ - .data_bits = SDRAM_DATA_32BIT, - .row_bits = 13, - .col_bits = 9, - .bank_bits = 2, - .cas = 2, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 4, - .txsr = 7, - /* 7.81 us */ - .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, -}; - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - - portmux_enable_ebi(SDRAM_DATA_32BIT, 23, 0, PORTMUX_DRIVE_HIGH); - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart0(PORTMUX_DRIVE_MIN); - portmux_enable_usart1(PORTMUX_DRIVE_MIN); -#if defined(CONFIG_MACB) - /* set PHY reset and pwrdown to low */ - portmux_select_gpio(PORTMUX_PORT_B, (1 << 29) | (1 << 30), - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_LOW); - udelay(100); - /* release PHYs reset */ - gpio_set_value(GPIO_PIN_PB(29), 1); - - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x00; - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bi) -{ - macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); - return 0; -} -#endif -/* vim: set noet ts=8: */ diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 89b73f4fb9..401a694712 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -83,9 +83,6 @@ static inline void print_bi_mem(const bd_t *bd) #elif defined(CONFIG_ARC) print_num("mem start", (ulong)bd->bi_memstart); print_lnum("mem size", (u64)bd->bi_memsize); -#elif defined(CONFIG_AVR32) - print_num("memstart", (ulong)bd->bi_dram[0].start); - print_lnum("memsize", (u64)bd->bi_dram[0].size); #else print_num("memstart", (ulong)bd->bi_memstart); print_lnum("memsize", (u64)bd->bi_memsize); @@ -300,14 +297,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -#elif defined(CONFIG_AVR32) - -int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - print_std_bdinfo(gd->bd); - return 0; -} - #elif defined(CONFIG_ARM) static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, diff --git a/common/board_r.c b/common/board_r.c index adc1f1937e..3341a528b0 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -57,9 +57,6 @@ #include <dm/root.h> #include <linux/compiler.h> #include <linux/err.h> -#ifdef CONFIG_AVR32 -#include <asm/arch/mmu.h> -#endif #include <efi_loader.h> DECLARE_GLOBAL_DATA_PTR; @@ -526,7 +523,7 @@ static int initr_api(void) #endif /* enable exceptions */ -#if defined(CONFIG_ARM) || defined(CONFIG_AVR32) +#ifdef CONFIG_ARM static int initr_enable_interrupts(void) { enable_interrupts(); @@ -845,10 +842,10 @@ static init_fnc_t init_sequence_r[] = { initr_kgdb, #endif interrupt_init, -#if defined(CONFIG_ARM) || defined(CONFIG_AVR32) +#ifdef CONFIG_ARM initr_enable_interrupts, #endif -#if defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || defined(CONFIG_M68K) +#if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K) timer_init, /* initialize timer */ #endif #if defined(CONFIG_LED_STATUS) @@ -919,10 +916,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) int i; #endif -#ifdef CONFIG_AVR32 - mmu_init_r(dest_addr); -#endif - #if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) gd = new_gd; #endif diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig deleted file mode 100644 index 17db763867..0000000000 --- a/configs/atngw100_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_ATNGW100=y -CONFIG_BOOTDELAY=1 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SYS_PROMPT="U-Boot> " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_MMC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig deleted file mode 100644 index 887c5fb8d7..0000000000 --- a/configs/atngw100mkii_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_ATNGW100MKII=y -CONFIG_BOOTDELAY=1 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SYS_PROMPT="U-Boot> " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_MMC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig deleted file mode 100644 index 0fa7969e47..0000000000 --- a/configs/atstk1002_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_ATSTK1002=y -CONFIG_BOOTDELAY=1 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SYS_PROMPT="U-Boot> " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_MMC=y -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig deleted file mode 100644 index 024231dbc6..0000000000 --- a/configs/grasshopper_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_GRASSHOPPER=y -CONFIG_BOOTDELAY=1 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot> " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_CMD_ELF is not set -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -CONFIG_MTD_NOR_FLASH=y diff --git a/doc/README.AVR32 b/doc/README.AVR32 deleted file mode 100644 index 632cc0546d..0000000000 --- a/doc/README.AVR32 +++ /dev/null @@ -1,25 +0,0 @@ -AVR32 is a new high-performance 32-bit RISC microprocessor core, -designed for cost-sensitive embedded applications, with particular -emphasis on low power consumption and high code density. The AVR32 -architecture is not binary compatible with earlier 8-bit AVR -architectures. - -The AVR32 architecture, including the instruction set, is described -by the AVR32 Architecture Manual, available from - -http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf - -A GNU toolchain with support for AVR32, along with non-GNU programming -and debugging support, can be downloaded from - -http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4118 - -A full set of u-boot, kernel and filesystem images can be built using -buildroot. This will also produce a working toolchain which can be -used instead of the official GNU toolchain above. A customized version -of buildroot for AVR32 can be downloaded here: - -http://www.atmel.no/buildroot/ - -The AVR32 ports of u-boot, the Linux kernel, the GNU toolchain and -other associated software are actively supported by Atmel Corporation. diff --git a/doc/README.AVR32-port-muxing b/doc/README.AVR32-port-muxing deleted file mode 100644 index 8c1718cdca..0000000000 --- a/doc/README.AVR32-port-muxing +++ /dev/null @@ -1,208 +0,0 @@ -AVR32 Port multiplexer configuration -==================================== - -On AVR32 chips, most external I/O pins are routed through a port -multiplexer. There are currently two kinds of port multiplexer -hardware around with different register interfaces: - - * PIO (AT32AP700x; this is also used on ARM AT91 chips) - * GPIO (all other AVR32 chips) - -The "PIO" variant supports multiplexing up to two peripherals per pin -in addition to GPIO (software control). Each pin has configurable -pull-up, glitch filter, interrupt and multi-drive capabilities. - -The "GPIO" variant supports multiplexing up to four peripherals per -pin in addition to GPIO. Each pin has configurable -pull-up/pull-down/buskeeper, glitch filter, interrupt, open-drain and -schmitt-trigger capabilities, as well as configurable drive strength -and slew rate control. - -Both controllers are configured using the same API, but the functions -may accept different values for some parameters depending on the -actual portmux implementation, and some parameters may be ignored by -one of the implementation (e.g. the "PIO" implementation will ignore -the drive strength flags since the hardware doesn't support -configurable drive strength.) - -Selecting the portmux implementation ------------------------------------- -Since u-boot is lacking a Kconfig-style configuration engine, the -portmux implementation must be selected manually by defining one of -the following symbols: - - CONFIG_PORTMUX_PIO - CONFIG_PORTMUX_GPIO - -depending on which implementation the chip in question uses. - -Identifying pins ----------------- -The portmux configuration functions described below identify the pins -to act on based on two parameters: A "port" (i.e. a block of pins -that somehow belong together) and a pin mask. Both are defined in an -implementation-specific manner. - -The available ports are defined on the form - - #define PORTMUX_PORT_A (something) - -where "A" matches the identifier given in the chip's data sheet, and -"something" is whatever the portmux implementation needs to identify -the port (usually a memory address). - -The pin mask is a bitmask where each '1' bit indicates a pin to apply -the current operation to. The width of the bitmask may vary from port -to port, but it is never wider than 32 bits (which is the width of -'unsigned long' on avr32). - -Selecting functions -------------------- -Each pin can either be assigned to one of a predefined set of on-chip -peripherals, or it can be set up to be controlled by software. For the -former case, the portmux implementation defines an enum containing all -the possible peripheral functions that can be selected. For example, -the PIO implementation, which allows multiplexing two peripherals per -pin, defines it like this: - - enum portmux_function { - PORTMUX_FUNC_A, - PORTMUX_FUNC_B, - }; - -To configure a set of pins to be connected to a given peripheral -function, the following function is used. - - void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags); - -To configure a set of pins to be controlled by software (GPIO), the -following function is used. In this case, no "function" argument is -required since "GPIO" is a function in its own right. - - void portmux_select_gpio(void *port, unsigned int pin_mask, - unsigned long flags); - -Both of these functions take a "flags" parameter which may be used to -alter the default configuration of the pin. This is a bitmask of -various flags defined in an implementation-specific way, but the names -of the flags are the same on all implementations. - - PORTMUX_DIR_OUTPUT - PORTMUX_DIR_INPUT - -These mutually-exclusive flags configure the initial direction of the -pins. PORTMUX_DIR_OUTPUT means that the pins are driven by the CPU, -while PORTMUX_DIR_INPUT means that the pins are tristated by the CPU. -These flags are ignored by portmux_select_peripheral(). - - PORTMUX_INIT_HIGH - PORTMUX_INIT_LOW - -These mutually-exclusive flags configure the initial state of the -pins: High (Vdd) or low (Vss). They are only effective when -portmux_select_gpio() is called with the PORTMUX_DIR_OUTPUT flag set. - - PORTMUX_PULL_UP - PORTMUX_PULL_DOWN - PORTMUX_BUSKEEPER - -These mutually-exclusive flags are used to enable any on-chip CMOS -resistors connected to the pins. PORTMUX_PULL_UP causes the pins to be -pulled up to Vdd, PORTMUX_PULL_DOWN causes the pins to be pulled down -to Vss, and PORTMUX_BUSKEEPER will keep the pins in whatever state -they were left in by whatever was driving them last. If none of the -flags are specified, the pins are left floating if no one are driving -them; this is only recommended for always-output pins (e.g. extern -address and control lines driven by the CPU.) - -Note that the "PIO" implementation will silently ignore the -PORTMUX_PULL_DOWN flag and interpret PORTMUX_BUSKEEPER as -PORTMUX_PULL_UP. - - PORTMUX_DRIVE_MIN - PORTMUX_DRIVE_LOW - PORTMUX_DRIVE_HIGH - PORTMUX_DRIVE_MAX - -These mutually-exclusive flags determine the drive strength of the -pins. PORTMUX_DRIVE_MIN will give low power-consumption, but may cause -corruption of high-speed signals. PORTMUX_DRIVE_MAX will give high -power-consumption, but may be necessary on pins toggling at very high -speeds. PORTMUX_DRIVE_LOW and PORTMUX_DRIVE_HIGH specify something in -between the other two. - -Note that setting the drive strength too high may cause excessive -overshoot and EMI problems, which may in turn cause signal corruption. -Also note that the "PIO" implementation will silently ignore these -flags. - - PORTMUX_OPEN_DRAIN - -This flag will configure the pins as "open drain", i.e. setting the -pin state to 0 will drive it low, while setting it to 1 will leave it -floating (or, in most cases, let it be pulled high by an internal or -external pull-up resistor.) In the data sheet for chips using the -"PIO" variant, this mode is called "multi-driver". - -Enabling specific peripherals ------------------------------ -In addition to the above functions, each chip provides a set of -functions for setting up the port multiplexer to use a given -peripheral. The following are some of the functions available. - -All the functions below take a "drive_strength" parameter, which must -be one of the PORTMUX_DRIVE_x flags specified above. Any other -portmux flags will be silently filtered out. - -To set up the External Bus Interface (EBI), call - - void portmux_enable_ebi(unsigned int bus_width, - unsigned long flags, unsigned long drive_strength) - -where "bus_width" must be either 16 or 32. "flags" can be any -combination of the following flags. - - PORTMUX_EBI_CS(x) /* Enable chip select x */ - PORTMUX_EBI_NAND /* Enable NAND flash interface */ - PORTMUX_EBI_CF(x) /* Enable CompactFlash interface x */ - PORTMUX_EBI_NWAIT /* Enable NWAIT signal */ - -To set up a USART, call - - void portmux_enable_usartX(unsigned long drive_strength); - -where X is replaced by the USART instance to be configured. - -To set up an ethernet MAC: - - void portmux_enable_macbX(unsigned long flags, - unsigned long drive_strength); - -where X is replaced by the MACB instance to be configured. "flags" can -be any combination of the following flags. - - PORTMUX_MACB_RMII /* Just set up the RMII interface */ - PORTMUX_MACB_MII /* Set up full MII interface */ - PORTMUX_MACB_SPEED /* Enable the SPEED pin */ - -To set up the MMC controller: - - void portmux_enable_mmci(unsigned long slot, unsigned long flags - unsigned long drive_strength); - -where "slot" identifies which of the alternative SD card slots to -enable. "flags" can be any combination of the following flags: - - PORTMUX_MMCI_4BIT /* Enable 4-bit SD card interface */ - PORTMUX_MMCI_8BIT /* Enable 8-bit MMC+ interface */ - PORTMUX_MMCI_EXT_PULLUP /* Board has external pull-ups */ - -To set up a SPI controller: - - void portmux_enable_spiX(unsigned long cs_mask, - unsigned long drive_strength); - -where X is replaced by the SPI instance to be configured. "cs_mask" is -a 4-bit bitmask specifying which of the four standard chip select -lines to set up as GPIOs. diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci index 6043dabff7..6c027b089f 100644 --- a/doc/README.atmel_mci +++ b/doc/README.atmel_mci @@ -11,8 +11,7 @@ to write blocks. - AT91SAM9260 (not tested, but MCI is to AT91SAM9XE) - AT91SAM9G20 (not tested, should work) -It should work with all other ATMEL devices that have MCI, -including AVR32. +It should work with all other ATMEL devices that have MCI. The generic driver does NOT assign port pins to the MCI block nor does it start the MCI clock. This has to be handled in a diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 5e5b07d95e..fc0873431a 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -94,12 +94,6 @@ vpac270_ond_256 arm pxa 452ef830 2015-08-30 Marek Vasut xaeniax arm pxa 1c87dd76 2015-08-30 zipitz2 arm pxa 49d8899b 2015-08-30 Cliff Brake <cliff.brake(a)gmail.com> cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs(a)denx.de> -atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> -atstk1004 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> -atstk1006 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> -mimc200 avr32 - c62d2f8f 2015-06-10 Mark Jackson <mpfj(a)mimc.co.uk> -hammerhead avr32 - e3693076 2015-06-10 Alex Raimondi <alex.raimondi(a)miromico.ch> -favr-32-ezkit avr32 - 9eb45aab 2015-06-10 Hans-Christian Egtvedt <hans-christian.egtvedt(a)atmel.com> afeb9260 arm arm926ejs f6b42c14 2015-05-13 Sergey Lapin <slapin(a)ossfans.org> tny_a9260 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre(a)free-electrons.com> sbc35_a9g20 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre(a)free-electrons.com> diff --git a/doc/git-mailrc b/doc/git-mailrc index 04c6c8df9d..af10a3d68e 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -54,7 +54,7 @@ alias vapier Mike Frysinger <vapier(a)gentoo.org> alias wd Wolfgang Denk <wd(a)denx.de> # Architecture aliases -alias arch arc, arm, avr32, bfin, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, sparc, x86 +alias arch arc, arm, bfin, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, sparc, x86 alias arches arch alias arc uboot, abrodkin @@ -79,7 +79,6 @@ alias ti uboot, trini alias uniphier uboot, masahiro alias zynq uboot, monstr alias rockchip uboot, sjg, Kever Yang <kever.yang(a)rock-chips.com>, ptomsich -alias avr32 uboot, abiessmann alias bfin uboot, vapier, sonic alias blackfin bfin diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index de3758d946..50597a7d5a 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -17,8 +17,9 @@ */ #include <common.h> -#if defined(CONFIG_AVR32) -#include <asm/arch/portmux.h> +#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ +#include <ioports.h> +#include <asm/io.h> #endif #if defined(CONFIG_AT91FAMILY) #include <asm/io.h> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index bef864f46e..fe01c737d7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -37,8 +37,8 @@ config ATMEL_SPI depends on ARCH_AT91 help This enables driver for the Atmel SPI Controller, present on - many AT32 (AVR32) and AT91 (ARM) chips. This driver can be - used to access the SPI Flash, such as AT25DF321. + many AT91 (ARM) chips. This driver can be used to access + the SPI Flash, such as AT25DF321. config CADENCE_QSPI bool "Cadence QSPI driver" diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h index 92e462db60..c6d12d3a8e 100644 --- a/drivers/usb/gadget/atmel_usba_udc.h +++ b/drivers/usb/gadget/atmel_usba_udc.h @@ -44,13 +44,8 @@ #define USBA_REMOTE_WAKE_UP (1 << 10) #define USBA_PULLD_DIS (1 << 11) -#if defined(CONFIG_AVR32) -#define USBA_ENABLE_MASK USBA_EN_USBA -#define USBA_DISABLE_MASK 0 -#elif defined(CONFIG_AT91FAMILY) #define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS) #define USBA_DISABLE_MASK USBA_DETACH -#endif /* CONFIG_ARCH_AT91 */ /* Bitfields in FNUM */ #define USBA_MICRO_FRAME_NUM_OFFSET 0 diff --git a/drivers/usb/musb-new/musb_io.h b/drivers/usb/musb-new/musb_io.h index 76682120f4..a4f4a6f8f4 100644 --- a/drivers/usb/musb-new/musb_io.h +++ b/drivers/usb/musb-new/musb_io.h @@ -22,7 +22,7 @@ #endif #if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \ - && !defined(CONFIG_AVR32) && !defined(CONFIG_PPC32) \ + && !defined(CONFIG_PPC32) \ && !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \ && !defined(CONFIG_M68K) static inline void readsl(const void __iomem *addr, void *buf, int len) diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index ed2bd306c6..2b9482a091 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -150,11 +150,7 @@ static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix, value << ATMEL_LCDC_CLKVAL_OFFSET); /* Initialize control register 2 */ -#ifdef CONFIG_AVR32 - value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; -#else value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; -#endif if (tft) value |= ATMEL_LCDC_DISTYPE_TFT; diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index d75abb660f..f54802052e 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1968,7 +1968,7 @@ static void *video_logo(void) static int cfb_fb_is_in_dram(void) { bd_t *bd = gd->bd; -#if defined(CONFIG_ARM) || defined(CONFIG_AVR32) || defined(CONFIG_NDS32) || \ +#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || \ defined(CONFIG_SANDBOX) || defined(CONFIG_X86) ulong start, end; int i; diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index a6a9fcf189..9c7a8c00f8 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -141,19 +141,6 @@ gd_t *global_data; " lwi r5, r5, %1\n" \ " bra r5\n" \ : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r5"); -#elif defined(CONFIG_AVR32) -/* - * r6 holds the pointer to the global_data. r8 is call clobbered. - */ -#define EXPORT_FUNC(f, a, x, ...) \ - asm volatile( \ - " .globl\t" #x "\n" \ - #x ":\n" \ - " ld.w r8, r6[%0]\n" \ - " ld.w pc, r8[%1]\n" \ - : \ - : "i"(offsetof(gd_t, jt)), "i"(FO(x)) \ - : "r8"); #elif defined(CONFIG_SH) /* * r13 holds the pointer to the global_data. r1 is a call clobbered. diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index b8f9c7aedb..789592992e 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -32,10 +32,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ -#ifdef CONFIG_AVR32 - unsigned char bi_phy_id[4]; /* PHY address for ATAG_ETHERNET */ - unsigned long bi_board_number;/* ATAG_BOARDINFO */ -#endif #ifdef CONFIG_ARM unsigned long bi_arm_freq; /* arm frequency */ unsigned long bi_dsp_freq; /* dsp core frequency */ diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h deleted file mode 100644 index bf13d937fb..0000000000 --- a/include/configs/atngw100.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * Configuration settings for the AVR32 Network Gateway - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/hardware.h> - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_ATNGW100 - -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency - * and the PBA bus to run at 1/4 the PLL frequency. - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -#define CONFIG_SYS_CLKDIV_CPU 0 -#define CONFIG_SYS_CLKDIV_HSB 1 -#define CONFIG_SYS_CLKDIV_PBA 2 -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 -/* User serviceable stuff */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" -#define CONFIG_BOOTCOMMAND \ - "fsload; bootm" - - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr" and "eth1addr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP/DHCP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - -/* - * Command line configuration. - */ - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_ATMEL_SPI - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h deleted file mode 100644 index a7f5e06c68..0000000000 --- a/include/configs/atngw100mkii.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * Copyright (C) 2012 Andreas Bießmann <andreas(a)biessmann.org> - * - * Configuration settings for the AVR32 Network Gateway - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/hardware.h> - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_ATNGW100MKII - -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency - * and the PBA bus to run at 1/4 the PLL frequency. - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for NOR flash, NAND flash and SDRAM */ -#define CONFIG_SYS_NR_VM_REGIONS 3 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -/* User serviceable stuff */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_BOOTARGS \ - "root=mtd:main rootfstype=jffs2" -#define CONFIG_BOOTCOMMAND \ - "fsload 0x10400000 /uImage; bootm" - - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr" and "eth1addr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP/DHCP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - -/* - * Command line configuration. - */ - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_ATMEL_SPI - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_PROTECTION - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) - -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS - -#endif /* __CONFIG_H */ diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h deleted file mode 100644 index c8e9340af2..0000000000 --- a/include/configs/atstk1002.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * Configuration settings for the ATSTK1002 CPU daughterboard - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/hardware.h> - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_ATSTK1002 -#define CONFIG_ATSTK1000 - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -/* User serviceable stuff */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1" - -#define CONFIG_BOOTCOMMAND \ - "fsload; bootm $(fileaddr)" - - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr" and "eth1addr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - -/* generic board */ -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * Command line configuration. - */ - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_GENERIC_ATMEL_MCI - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h deleted file mode 100644 index 83b78907f2..0000000000 --- a/include/configs/grasshopper.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (C) 2011 - * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann(a)corscience.de> - * - * Configuration settings for the grasshopper (ICnova AP7000) board - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __GRASSHOPPER_CONFIG_H -#define __GRASSHOPPER_CONFIG_H - -#include <asm/arch/hardware.h> - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -#define CONFIG_BOARD_EARLY_INIT_R - -/* User serviceable stuff */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - -/* - * Command line configuration. - */ -/* add useful commands */ -#define CONFIG_CMD_REGINFO - -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -/* place u-boot env in flash sector after u-boot */ -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0x20000 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + \ - CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) - -#endif /* __GRASSHOPPER_CONFIG_H */ -/* vim: set ts=8 noet: */ diff --git a/include/linux/fb.h b/include/linux/fb.h index fcf331b79f..c820a4f77b 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -537,7 +537,7 @@ struct fb_info { #define fb_writeq sbus_writeq #define fb_memset sbus_memset_io -#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || defined(__avr32__) || defined(__bfin__) +#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || defined(__bfin__) #define fb_readb __raw_readb #define fb_readw __raw_readw diff --git a/include/linux/stat.h b/include/linux/stat.h index 1af0876621..5eba6334e6 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -126,7 +126,7 @@ struct stat { #endif /* __MIPS__ */ -#if defined(__AVR32__) || defined(__SH__) || defined(__XTENSA__) +#if defined(__SH__) || defined(__XTENSA__) struct stat { unsigned long st_dev; @@ -149,7 +149,7 @@ struct stat { unsigned long __unused5; }; -#endif /* __AVR32__ || __SH__ || __XTENSA__ */ +#endif /* __SH__ || __XTENSA__ */ #ifdef __cplusplus } diff --git a/scripts/checkstack.pl b/scripts/checkstack.pl index dd8397894d..f4f4a5fa47 100755 --- a/scripts/checkstack.pl +++ b/scripts/checkstack.pl @@ -12,7 +12,6 @@ # sh64 port by Paul Mundt # Random bits by Matt Mackall <mpm(a)selenic.com> # M68k port by Geert Uytterhoeven and Andreas Schwab -# AVR32 port by Haavard Skinnemoen (Atmel) # AArch64, PARISC ports by Kyle McMartin # sparc port by Martin Habets <errandir_news(a)mph.eclipse.co.uk> # @@ -51,10 +50,6 @@ my (@stack, $re, $dre, $x, $xs, $funcre); } elsif ($arch eq 'arm') { #c0008ffc: e24dd064 sub sp, sp, #100 ; 0x64 $re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o; - } elsif ($arch eq 'avr32') { - #8000008a: 20 1d sub sp,4 - #80000ca8: fa cd 05 b0 sub sp,sp,1456 - $re = qr/^.*sub.*sp.*,([0-9]{1,8})/o; } elsif ($arch =~ /^x86(_64)?$/ || $arch =~ /^i[3456]86$/) { #c0105234: 81 ec ac 05 00 00 sub $0x5ac,%esp # or diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 95f27b6ead..de4bdb3d37 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -94,9 +94,6 @@ CONFIG_ASTRO_TWIN7S2 CONFIG_ASTRO_V512 CONFIG_ASTRO_V532 CONFIG_ASTRO_V912 -CONFIG_AT32AP -CONFIG_AT32AP7000 -CONFIG_AT32UC3A0xxx CONFIG_AT91C_PQFP_UHPBUG CONFIG_AT91FAMILY CONFIG_AT91RESET_EXTRST @@ -145,11 +142,6 @@ CONFIG_ATMEL_MCI_8BIT CONFIG_ATMEL_NAND_HWECC CONFIG_ATMEL_NAND_HW_PMECC CONFIG_ATMEL_SPI0 -CONFIG_ATNGW100 -CONFIG_ATNGW100MKII -CONFIG_ATSTK1000 -CONFIG_ATSTK1000_16MB_SDRAM -CONFIG_ATSTK1002 CONFIG_AT_TRANS CONFIG_AUTONEG_TIMEOUT CONFIG_AUTO_COMPLETE @@ -1339,7 +1331,6 @@ CONFIG_LAN91C96_USE_32_BIT CONFIG_LAST_STAGE_INIT CONFIG_LAYERSCAPE_NS_ACCESS CONFIG_LBA48 -CONFIG_LBD CONFIG_LBDAF CONFIG_LCD_ALIGNMENT CONFIG_LCD_BMP_RLE8 @@ -1814,7 +1805,6 @@ CONFIG_PLATINUM_CPU CONFIG_PLATINUM_PICON CONFIG_PLATINUM_PROJECT CONFIG_PLATINUM_TITANIUM -CONFIG_PLL CONFIG_PLL1_CLK_FREQ CONFIG_PLL1_DIV2_CLK_FREQ CONFIG_PM @@ -1830,7 +1820,6 @@ CONFIG_PME_PLAT_CLK_DIV CONFIG_PMU CONFIG_PMW_BASE CONFIG_PM_SLEEP -CONFIG_PORTMUX_PIO CONFIG_POST CONFIG_POSTBOOTMENU CONFIG_POST_ALT_LIST @@ -2548,10 +2537,6 @@ CONFIG_SYS_CF_INTC_REG1 CONFIG_SYS_CH7301_I2C CONFIG_SYS_CKEN CONFIG_SYS_CLK -CONFIG_SYS_CLKDIV_CPU -CONFIG_SYS_CLKDIV_HSB -CONFIG_SYS_CLKDIV_PBA -CONFIG_SYS_CLKDIV_PBB CONFIG_SYS_CLKTL_CBCDR CONFIG_SYS_CLK_100 CONFIG_SYS_CLK_100_DDR_100 @@ -2750,7 +2735,6 @@ CONFIG_SYS_DBAT6U_EARLY CONFIG_SYS_DBAT7L CONFIG_SYS_DBAT7U CONFIG_SYS_DCACHE_INV -CONFIG_SYS_DCACHE_LINESZ CONFIG_SYS_DCSRBAR CONFIG_SYS_DCSRBAR_PHYS CONFIG_SYS_DCSR_COP_CCP_ADDR @@ -3482,7 +3466,6 @@ CONFIG_SYS_HOSTNAME CONFIG_SYS_HRCW_HIGH CONFIG_SYS_HRCW_HIGH_BASE CONFIG_SYS_HRCW_LOW -CONFIG_SYS_HSDRAMC CONFIG_SYS_HZ_CLOCK CONFIG_SYS_I2C CONFIG_SYS_I2C2_FSL_OFFSET @@ -3674,7 +3657,6 @@ CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_IBAT7L CONFIG_SYS_IBAT7U CONFIG_SYS_ICACHE_INV -CONFIG_SYS_ICACHE_LINESZ CONFIG_SYS_ICS8N3QV01_I2C CONFIG_SYS_IDE_MAXBUS CONFIG_SYS_IDE_MAXDEVICE @@ -3706,8 +3688,6 @@ CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_INPUT_CLKSRC CONFIG_SYS_INTEL_BOOT CONFIG_SYS_INTERLAKEN -CONFIG_SYS_INTRAM_BASE -CONFIG_SYS_INTRAM_SIZE CONFIG_SYS_INTR_BASE CONFIG_SYS_INTSRAM CONFIG_SYS_INTSRAMSZ @@ -4127,8 +4107,6 @@ CONFIG_SYS_NOR_FTIM2 CONFIG_SYS_NOR_FTIM3 CONFIG_SYS_NOR_OR_PRELIM CONFIG_SYS_NO_DCACHE -CONFIG_SYS_NR_PIOS -CONFIG_SYS_NR_VM_REGIONS CONFIG_SYS_NS16550_CLK CONFIG_SYS_NS16550_CLK_DIV CONFIG_SYS_NS16550_COM1 @@ -4217,8 +4195,6 @@ CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR7_PRELIM CONFIG_SYS_OR_TIMING_FLASH CONFIG_SYS_OR_TIMING_MRAM -CONFIG_SYS_OSC0_HZ -CONFIG_SYS_OSC1_HZ CONFIG_SYS_OSCIN_FREQ CONFIG_SYS_OSD_DH CONFIG_SYS_OSD_SCREENS @@ -4504,10 +4480,6 @@ CONFIG_SYS_PL310_BASE CONFIG_SYS_PLATFORM_SRAM_BASE CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS CONFIG_SYS_PLATFORM_SRAM_SIZE -CONFIG_SYS_PLL0_DIV -CONFIG_SYS_PLL0_MUL -CONFIG_SYS_PLL0_OPT -CONFIG_SYS_PLL0_SUPPRESS_CYCLES CONFIG_SYS_PLLAR_VAL CONFIG_SYS_PLLBR_VAL CONFIG_SYS_PLLCR @@ -4553,7 +4525,6 @@ CONFIG_SYS_POST_UART CONFIG_SYS_POST_USB CONFIG_SYS_POST_WATCHDOG CONFIG_SYS_POST_WORD_ADDR -CONFIG_SYS_POWER_MANAGER CONFIG_SYS_PPC_DDR_WIMGE CONFIG_SYS_PQSPAR CONFIG_SYS_PRELIM_OR_AM diff --git a/tools/buildman/README b/tools/buildman/README index f66527665a..aaee58152b 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -343,12 +343,6 @@ Toolchain '/toolchains/gcc-4.6.3-nolibc/m68k-linux/bin/m68k-linux-gcc' at priori - looking in '/toolchains/gcc-4.6.3-nolibc/powerpc-linux/usr/bin' Tool chain test: OK, arch='powerpc', priority 4 Tool chain test: OK, arch='or32', priority 4 - - scanning path '/toolchains/gcc-4.2.4-nolibc/avr32-linux' - - looking in '/toolchains/gcc-4.2.4-nolibc/avr32-linux/.' - - looking in '/toolchains/gcc-4.2.4-nolibc/avr32-linux/bin' - - found '/toolchains/gcc-4.2.4-nolibc/avr32-linux/bin/avr32-linux-gcc' - - looking in '/toolchains/gcc-4.2.4-nolibc/avr32-linux/usr/bin' -Tool chain test: OK, arch='avr32', priority 4 - scanning path '/' - looking in '/.' - looking in '/bin' @@ -381,7 +375,6 @@ aarch64 : /toolchains/gcc-4.9.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc alpha : /toolchains/gcc-4.9.0-nolibc/alpha-linux/bin/alpha-linux-gcc am33_2.0 : /toolchains/gcc-4.9.0-nolibc/am33_2.0-linux/bin/am33_2.0-linux-gcc arm : /opt/arm-eabi-4.6/bin/arm-eabi-gcc -avr32 : /toolchains/gcc-4.2.4-nolibc/avr32-linux/bin/avr32-linux-gcc bfin : /toolchains/gcc-4.6.3-nolibc/bfin-uclinux/bin/bfin-uclinux-gcc c89 : /usr/bin/c89-gcc c99 : /usr/bin/c99-gcc @@ -428,7 +421,7 @@ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.2/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.2.4/ -Available architectures: alpha am33_2.0 arm avr32 bfin cris crisv32 frv h8300 +Available architectures: alpha am33_2.0 arm bfin cris crisv32 frv h8300 hppa hppa64 i386 ia64 m32r m68k mips mips64 or32 powerpc powerpc64 s390x sh4 sparc sparc64 tilegx x86_64 xtensa @@ -473,7 +466,7 @@ Buildman should now be set up to use your new toolchain. At the time of writing, U-Boot has these architectures: - arc, arm, avr32, blackfin, m68k, microblaze, mips, nds32, nios2, openrisc + arc, arm, blackfin, m68k, microblaze, mips, nds32, nios2, openrisc powerpc, sandbox, sh, sparc, x86 Of these, only arc and nds32 are not available at kernel.org.. diff --git a/tools/moveconfig.py b/tools/moveconfig.py index 95ef352f05..7aa96120a1 100755 --- a/tools/moveconfig.py +++ b/tools/moveconfig.py @@ -206,7 +206,6 @@ CROSS_COMPILE = { 'arc': 'arc-linux-', 'aarch64': 'aarch64-linux-', 'arm': 'arm-unknown-linux-gnueabi-', - 'avr32': 'avr32-linux-', 'm68k': 'm68k-linux-', 'microblaze': 'microblaze-linux-', 'mips': 'mips-linux-', -- 2.11.0

2 1

[U-Boot] [PATCH] km/common: remove unused code
by Holger Brunck 07 Jul '17

07 Jul '17

The 82xx board mgcoge3ne was removed from the codebase, so this is dead code. Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> Cc: Heiko Schocher <hs(a)denx.de> --- board/keymile/common/common.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 0829b7fa06..408079c9a1 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -355,9 +355,6 @@ static int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc, #if defined(CONFIG_POST) testpin = post_hotkeys_pressed(); #endif -#if defined(CONFIG_MGCOGE3NE) - testpin = get_testpin(); -#endif s = getenv("test_bank"); /* when test_bank is not set, act as if testpin is not asserted */ testboot = (testpin != 0) && (s); -- 2.12.0.rc1

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