June 2017 - U-Boot

[U-Boot] [PATCH 1/2] net: zynq_gem: Use wait_for_bit with non breakable
by Michal Simek 02 Jun '17

02 Jun '17

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Use wait_for_bit to be non breakable as using it with breakable causes issue of un interruptible auto negotiation. This is due to the ctrlc pressed will taken for wait_for_bit() abort during phy_read() and hence not coming out of auto negotiation. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/zynq_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 357f8c2917d2..9c0f5fba28cd 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -192,7 +192,7 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, int err; err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, - true, 20000, true); + true, 20000, false); if (err) return err; @@ -205,7 +205,7 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, writel(mgtcr, &regs->phymntnc); err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, - true, 20000, true); + true, 20000, false); if (err) return err; -- 1.9.1

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[U-Boot] [PATCH] net: phy: marvell 88e151x: Fix handling of RGMII interface types
by Phil Edworthy 02 Jun '17

02 Jun '17

The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- drivers/net/phy/marvell.c | 45 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index ab0c443..8041922 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -13,6 +13,8 @@ #define PHY_AUTONEGOTIATE_TIMEOUT 5000 +#define MII_MARVELL_PHY_PAGE 22 + /* 88E1011 PHY Status Register */ #define MIIM_88E1xxx_PHY_STATUS 0x11 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 @@ -83,6 +85,11 @@ #define MIIM_88E1310_PHY_PAGE 22 /* 88E151x PHY defines */ +/* Page 2 registers */ +#define MIIM_88E151x_PHY_MSCR 21 +#define MIIM_88E151x_RGMII_RX_DELAY BIT(5) +#define MIIM_88E151x_RGMII_TX_DELAY BIT(4) +#define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4)) /* Page 3 registers */ #define MIIM_88E151x_LED_FUNC_CTRL 16 #define MIIM_88E151x_LED_FLD_SZ 4 @@ -295,6 +302,8 @@ void m88e1518_phy_writebits(struct phy_device *phydev, static int m88e1518_config(struct phy_device *phydev) { + u16 reg; + /* * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 * /88E1514 Rev A0, Errata Section 3.1 @@ -331,7 +340,41 @@ static int m88e1518_config(struct phy_device *phydev) udelay(100); } - return m88e1111s_config(phydev); + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + reg = phy_read(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR); + + reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); + reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; + reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR, reg); + } + + if (phy_interface_is_rgmii(phydev)) { + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); + reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + reg |= MIIM_88E151x_RGMII_RXTX_DELAY; + else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + reg |= MIIM_88E151x_RGMII_RX_DELAY; + else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + reg |= MIIM_88E151x_RGMII_TX_DELAY; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0); + } + + /* soft reset */ + phy_reset(phydev); + + genphy_config_aneg(phydev); + genphy_restart_aneg(phydev); + + return 0; } /* Marvell 88E1510 */ -- 2.7.4

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[U-Boot] [PATCH 1/1] net: core: avoid possible NULL pointer dereference
by Heinrich Schuchardt 02 Jun '17

02 Jun '17

Checking if dev is NULL after dereferencing it does not make sense. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- net/eth-uclass.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index c3cc3152a2..b659961a5d 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -181,7 +181,7 @@ int eth_get_dev_index(void) static int eth_write_hwaddr(struct udevice *dev) { - struct eth_pdata *pdata = dev->platdata; + struct eth_pdata *pdata; int ret = 0; if (!dev || !device_active(dev)) @@ -189,6 +189,7 @@ static int eth_write_hwaddr(struct udevice *dev) /* seq is valid since the device is active */ if (eth_get_ops(dev)->write_hwaddr && !eth_mac_skip(dev->seq)) { + pdata = dev->platdata; if (!is_valid_ethaddr(pdata->enetaddr)) { printf("\nError: %s address %pM illegal value\n", dev->name, pdata->enetaddr); -- 2.11.0

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[U-Boot] [PATCH] drivers: net: cpsw: abort init() on aneg timeout
by Sekhar Nori 02 Jun '17

02 Jun '17

Abort CPSW driver init when auto-negotiation of link times out. Currently, the code ignores return status of phy_startup(), and goes ahead with network operation (like DHCP) even though the link may be down. Instead, abort init process if link is down or if there is another error, so phy_startup() can easily be retried again. This also helps quick fallback to next network interface (like USB RNDIS) without inordinate delay. Tested on AM571x IDK and AM335x BeagleBone black. Signed-off-by: Sekhar Nori <nsekhar(a)ti.com> --- drivers/net/cpsw.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 5fbab9e492f8..d85a25904d02 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -612,21 +612,25 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave, #endif } -static void cpsw_slave_update_link(struct cpsw_slave *slave, +static int cpsw_slave_update_link(struct cpsw_slave *slave, struct cpsw_priv *priv, int *link) { struct phy_device *phy; u32 mac_control = 0; + int ret = -ENODEV; phy = priv->phydev; - if (!phy) - return; + goto out; + + ret = phy_startup(phy); + if (ret) + goto out; - phy_startup(phy); - *link = phy->link; + if (link) + *link = phy->link; - if (*link) { /* link up */ + if (phy->link) { /* link up */ mac_control = priv->data.mac_control; if (phy->speed == 1000) mac_control |= GIGABITEN; @@ -637,7 +641,7 @@ static void cpsw_slave_update_link(struct cpsw_slave *slave, } if (mac_control == slave->mac_control) - return; + goto out; if (mac_control) { printf("link up on port %d, speed %d, %s duplex\n", @@ -649,17 +653,20 @@ static void cpsw_slave_update_link(struct cpsw_slave *slave, __raw_writel(mac_control, &slave->sliver->mac_control); slave->mac_control = mac_control; + +out: + return ret; } static int cpsw_update_link(struct cpsw_priv *priv) { - int link = 0; + int ret = -ENODEV; struct cpsw_slave *slave; for_active_slave(slave, priv) - cpsw_slave_update_link(slave, priv, &link); + ret = cpsw_slave_update_link(slave, priv, NULL); - return link; + return ret; } static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) @@ -822,7 +829,9 @@ static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) for_active_slave(slave, priv) cpsw_slave_init(slave, priv); - cpsw_update_link(priv); + ret = cpsw_update_link(priv); + if (ret) + goto out; /* init descriptor pool */ for (i = 0; i < NUM_DESCS; i++) { @@ -897,7 +906,8 @@ static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) } } - return 0; +out: + return ret; } static void _cpsw_halt(struct cpsw_priv *priv) -- 2.9.0

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[U-Boot] [PATCH v2] net: macb: Fix GMAC not work when enable DM_ETH
by Wenyou Yang 02 Jun '17

02 Jun '17

Always search the PHY to determine the macb->phy_addr before using the PHY to fix "No PHY present" error. Fix the wrong test of the GMAC's phy interface mode, it should be PHY_INTERFACE_MODE_RGMII. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Fix the wrong missed RMII phy interface mode. - Add Reviewed-by tag. drivers/net/macb.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 402e866817..8e9b38f34f 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -447,7 +447,6 @@ static void macb_phy_reset(struct macb_device *macb, const char *name) name, status); } -#ifdef CONFIG_MACB_SEARCH_PHY static int macb_phy_find(struct macb_device *macb, const char *name) { int i; @@ -468,7 +467,6 @@ static int macb_phy_find(struct macb_device *macb, const char *name) return 0; } -#endif /* CONFIG_MACB_SEARCH_PHY */ #ifdef CONFIG_DM_ETH static int macb_phy_init(struct udevice *dev, const char *name) @@ -488,11 +486,9 @@ static int macb_phy_init(struct macb_device *macb, const char *name) int i; arch_get_mdio_control(name); -#ifdef CONFIG_MACB_SEARCH_PHY /* Auto-detect phy_addr */ if (!macb_phy_find(macb, name)) return 0; -#endif /* CONFIG_MACB_SEARCH_PHY */ /* Check if the PHY is up to snuff... */ phy_id = macb_mdio_read(macb, MII_PHYSID1); @@ -667,7 +663,8 @@ static int _macb_init(struct macb_device *macb, const char *name) * to select interface between RMII and MII. */ #ifdef CONFIG_DM_ETH - if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) + if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) || + (macb->phy_interface == PHY_INTERFACE_MODE_RGMII)) gem_writel(macb, UR, GEM_BIT(RGMII)); else gem_writel(macb, UR, 0); -- 2.11.0

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[U-Boot] [PATCH] arm64: mvebu: armada-7040-db: Enable 10GB port 0 / SFI (KR)
by Stefan Roese 02 Jun '17

02 Jun '17

This patch enables the mvpp2 port 0 usage on the Armada 7k DB by setting the correct PHY type (KR / SFI) for the COMPHY driver and enabling the ethernet0 device node in the dts. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Stefan Chulski <stefanc(a)marvell.com> Cc: Kostya Porotchkin <kostap(a)marvell.com> Cc: Nadav Haklai <nadavh(a)marvell.com> --- arch/arm/dts/armada-7040-db.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 84e0dbdc3d..54b888ac22 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -168,8 +168,7 @@ }; phy2 { - phy-type = <PHY_TYPE_SGMII0>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <PHY_TYPE_KR>; }; phy3 { @@ -223,6 +222,11 @@ status = "okay"; }; +&cpm_eth0 { + status = "okay"; + phy-mode = "sfi"; /* lane-2 */ +}; + &cpm_eth1 { status = "okay"; phy = <&phy0>; -- 2.12.2

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[U-Boot] [PATCH 0/2] armv8/ls104xa: add Tx internal delays for the RGMII PHYs
by Madalin Bucur 02 Jun '17

02 Jun '17

The RGMII PHYs used by the ls1043ardb/ls1046ardb boards require internal delay on Tx. Changing the fix-up code to reflect this. Madalin Bucur (2): armv8/ls1043a: RGMII PHY requires internal delay on Tx armv8/ls1046a: RGMII PHY requires internal delay on Tx drivers/net/fm/ls1043.c | 4 ++-- drivers/net/fm/ls1046.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) -- 2.1.0

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[U-Boot] [PATCHv2] net: zynq_gem: Do not return -ENOSYS on success
by Olliver Schinagl 02 Jun '17

02 Jun '17

The .read_rom_hwaddr net_ops hook does not check the return value, which is why it was never caught that we are currently returning 0 if the read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise. In this case we can simplify this by just returning the result of the function. Signed-off-by: Olliver Schinagl <oliver(a)schinagl.nl> --- Changes since v1: Check pdata for NULL before dereferencing. drivers/net/zynq_gem.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 86dd03feda..52beedfad0 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -589,14 +589,12 @@ __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) static int zynq_gem_read_rom_mac(struct udevice *dev) { - int retval; struct eth_pdata *pdata = dev_get_platdata(dev); - retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); - if (retval == -ENOSYS) - retval = 0; + if (!pdata) + return -ENOSYS; - return retval; + return zynq_board_read_rom_ethaddr(pdata->enetaddr); } static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, -- 2.11.0

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[U-Boot] [PATCH v2] net: designware: Add phy supply support
by Jacob Chen 02 Jun '17

02 Jun '17

Some board need a regulator for gmac phy, so add this code to handle it. Signed-off-by: Jacob Chen <jacob2.chen(a)rock-chips.com> --- drivers/net/designware.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index f9fb8e0..0fcd125 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -18,6 +18,7 @@ #include <linux/compiler.h> #include <linux/err.h> #include <asm/io.h> +#include <power/regulator.h> #include "designware.h" DECLARE_GLOBAL_DATA_PTR; @@ -661,6 +662,22 @@ int designware_eth_probe(struct udevice *dev) ulong ioaddr; int ret; +#if defined(CONFIG_DM_REGULATOR) + struct udevice *phy_supply; + + ret = device_get_supply_regulator(dev, "phy-supply", + &phy_supply); + if (ret) { + debug("%s: No phy supply\n", dev->name); + } else { + ret = regulator_set_enable(phy_supply, true); + if (ret) { + puts("Error enabling phy supply\n"); + return ret; + } + } +#endif + #ifdef CONFIG_DM_PCI /* * If we are on PCI bus, either directly attached to a PCI root port, -- 1.9.1

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[U-Boot] [PATCH v3] net: Kconfig:make PHY_GIGE and individual Micrel PHYs selectable
by Philipp Tomsich 02 Jun '17

02 Jun '17

This change migrate the following configuration options for Kconfig: * PHY_GIGE, indicates that a controller (with an appropriate PHY) is Gigabit capable and enables extra support in the miiutil for parsing the status of Gigabit PHYs * adds configuration options for Micrel KSZ9021 and KSZ9031 GbE PHYs, which previously had to enabled through a board-specific config file Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- Changes in v3: - add a label to the PHY_GIGE option to make it selectable via menuconf - automatically select PHY_GIGE when a KSZ9021 or KSZ9031 is selected - fix indentations (convert spaces to tabs) - adds help text for PHY_MICREL Changes in v2: - migrate PHY_GIGE to Kconfig drivers/net/Kconfig | 8 ++++++++ drivers/net/phy/Kconfig | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 70e3661..653ee5a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -22,6 +22,13 @@ menuconfig NETDEVICES if NETDEVICES +config PHY_GIGE + bool "Enable GbE PHY status parsing and configuration" + help + Enables support for parsing the status output and for + configuring GbE PHYs (affects the inner workings of some + commands and miiphyutil.c). + config AG7XXX bool "Atheros AG7xxx Ethernet MAC support" depends on DM_ETH && ARCH_ATH79 @@ -165,6 +172,7 @@ config SUN8I_EMAC bool "Allwinner Sun8i Ethernet MAC support" depends on DM_ETH select PHYLIB + select PHY_GIGE help This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. It can be found in H3/A64/A83T based SoCs and compatible with both diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 1d514e9..e2dfd88 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -44,6 +44,40 @@ config PHY_MARVELL config PHY_MICREL bool "Micrel Ethernet PHYs support" + help + Enable support for the GbE PHYs manufactured by Micrel (now + a part of Microchip). This includes drivers for the KSZ804, + KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, KSZ8721 + either/or KSZ9021 (see the "Micrel KSZ9021 family support" + config option for details), and KSZ9031 (if configured). + +if PHY_MICREL + +config PHY_MICREL_KSZ9021 + bool "Micrel KSZ9021 family support" + select PHY_GIGE + help + Enable support for the Micrel KSZ9021 GbE PHY family. If + enabled, the extended register read/write for KSZ9021 PHYs + is supported through the 'mdio' command and any RGMII signal + delays configured in the device tree will be applied to the + PHY during initialisation. + + Note that the KSZ9021 uses the same part number os the + KSZ8921BL, so enabling this option disables support for the + KSZ8721BL. + +config PHY_MICREL_KSZ9031 + bool "Micrel KSZ9031 family support" + select PHY_GIGE + help + Enable support for the Micrel KSZ9031 GbE PHY family. If + enabled, the extended register read/write for KSZ9021 PHYs + is supported through the 'mdio' command and any RGMII signal + delays configured in the device tree will be applied to the + PHY during initialisatioin. + +endif # PHY_MICREL config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" -- 1.9.1

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