June 2017 - U-Boot

[U-Boot] [PATCH 1/3] regulator: lp87565: Fix the return value of buck_get_enable function
by Keerthy 15 Jun '17

15 Jun '17

The function wrongly returned an integer while it is supposed to return boolean. Fix that. Fixes: 2dd9dc02a3("power: regulator: lp87565: add regulator support") Reported-by: Nishanth Menon <nm(a)ti.com> Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- drivers/power/regulator/lp87565_regulator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/lp87565_regulator.c b/drivers/power/regulator/lp87565_regulator.c index 2a0b8ca..e5de578 100644 --- a/drivers/power/regulator/lp87565_regulator.c +++ b/drivers/power/regulator/lp87565_regulator.c @@ -174,7 +174,7 @@ static bool buck_get_enable(struct udevice *dev) ret = lp87565_buck_enable(dev, PMIC_OP_GET, &enable); if (ret) - return ret; + return false; return enable; } -- 1.9.1

3 8

[U-Boot] [PATCH v1] rockchip: video: mipi: Modify format type for debug message
by Eric Gao 15 Jun '17

15 Jun '17

Modify format type for debug message. Signed-off-by: Eric Gao <eric.gao(a)rock-chips.com> --- drivers/video/rockchip/rk_mipi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index af7656e..e0bfecf 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -437,14 +437,14 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (priv->grf <= 0) { - debug("%s: Get syscon grf failed (ret=%llu)\n", - __func__, (u64)priv->grf); + debug("%s: Get syscon grf failed (ret=%p)\n", + __func__, priv->grf); return -ENXIO; } priv->regs = (void *)devfdt_get_addr(dev); if (priv->regs <= 0) { - debug("%s: Get MIPI dsi address failed (ret=%llu)\n", __func__, - (u64)priv->regs); + debug("%s: Get MIPI dsi address failed (ret=%p)\n", __func__, + priv->regs); return -ENXIO; } -- 1.9.1

2 1

[U-Boot] [PATCH v1] rockchip: video: mipi: Modify variable type for arm32 compatibility
by Eric Gao 15 Jun '17

15 Jun '17

Some address relevant varibable is defined originally as u64. To compatible with arm32, this patch change them to "void __iomem *" type. Signed-off-by: Eric Gao <eric.gao(a)rock-chips.com> --- drivers/video/rockchip/rk_mipi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index ad00397..af7656e 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -76,13 +76,13 @@ static int rk_mipi_read_timing(struct udevice *dev, * use define in rk_mipi.h directly for this parameter * @val: value that will be write to specified bits of register */ -static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val) +static void rk_mipi_dsi_write(void __iomem *regs, u32 reg, u32 val) { u32 dat; u32 mask; u32 offset = (reg >> OFFSET_SHIFT) & 0xff; u32 bits = (reg >> BITS_SHIFT) & 0xff; - u64 addr = (reg >> ADDR_SHIFT) + regs; + void __iomem *addr = (reg >> ADDR_SHIFT) + regs; /* Mask for specifiled bits,the corresponding bits will be clear */ mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); @@ -108,7 +108,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, int node, timing_node; int val; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + void __iomem *regs = priv->regs; struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); u32 txbyte_clk = priv->txbyte_clk; u32 txesc_clk = priv->txesc_clk; @@ -224,7 +224,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, } /* rk mipi dphy write function. It is used to write test data to dphy */ -static void rk_mipi_phy_write(u32 regs, unsigned char test_code, +static void rk_mipi_phy_write(void __iomem *regs, unsigned char test_code, unsigned char *test_data, unsigned char size) { int i = 0; @@ -253,7 +253,7 @@ static int rk_mipi_phy_enable(struct udevice *dev) { int i; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + void __iomem *regs = priv->regs; u64 fbdiv; u64 prediv = 1; u32 max_fbdiv = 512; -- 1.9.1

2 1

[U-Boot] U-boot Memory configure
by Péter Bittner 15 Jun '17

15 Jun '17

Hi all, I have a problem and i can't solve it. I have a costume IMX6 board. I want to make new memory configure file. I found this script: I.MX6DQSDL DDR3 Script Aid V0.10 and i set everything which need. It generated init script for the calibration. It's worked and didn't get any error. Then i modified this script for uboot memory config file and changed calibration data. But when i tried flash the board then Uboot don't start. this is the Uboot config file: IMAGE_VERSION 2 BOOT_FROM sd DATA 4 0x020c4068 0x00003fff DATA 4 0x020c406c 0x00f0fc00 DATA 4 0x020c4070 0x00fff000 DATA 4 0x020c4074 0x3ff00000 DATA 4 0x020c4078 0xff00f300 DATA 4 0x020c407c 0x0f0000c3 DATA 4 0x020c4080 0x000003ff DATA 4 0x020e0798 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE DATA 4 0x020e0588 0x00000018 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 DATA 4 0x020e0594 0x00000018 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL DATA 4 0x020e05a8 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DATA 4 0x020e05b0 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DATA 4 0x020e0524 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DATA 4 0x020e051c 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DATA 4 0x020e0518 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 DATA 4 0x020e050c 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 DATA 4 0x020e05b8 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 DATA 4 0x020e05c0 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 DATA 4 0x020e0534 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10) DATA 4 0x020e0538 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00) DATA 4 0x020e053c 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10) DATA 4 0x020e0540 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10) DATA 4 0x020e0544 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10) DATA 4 0x020e0548 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10) DATA 4 0x020e054c 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10) DATA 4 0x020e0550 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10) DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE DATA 4 0x020e0784 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B0DS DATA 4 0x020e0788 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B1DS DATA 4 0x020e0794 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B2DS DATA 4 0x020e079c 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B3DS DATA 4 0x020e07a0 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B4DS DATA 4 0x020e07a4 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B5DS DATA 4 0x020e07a8 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B6DS DATA 4 0x020e0748 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B7DS DATA 4 0x020e05ac 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 DATA 4 0x020e05b4 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 DATA 4 0x020e0528 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 DATA 4 0x020e0520 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 DATA 4 0x020e0514 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 DATA 4 0x020e0510 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 DATA 4 0x020e05bc 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 DATA 4 0x020e05c4 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 DATA 4 0x021b001c 0x00008000 //MMDC0_MDSCR, set the Configuration request bit during MMDC set up DATA 4 0x021b0800 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration. DATA 4 0x021b080c 0x000D000D DATA 4 0x021b0810 0x00150011 DATA 4 0x021b480c 0x00060015 DATA 4 0x021b4810 0x00000013 DATA 4 0x021b083c 0x0310031C // MPDGCTRL0 PHY0 DATA 4 0x021b0840 0x03080270 // MPDGCTRL1 PHY0 DATA 4 0x021b483c 0x03080320 // MPDGCTRL0 PHY1 DATA 4 0x021b4840 0x030C024C // MPDGCTRL1 PHY1 DATA 4 0x021b0848 0x42323A3A // MPRDDLCTL PHY0 DATA 4 0x021b4848 0x3C323044 // MPRDDLCTL PHY1 DATA 4 0x021b0850 0x30363832 // MPWRDLCTL PHY0 DATA 4 0x021b4850 0x3E2E4236 // MPWRDLCTL PHY1 DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3 DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3 DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3 DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3 DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3 DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3 DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3 DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3 DATA 4 0x021b08c0 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 DATA 4 0x021b48c0 0x24914452 DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr DATA 4 0x021b0004 0x00020036 // MMDC0_MDPDC DATA 4 0x021b0008 0x09444040 // MMDC0_MDOTC DATA 4 0x021b000c 0x898E7955 // MMDC0_MDCFG0 DATA 4 0x021b0010 0xFF328F64 // MMDC0_MDCFG1 DATA 4 0x021b0014 0x01FF00DB // MMDC0_MDCFG2 DATA 4 0x021b0018 0x00011740 // MMDC0_MDMISC DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up DATA 4 0x021b002c 0x000026D2 // MMDC0_MDRWD DATA 4 0x021b0030 0x008E1023 // MMDC0_MDOR DATA 4 0x021b0040 0x00000047 // Chan0 CS0_END DATA 4 0x021b0400 0x14420000 // adopt bypass DATA 4 0x021b0000 0x841A0000 // MMDC0_MDCTL DATA 4 0x021b0890 0x00400c58 //ZQ Offset DATA 4 0x00bb0008 0x00000000 // GPV0_S_A_0_DDRCONF DATA 4 0x00bb000c 0x2891E41A // GPV0_S_A_0_DDRTIMING accorindt to MMDC0_MDCFG0/1/2 DATA 4 0x00bb0038 0x00000564 // GPV0_S_A_0_Activate DATA 4 0x00bb0014 0x00000040 // Read latency DATA 4 0x00bb0028 0x00000020 // Aging control for IPU1/PRE0/PRE3 DATA 4 0x00bb002c 0x00000020 // Aging control for IPU2/PRE1/PRE2 DATA 4 0x021b001c 0x02088032 // MMDC0_MDSCR, MR2 write, CS0 DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR, MR3 write, CS0 DATA 4 0x021b001c 0x00408031 // MMDC0_MDSCR, MR1 write, CS0 DATA 4 0x021b001c 0x19408030 // MMDC0_MDSCR, MR0write, CS0 DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0 DATA 4 0x021b0020 0x00007800 // MMDC0_MDREF DATA 4 0x021b0818 0x00011117 // DDR_PHY_P0_MPODTCTRL DATA 4 0x021b4818 0x00011117 // DDR_PHY_P1_MPODTCTRL DATA 4 0x021b0004 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached. DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete) This is the calibration script //=================================================================== ========== //init script for i.Mx6Q DDR3 //============================================================================= // Revision History // v01 //============================================================================= wait = on //============================================================================= // Disable WDOG //============================================================================= setmem /16 0x020bc000 = 0x30 //============================================================================= // Enable all clocks (they are disabled by ROM code) //============================================================================= setmem /32 0x020c4068 = 0xffffffff setmem /32 0x020c406c = 0xffffffff setmem /32 0x020c4070 = 0xffffffff setmem /32 0x020c4074 = 0xffffffff setmem /32 0x020c4078 = 0xffffffff setmem /32 0x020c407c = 0xffffffff setmem /32 0x020c4080 = 0xffffffff setmem /32 0x020c4084 = 0xffffffff //============================================================================= // IOMUX //============================================================================= //DDR IO TYPE: setmem /32 0x020e0798 = 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE setmem /32 0x020e0758 = 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE //CLOCK: setmem /32 0x020e0588 = 0x00000018 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 setmem /32 0x020e0594 = 0x00000018 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 //ADDRESS: setmem /32 0x020e056c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS setmem /32 0x020e0578 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS setmem /32 0x020e074c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS //Control: setmem /32 0x020e057c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET setmem /32 0x020e058c = 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS setmem /32 0x020e059c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 setmem /32 0x020e05a0 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 setmem /32 0x020e078c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS //Data Strobes: setmem /32 0x020e0750 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL setmem /32 0x020e05a8 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 setmem /32 0x020e05b0 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 setmem /32 0x020e0524 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 setmem /32 0x020e051c = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 setmem /32 0x020e0518 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 setmem /32 0x020e050c = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 setmem /32 0x020e05b8 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 setmem /32 0x020e05c0 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 //Data: setmem /32 0x020e0774 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE setmem /32 0x020e0784 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B0DS setmem /32 0x020e0788 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B1DS setmem /32 0x020e0794 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B2DS setmem /32 0x020e079c = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B3DS setmem /32 0x020e07a0 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B4DS setmem /32 0x020e07a4 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B5DS setmem /32 0x020e07a8 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B6DS setmem /32 0x020e0748 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B7DS setmem /32 0x020e05ac = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 setmem /32 0x020e05b4 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 setmem /32 0x020e0528 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 setmem /32 0x020e0520 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 setmem /32 0x020e0514 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 setmem /32 0x020e0510 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 setmem /32 0x020e05bc = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 setmem /32 0x020e05c4 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 //============================================================================= // DDR Controller Registers //============================================================================= // Manufacturer: Micron // Device Part Number: MT41K128M16JT-125 // Clock Freq.: 528MHz // Density per CS in Gb: 16 // Chip Selects used: 1 // Number of Banks: 8 // Row address: 15 // Column address: 10 // Data bus width 64 //============================================================================= setmem /32 0x021b001c = 0x00008000 MMDC0_MDSCR, set the Configuration request bit during MMDC set up //============================================================================= // Calibration setup. //============================================================================= setmem /32 0x021b0800 = 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration. // For target board, may need to run write leveling calibration to fine tune these settings. setmem /32 0x021b080c = 0x00000000 setmem /32 0x021b0810 = 0x00000000 setmem /32 0x021b480c = 0x00000000 setmem /32 0x021b4810 = 0x00000000 ////Read DQS Gating calibration setmem /32 0x021b083c = 0x00000000 // MPDGCTRL0 PHY0 setmem /32 0x021b0840 = 0x00000000 // MPDGCTRL1 PHY0 setmem /32 0x021b483c = 0x00000000 // MPDGCTRL0 PHY1 setmem /32 0x021b4840 = 0x00000000 // MPDGCTRL1 PHY1 //Read calibration setmem /32 0x021b0848 = 0x40404040 // MPRDDLCTL PHY0 setmem /32 0x021b4848 = 0x40404040 // MPRDDLCTL PHY1 //Write calibration setmem /32 0x021b0850 = 0x40404040 // MPWRDLCTL PHY0 setmem /32 0x021b4850 = 0x40404040 // MPWRDLCTL PHY1 //read data bit delay: (3 is the reccommended default value, although out of reset value is 0) setmem /32 0x021b081c = 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3 setmem /32 0x021b0820 = 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3 setmem /32 0x021b0824 = 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3 setmem /32 0x021b0828 = 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3 setmem /32 0x021b481c = 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3 setmem /32 0x021b4820 = 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3 setmem /32 0x021b4824 = 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3 setmem /32 0x021b4828 = 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3 //For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented //setmem /32 0x021b08c0 = 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 //setmem /32 0x021b48c0 = 0x24911492 // Complete calibration by forced measurement: setmem /32 0x021b08b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr setmem /32 0x021b48b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr //============================================================================= // Calibration setup end //============================================================================= //MMDC init: setmem /32 0x021b0004 = 0x00020036 // MMDC0_MDPDC setmem /32 0x021b0008 = 0x09444040 // MMDC0_MDOTC setmem /32 0x021b000c = 0x54597955 // MMDC0_MDCFG0 setmem /32 0x021b0010 = 0xFF328F64 // MMDC0_MDCFG1 setmem /32 0x021b0014 = 0x01FF00DB // MMDC0_MDCFG2 //MDMISC: RALAT kept to the high level of 5. //MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: //a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 //b. Small performence improvment setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC setmem /32 0x021b001c = 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up setmem /32 0x021b002c = 0x000026D2 // MMDC0_MDRWD setmem /32 0x021b0030 = 0x00591023 // MMDC0_MDOR setmem /32 0x021b0040 = 0x00000047 // Chan0 CS0_END setmem /32 0x021b0000 = 0x841A0000 // MMDC0_MDCTL //Mode register writes setmem /32 0x021b001c = 0x02088032 // MMDC0_MDSCR, MR2 write, CS0 setmem /32 0x021b001c = 0x00008033 // MMDC0_MDSCR, MR3 write, CS0 setmem /32 0x021b001c = 0x00408031 // MMDC0_MDSCR, MR1 write, CS0 setmem /32 0x021b001c = 0x19408030 // MMDC0_MDSCR, MR0write, CS0 setmem /32 0x021b001c = 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0 //setmem /32 0x021b001c = 0x0208803A // MMDC0_MDSCR, MR2 write, CS1 //setmem /32 0x021b001c = 0x0000803B // MMDC0_MDSCR, MR3 write, CS1 //setmem /32 0x021b001c = 0x00408039 // MMDC0_MDSCR, MR1 write, CS1 //setmem /32 0x021b001c = 0x19408038 // MMDC0_MDSCR, MR0write, CS1 //setmem /32 0x021b001c = 0x04008048 // MMDC0_MDSCR, ZQ calibration command sent to device on CS1 setmem /32 0x021b0020 = 0x00007800 // MMDC0_MDREF setmem /32 0x021b0818 = 0x00011117 // DDR_PHY_P0_MPODTCTRL setmem /32 0x021b4818 = 0x00011117 // DDR_PHY_P1_MPODTCTRL setmem /32 0x021b0004 = 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled setmem /32 0x021b0404 = 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached. setmem /32 0x021b001c = 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete) PS.: sorry for my English regards, Péter

1 0

[U-Boot] Please pull u-boot-mpc85xx master
by York Sun 15 Jun '17

15 Jun '17

Tom, The following changes since commit 8cb3ce64f936f5dedbcfc1935c5caf31bb682474: Merge git://git.denx.de/u-boot-dm (2017-06-10 18:01:22 -0400) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git for you to fetch changes up to 1079af4817b562e176259c2beadb67ef0d046d91: powerpc: fsl: Update maintainers (2017-06-12 12:18:37 -0700) ---------------------------------------------------------------- York Sun (16): powerpc: mpc8540ads: mpc8560ads: Drop support for MPC8540/60ADS powerpc: mpc85xx: Update maintainer for MPC8541CDS and MPC8555CDS powerpc: mpc86xx: Update maintainer for MPC8610HPCD and MPC8641HPCN powerpc: mpc8536ds: Enable DHCP command by default driver: ddr: fsl: Fix compiling error for DDR2 powerpc: mpc8641hpcn: Enable DHCP command and DDR debug net: phy: marvell: Fix init function for m88e1145 powerpc: mpc8548cds: Update maintainer powerpc: mpc8548cds: Enable DHCP command by default powerpc: mpc8544ds: Enable DHCP command by default powerpc: mpc8544ds: Fix environmental variable location powerpc: mpc8544ds: Update maintainer powerpc: mpc8536ds: Update maintainer powerpc: mpc8568mds: Update board config powerpc: mpc8569mds: Update config and maintainer powerpc: fsl: Update maintainers arch/powerpc/cpu/mpc85xx/Kconfig | 10 - board/freescale/b4860qds/MAINTAINERS | 2 +- board/freescale/mpc8536ds/MAINTAINERS | 2 +- board/freescale/mpc8540ads/Kconfig | 12 - board/freescale/mpc8540ads/MAINTAINERS | 6 - board/freescale/mpc8540ads/Makefile | 11 - board/freescale/mpc8540ads/ddr.c | 44 --- board/freescale/mpc8540ads/law.c | 42 --- board/freescale/mpc8540ads/mpc8540ads.c | 242 ----------------- board/freescale/mpc8540ads/tlb.c | 95 ------- board/freescale/mpc8541cds/MAINTAINERS | 4 +- board/freescale/mpc8544ds/MAINTAINERS | 2 +- board/freescale/mpc8548cds/MAINTAINERS | 2 +- board/freescale/mpc8555cds/MAINTAINERS | 4 +- board/freescale/mpc8560ads/Kconfig | 12 - board/freescale/mpc8560ads/MAINTAINERS | 6 - board/freescale/mpc8560ads/Makefile | 11 - board/freescale/mpc8560ads/ddr.c | 44 --- board/freescale/mpc8560ads/law.c | 42 --- board/freescale/mpc8560ads/mpc8560ads.c | 462 -------------------------------- board/freescale/mpc8560ads/tlb.c | 95 ------- board/freescale/mpc8568mds/MAINTAINERS | 2 +- board/freescale/mpc8569mds/MAINTAINERS | 2 +- board/freescale/mpc8610hpcd/MAINTAINERS | 2 +- board/freescale/mpc8641hpcn/MAINTAINERS | 4 +- board/freescale/p1010rdb/MAINTAINERS | 2 +- board/freescale/p1_twr/MAINTAINERS | 2 +- board/freescale/t104xrdb/MAINTAINERS | 4 +- configs/MPC8536DS_36BIT_defconfig | 1 + configs/MPC8536DS_defconfig | 1 + configs/MPC8540ADS_defconfig | 15 -- configs/MPC8544DS_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8560ADS_defconfig | 14 - configs/MPC8568MDS_defconfig | 1 + configs/MPC8569MDS_ATM_defconfig | 1 + configs/MPC8569MDS_defconfig | 1 + configs/MPC8641HPCN_defconfig | 1 + doc/README.mpc85xxads | 301 --------------------- drivers/ddr/fsl/interactive.c | 4 + drivers/net/phy/marvell.c | 5 +- include/configs/MPC8544DS.h | 4 +- include/configs/MPC8568MDS.h | 6 +- include/configs/MPC8641HPCN.h | 2 +- 45 files changed, 40 insertions(+), 1488 deletions(-) delete mode 100644 board/freescale/mpc8540ads/Kconfig delete mode 100644 board/freescale/mpc8540ads/MAINTAINERS delete mode 100644 board/freescale/mpc8540ads/Makefile delete mode 100644 board/freescale/mpc8540ads/ddr.c delete mode 100644 board/freescale/mpc8540ads/law.c delete mode 100644 board/freescale/mpc8540ads/mpc8540ads.c delete mode 100644 board/freescale/mpc8540ads/tlb.c delete mode 100644 board/freescale/mpc8560ads/Kconfig delete mode 100644 board/freescale/mpc8560ads/MAINTAINERS delete mode 100644 board/freescale/mpc8560ads/Makefile delete mode 100644 board/freescale/mpc8560ads/ddr.c delete mode 100644 board/freescale/mpc8560ads/law.c delete mode 100644 board/freescale/mpc8560ads/mpc8560ads.c delete mode 100644 board/freescale/mpc8560ads/tlb.c delete mode 100644 configs/MPC8540ADS_defconfig delete mode 100644 configs/MPC8560ADS_defconfig delete mode 100644 doc/README.mpc85xxads Thanks. York

2 1

[U-Boot] Pull request, u-boot-tegra/master
by Tom Warren 15 Jun '17

15 Jun '17

Tom, Please pull u-boot-tegra/master into U-Boot/master. Thanks! All Tegra builds are OK, and Stephen's automated test system reports that all tests pass. The following changes since commit 8cb3ce64f936f5dedbcfc1935c5caf31bb682474: Merge git://git.denx.de/u-boot-dm (2017-06-10 18:01:22 -0400) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to 2eb3e28b2c69261d274bc22321f688c193985e7b: ARM: tegra: remove Whistler support (2017-06-12 13:03:50 -0700) ---------------------------------------------------------------- Stephen Warren (1): ARM: tegra: remove Whistler support arch/arm/dts/Makefile | 1 - arch/arm/dts/tegra20-whistler.dts | 77 ----------------------------------- arch/arm/mach-tegra/tegra20/Kconfig | 5 --- board/nvidia/whistler/Kconfig | 12 ------ board/nvidia/whistler/MAINTAINERS | 7 ---- board/nvidia/whistler/Makefile | 8 ---- board/nvidia/whistler/whistler.c | 80 ------------------------------------- configs/whistler_defconfig | 29 -------------- include/configs/whistler.h | 49 ----------------------- 9 files changed, 268 deletions(-) delete mode 100644 arch/arm/dts/tegra20-whistler.dts delete mode 100644 board/nvidia/whistler/Kconfig delete mode 100644 board/nvidia/whistler/MAINTAINERS delete mode 100644 board/nvidia/whistler/Makefile delete mode 100644 board/nvidia/whistler/whistler.c delete mode 100644 configs/whistler_defconfig delete mode 100644 include/configs/whistler.h

2 1

[U-Boot] [PATCH v2] sun50i: h5: Add initial NanoPi NEO2 support
by Jagan Teki 14 Jun '17

14 Jun '17

From: Jagan Teki <jagan(a)amarulasolutions.com> NanoPi M1 Plus is designed and developed by FriendlyElec using the Allwinner 64-bit H5 SOC. NanoPi Neo2 key features - Allwinner H5, Quad-core 64-bit Cortex-A53 - 512MB DDR3 RAM - microSD slot - 10/100/1000M Ethernet - Serial Debug Port - 5V 2A DC MicroUSB power-supply Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> Tested-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v2: - Droped memory node - Remove /soc under regulator - Tested on neo2 arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h5-nanopi-neo2.dts | 86 ++++++++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 ++ configs/nanopi_neo2_defconfig | 16 +++++++ 4 files changed, 108 insertions(+) create mode 100644 arch/arm/dts/sun50i-h5-nanopi-neo2.dts create mode 100644 configs/nanopi_neo2_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a6eab75..5d7432f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -319,6 +319,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ sun8i-v3s-licheepi-zero.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-nanopi-neo2.dtb \ sun50i-h5-orangepi-pc2.dtb \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts new file mode 100644 index 0000000..c08af78 --- /dev/null +++ b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2017 Icenowy Zheng <icenowy(a)aosc.io> + * Copyright (C) 2017 Jagan Teki <jteki(a)openedev.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-h5.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "FriendlyARM NanoPi NEO 2"; + compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 77d8d17..e9f3e35 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -257,6 +257,11 @@ M: Jelle van der Waa <jelle(a)vdwaa.nl> S: Maintained F: configs/nanopi_neo_defconfig +NANOPI-NEO2 BOARD +M: Jagan Teki <jagan(a)amarulasolutions.com> +S: Maintained +F: configs/nanopi_neo2_defconfig + NANOPI-NEO-AIR BOARD M: Jelle van der Waa <jelle(a)vdwaa.nl> S: Maintained diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig new file mode 100644 index 0000000..c0ac100 --- /dev/null +++ b/configs/nanopi_neo2_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_DRAM_CLK=672 +CONFIG_DRAM_ZQ=3881977 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y -- 2.7.4

2 1

Re: [U-Boot] [PATCH v1 1/3] powerpc, 8xx: remove support for 8xx
by Christophe LEROY 14 Jun '17

14 Jun '17

Le 13/06/2017 à 07:26, Christophe LEROY a écrit : > There was for long time no activity in the 8xx area. > We need to go further and convert to Kconfig, but it > turned out, nobody is interested anymore in 8xx, > so remove it (with a heavy heart, knowing that I remove > here the root of U-Boot). > > Signed-off-by: Heiko Schocher <hs(a)denx.de> > Please don't do that. As you can see in Linux kernel activity, there have been a lot activity related to the 8xx, including but not limited to: 1/ HW Crypto for the 885 (Talitos SEC1) 2/ TX NAPI in the 8xx Ethernet driver 3/ Scatter/Gather support in the 8xx Ethernet driver 4/ Hugepages 5/ Perf events 6/ hw breakpoints 7/ Linear memory mapping via Large TLBs The followings links give an overview of the activity: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/log… https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/log… https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/log… https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/log… We have thousands of boards with mpc885 running and requiring support for at least the next 10 years. How can the 8xx survive without U-boot support ? Christophe

3 5

[U-Boot] [PATCH] ARM: fixed relocation using proper alignment
by Manfred Schlaegl 14 Jun '17

14 Jun '17

Using u-boot-2017.05 on i.MX6UL we ran into following problem: Initially U-Boot could be started normally. If we added one random command in configuration, the newly generated image hung at startup (last output was DRAM: 256 MiB). We tracked this down to a data abort within relocation (relocated_code). relocated_code in arch/arm/lib/relocate.S copies 8 bytes per loop iteration until the source pointer is equal to __image_copy_end. In a good case __image_copy_end was aligned to 8 bytes, so the loop stopped as suggested, but in an errornous case __image_copy_end was not aligned to 8 bytes, so the loop ran out of bounds and caused a data abort exception. This patches solves the issue by aligning __image_copy_end to 8 byte using the linker script related to arm. I don't know if it's the correct way to solve this, so some review would be very appreciated. --- arch/arm/cpu/u-boot.lds | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 37d4c60..70bee1a 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -165,7 +165,7 @@ SECTIONS *(.__efi_runtime_rel_stop) } - . = ALIGN(4); + . = ALIGN(8); .image_copy_end : { -- 2.1.4

6 15

[U-Boot] [PATCH 00/29] dm: scsi: Enhance SCSI support for driver model
by Simon Glass 14 Jun '17

14 Jun '17

At present U-Boot has a SCSI uclass but it does not have any operations. The global scsi_exec() function is still used to execute SCSI commands. This series tidies this up with the following changes: - Move CONFIG_SCSI and CONFIG_CMD_SATA to use Kconfig - Move SCSI and SATA code into separate drivers/ directories - Add operations to the SCSI uclass - Add driver-model support to AHCI - Move link over to use CONFIG_DM_SCSI - Drops an old SCSI driver for a single board that will likely be removed More work is still needed, such as adding operations to the AHCI uclass, but from what I can tell this can be done as a separate step. Simon Glass (29): configs: Resync with savedefconfig Convert CONFIG_SCSI to Kconfig scsi: Drop sym53c8xx driver scsi: Drop scsi_print_error() Convert CONFIG_CMD_SATA to Kconfig Kconfig: Add CONFIG_SATA to enable SATA sata: Move drivers into new drivers/ata directory scsi: Move drivers into new drivers/scsi directory dm: scsi: Rearrange header file for driver model dm: scsi: Rename struct SCSI_cmd_block to struct scsi_cmd dm: scsi: Drop the ccb typedef dm: scsi: Use the uclass platform data dm: ahci: Rename struct ahci_probe_ent dm: sata: Move ataid into struct ahci_uc_priv dm: ahci: Refactor to avoid static variables dm: scsi: Indent the confusing #ifdefs dm: ahci: Move common code for starting ports into a function dm: ahci: Unwind the confusing init code dm: ahci: Drop use of probe_ent dm: scsi: Add operations dm: scsi: Add a device pointer to scan_exec(), scsi_bus_reset() dm: scsi: Document and rename the scsi_scan() parameter dm: ahci: Create a local version of two SCSI functions dm: scsi: Add operations for SCSI devices dm: scsi: Adjust return value of scsi_exec() dm: scsi: Split out the bus scanning code dm: ahci: Add a driver for SCSI on AHCI dm: scsi: Drop scsi_init() when driver model is used RFC: x86: Move link to use driver model for SCSI README | 6 - api/api_storage.c | 2 +- arch/Kconfig | 2 + arch/arm/Kconfig | 10 + arch/arm/cpu/armv7/ls102xa/Kconfig | 1 + arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 2 +- arch/arm/cpu/armv7/mx6/Kconfig | 4 + arch/arm/cpu/armv7/mx6/clock.c | 6 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 +- arch/arm/imx-common/Makefile | 2 +- arch/arm/imx-common/cpu.c | 2 +- arch/arm/include/asm/arch-ls102xa/config.h | 1 - arch/arm/mach-mvebu/Kconfig | 4 + arch/arm/mach-omap2/omap5/Kconfig | 2 + arch/arm/mach-omap2/sata.c | 4 +- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc85xx/Kconfig | 46 ++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 +- arch/powerpc/cpu/mpc86xx/Kconfig | 1 + arch/x86/cpu/ivybridge/sata.c | 38 +- board/advantech/dms-ba16/dms-ba16.c | 2 +- board/bachmann/ot1200/ot1200.c | 2 +- board/boundary/nitrogen6x/nitrogen6x.c | 2 +- board/congatec/Kconfig | 1 + board/congatec/cgtqmx6eval/cgtqmx6eval.c | 2 +- board/dfi/Kconfig | 1 + board/gateworks/gw_ventana/gw_ventana.c | 2 +- board/highbank/ahci.c | 2 +- board/highbank/highbank.c | 2 +- board/kosagi/novena/novena.c | 2 +- board/mpl/pip405/README | 5 +- board/toradex/apalis_imx6/apalis_imx6.c | 2 +- board/toradex/colibri_imx6/colibri_imx6.c | 2 +- board/udoo/udoo.c | 2 +- board/wandboard/wandboard.c | 2 +- cmd/Kconfig | 13 + cmd/scsi.c | 6 +- common/Makefile | 5 - common/spl/spl_sata.c | 2 +- common/splash_source.c | 2 +- common/usb_storage.c | 44 +- configs/A10-OLinuXino-Lime_defconfig | 1 + configs/A20-OLinuXino-Lime2_defconfig | 1 + configs/A20-OLinuXino-Lime_defconfig | 1 + configs/A20-OLinuXino_MICRO_defconfig | 1 + configs/A20-Olimex-SOM-EVB_defconfig | 1 + configs/Bananapi_M2_Ultra_defconfig | 1 + configs/Bananapi_defconfig | 1 + configs/Bananapro_defconfig | 1 + configs/Cubieboard2_defconfig | 1 + configs/Cubieboard_defconfig | 1 + configs/Cubietruck_defconfig | 1 + configs/Itead_Ibox_A20_defconfig | 1 + configs/Lamobo_R1_defconfig | 1 + configs/Linksprite_pcDuino3_Nano_defconfig | 1 + configs/Linksprite_pcDuino3_defconfig | 1 + configs/MPC8315ERDB_defconfig | 1 + configs/MPC8349ITX_LOWBOOT_defconfig | 1 + configs/MPC8349ITX_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/MPC8544DS_defconfig | 1 + configs/MPC8610HPCD_defconfig | 1 + configs/Marsboard_A10_defconfig | 1 + configs/Mele_A1000_defconfig | 1 + configs/Mele_M5_defconfig | 1 + configs/Orangepi_defconfig | 1 + configs/Orangepi_mini_defconfig | 1 + configs/Sinovoip_BPI_M2_Plus_defconfig | 1 - configs/UCP1020_SPIFLASH_defconfig | 2 +- configs/UCP1020_defconfig | 2 +- configs/Wits_Pro_A20_DKT_defconfig | 1 + configs/adp-ae3xx_defconfig | 6 +- configs/adp-ag101p_defconfig | 6 +- configs/am335x_baltos_defconfig | 4 +- configs/am335x_boneblack_vboot_defconfig | 1 - configs/am335x_evm_defconfig | 1 - configs/am335x_hs_evm_defconfig | 4 - configs/am335x_igep003x_defconfig | 6 +- configs/am335x_shc_defconfig | 4 +- configs/am335x_shc_ict_defconfig | 4 +- configs/am335x_shc_netboot_defconfig | 4 +- configs/am335x_shc_prompt_defconfig | 4 +- configs/am335x_shc_sdboot_defconfig | 4 +- configs/am335x_shc_sdboot_prompt_defconfig | 4 +- configs/am335x_sl50_defconfig | 4 +- configs/am43xx_evm_defconfig | 3 +- configs/am43xx_evm_usbhost_boot_defconfig | 1 - configs/am43xx_hs_evm_defconfig | 3 +- configs/am57xx_evm_defconfig | 5 +- configs/am57xx_hs_evm_defconfig | 5 +- configs/at91sam9263ek_norflash_boot_defconfig | 2 +- configs/at91sam9263ek_norflash_defconfig | 2 +- configs/bayleybay_defconfig | 1 + configs/bcm958622hr_defconfig | 2 +- configs/birdland_bav335a_defconfig | 2 +- configs/birdland_bav335b_defconfig | 2 +- configs/blanche_defconfig | 1 - configs/brppt1_mmc_defconfig | 2 +- configs/brppt1_nand_defconfig | 2 +- configs/brppt1_spi_defconfig | 2 +- configs/brxre1_defconfig | 2 +- configs/canyonlands_defconfig | 1 + configs/cgtqmx6eval_defconfig | 1 + configs/chiliboard_defconfig | 4 +- configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 3 + configs/chromebook_minnie_defconfig | 2 +- configs/chromebook_samus_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/clearfog_defconfig | 2 - configs/cm_fx6_defconfig | 3 +- configs/cm_t335_defconfig | 2 +- configs/cm_t43_defconfig | 2 +- configs/cm_t54_defconfig | 1 + configs/colibri_imx7_defconfig | 2 +- configs/colibri_vf_defconfig | 2 +- configs/comtrend_ar5387un_ram_defconfig | 66 +- configs/comtrend_ct5361_ram_defconfig | 68 +- configs/comtrend_vr3032u_ram_defconfig | 66 +- .../controlcenterd_36BIT_SDCARD_DEVELOP_defconfig | 1 + configs/controlcenterd_36BIT_SDCARD_defconfig | 1 + configs/controlcenterdc_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/db-88f6820-gp_defconfig | 1 + configs/db-mv784mp-gp_defconfig | 1 + configs/dra7xx_evm_defconfig | 12 +- configs/dra7xx_hs_evm_defconfig | 9 +- configs/evb-ast2500_defconfig | 12 +- configs/evb-rk3399_defconfig | 5 +- configs/firefly-rk3399_defconfig | 1 - configs/gwventana_emmc_defconfig | 2 +- configs/gwventana_gw5904_defconfig | 2 +- configs/gwventana_nand_defconfig | 2 +- configs/highbank_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 67 +- configs/imx6qdl_icore_mmc_defconfig | 4 +- configs/imx6qdl_icore_rqs_mmc_defconfig | 2 +- configs/k2e_evm_defconfig | 5 +- configs/k2e_hs_evm_defconfig | 3 +- configs/k2g_evm_defconfig | 5 +- configs/k2g_hs_evm_defconfig | 6 +- configs/k2hk_evm_defconfig | 4 +- configs/k2hk_hs_evm_defconfig | 3 +- configs/k2l_evm_defconfig | 4 +- configs/ls1012aqds_qspi_defconfig | 1 + configs/ls2081ardb_defconfig | 14 +- configs/ls2088ardb_qspi_defconfig | 13 +- configs/m53evk_defconfig | 3 +- configs/minnowmax_defconfig | 1 + configs/mx51evk_defconfig | 2 +- configs/mx53cx9020_defconfig | 2 +- configs/mx53loco_defconfig | 3 +- configs/mx6cuboxi_defconfig | 2 +- configs/mx6qsabrelite_defconfig | 1 + configs/mx6sxsabresd_defconfig | 2 +- configs/mx6sxsabresd_spl_defconfig | 2 +- configs/mx7dsabresd_defconfig | 2 +- configs/nanopi_neo_air_defconfig | 2 +- configs/nanopi_neo_defconfig | 2 +- configs/netgear_cg3100d_ram_defconfig | 66 +- configs/nitrogen6q2g_defconfig | 1 + configs/nitrogen6q_defconfig | 1 + configs/novena_defconfig | 3 +- configs/omap3_logic_defconfig | 1 - configs/omap5_uevm_defconfig | 1 + configs/opos6uldev_defconfig | 2 +- configs/orangepi_2_defconfig | 1 - configs/orangepi_lite_defconfig | 1 - configs/orangepi_one_defconfig | 1 - configs/orangepi_pc2_defconfig | 1 - configs/orangepi_pc_defconfig | 1 - configs/orangepi_pc_plus_defconfig | 1 - configs/orangepi_plus2e_defconfig | 1 - configs/orangepi_plus_defconfig | 1 - configs/orangepi_zero_defconfig | 2 +- configs/pcm051_rev1_defconfig | 2 +- configs/pcm051_rev3_defconfig | 2 +- configs/pengwyn_defconfig | 2 +- configs/pepper_defconfig | 2 +- configs/pine64_plus_defconfig | 3 +- configs/puma-rk3399_defconfig | 1 - configs/pxm2_defconfig | 2 +- configs/r8a7795_salvator-x_defconfig | 19 +- configs/r8a7796_salvator-x_defconfig | 20 +- configs/rut_defconfig | 2 +- configs/sagem_f@st1704_ram_defconfig | 66 +- configs/sama5d2_xplained_mmc_defconfig | 4 +- configs/sama5d2_xplained_spiflash_defconfig | 2 +- configs/sandbox_defconfig | 9 +- configs/sandbox_flattree_defconfig | 11 +- configs/sandbox_noblk_defconfig | 5 +- configs/sandbox_spl_defconfig | 4 +- configs/sfr_nb4-ser_ram_defconfig | 66 +- configs/som-db5800-som-6867_defconfig | 1 + configs/stm32f746-disco_defconfig | 14 +- configs/tbs2910_defconfig | 3 +- configs/udoo_defconfig | 1 + configs/wandboard_defconfig | 1 + configs/xilinx_zynqmp_ep_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 2 +- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 2 +- configs/xilinx_zynqmp_zcu102_defconfig | 3 +- configs/xilinx_zynqmp_zcu102_revB_defconfig | 3 +- drivers/Kconfig | 4 + drivers/Makefile | 4 +- drivers/ata/Kconfig | 62 ++ drivers/ata/Makefile | 22 + drivers/{block => ata}/ahci-uclass.c | 0 drivers/{block => ata}/ahci.c | 390 ++++++---- drivers/{block => ata}/dwc_ahci.c | 10 +- drivers/{block => ata}/dwc_ahsata.c | 74 +- drivers/{block => ata}/dwc_ahsata.h | 0 drivers/{block => ata}/fsl_sata.c | 0 drivers/{block => ata}/fsl_sata.h | 0 drivers/{block => ata}/libata.c | 0 drivers/{block => ata}/mvsata_ide.c | 0 drivers/{block => ata}/mxc_ata.c | 0 {common => drivers/ata}/sata.c | 0 drivers/{block => ata}/sata_ceva.c | 9 +- drivers/{block => ata}/sata_dwc.c | 0 drivers/{block => ata}/sata_dwc.h | 0 drivers/{block => ata}/sata_mv.c | 0 drivers/{block => ata}/sata_sandbox.c | 0 drivers/{block => ata}/sata_sil.c | 0 drivers/{block => ata}/sata_sil.h | 0 drivers/{block => ata}/sata_sil3114.c | 0 drivers/{block => ata}/sata_sil3114.h | 0 drivers/block/Kconfig | 41 - drivers/block/Makefile | 17 +- drivers/block/scsi-uclass.c | 27 - drivers/block/sym53c8xx.c | 851 --------------------- drivers/scsi/Kconfig | 17 + drivers/scsi/Makefile | 19 + drivers/{block => scsi}/sandbox_scsi.c | 9 +- drivers/scsi/scsi-uclass.c | 40 + {common => drivers/scsi}/scsi.c | 147 ++-- drivers/usb/emul/sandbox_flash.c | 2 +- fs/fat/fat.c | 2 +- include/ahci.h | 60 +- include/config_cmd_all.h | 1 - include/config_distro_bootcmd.h | 6 +- include/config_fallbacks.h | 2 +- include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8349ITX.h | 4 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8544DS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P1022DS.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/P4080DS.h | 1 - include/configs/PIP405.h | 10 - include/configs/T102xQDS.h | 1 - include/configs/T1040QDS.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240QDS.h | 1 - include/configs/T4240RDB.h | 2 - include/configs/UCP1020.h | 1 - include/configs/advantech_dms-ba16.h | 1 - include/configs/am57xx_evm.h | 1 - include/configs/apalis_imx6.h | 4 - include/configs/canyonlands.h | 1 - include/configs/cgtqmx6eval.h | 1 - include/configs/cm_fx6.h | 1 - include/configs/cm_t54.h | 1 - include/configs/controlcenterd.h | 1 - include/configs/controlcenterdc.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/cyrus.h | 1 - include/configs/db-88f6820-gp.h | 1 - include/configs/db-mv784mp-gp.h | 1 - include/configs/dra7xx_evm.h | 1 - include/configs/efi-x86.h | 1 - include/configs/galileo.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/highbank.h | 1 - include/configs/ls1012aqds.h | 1 - include/configs/ls1012ardb.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1046aqds.h | 1 - include/configs/ls1046ardb.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/m53evk.h | 1 - include/configs/mvebu_armada-37xx.h | 1 - include/configs/mvebu_armada-8k.h | 1 - include/configs/mx53loco.h | 1 - include/configs/nitrogen6x.h | 4 - include/configs/novena.h | 1 - include/configs/omap5_uevm.h | 1 - include/configs/ot1200.h | 4 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/p1_twr.h | 1 - include/configs/qemu-x86.h | 1 - include/configs/sandbox.h | 2 - include/configs/sunxi-common.h | 1 - include/configs/t4qds.h | 1 - include/configs/tbs2910.h | 1 - include/configs/theadorable.h | 1 - include/configs/udoo.h | 1 - include/configs/wandboard.h | 1 - include/configs/x86-common.h | 1 - include/configs/xilinx_zynqmp.h | 1 - include/scsi.h | 85 +- scripts/config_whitelist.txt | 4 - 313 files changed, 1262 insertions(+), 1879 deletions(-) create mode 100644 drivers/ata/Kconfig create mode 100644 drivers/ata/Makefile rename drivers/{block => ata}/ahci-uclass.c (100%) rename drivers/{block => ata}/ahci.c (74%) rename drivers/{block => ata}/dwc_ahci.c (92%) rename drivers/{block => ata}/dwc_ahsata.c (92%) rename drivers/{block => ata}/dwc_ahsata.h (100%) rename drivers/{block => ata}/fsl_sata.c (100%) rename drivers/{block => ata}/fsl_sata.h (100%) rename drivers/{block => ata}/libata.c (100%) rename drivers/{block => ata}/mvsata_ide.c (100%) rename drivers/{block => ata}/mxc_ata.c (100%) rename {common => drivers/ata}/sata.c (100%) rename drivers/{block => ata}/sata_ceva.c (95%) rename drivers/{block => ata}/sata_dwc.c (100%) rename drivers/{block => ata}/sata_dwc.h (100%) rename drivers/{block => ata}/sata_mv.c (100%) rename drivers/{block => ata}/sata_sandbox.c (100%) rename drivers/{block => ata}/sata_sil.c (100%) rename drivers/{block => ata}/sata_sil.h (100%) rename drivers/{block => ata}/sata_sil3114.c (100%) rename drivers/{block => ata}/sata_sil3114.h (100%) delete mode 100644 drivers/block/scsi-uclass.c delete mode 100644 drivers/block/sym53c8xx.c create mode 100644 drivers/scsi/Kconfig create mode 100644 drivers/scsi/Makefile rename drivers/{block => scsi}/sandbox_scsi.c (75%) create mode 100644 drivers/scsi/scsi-uclass.c rename {common => drivers/scsi}/scsi.c (86%) -- 2.13.0.506.g27d5fe0cd-goog

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