June 2017 - U-Boot

[U-Boot] [PATCH] drivers: mmc: Avoid memory leak in case of failure
by sunil.m＠techveda.org 20 Oct '17

20 Oct '17

From: Suniel Mahesh <sunil.m(a)techveda.org> priv pointer should be freed before returning with an error value from exynos_dwmci_get_config(). Signed-off-by: Suniel Mahesh <sunil.m(a)techveda.org> Signed-off-by: Raghu Bharadwaj <raghu(a)techveda.org> --- drivers/mmc/exynos_dw_mmc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 40f7892..84ef2da 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -168,6 +168,7 @@ static int exynos_dwmci_get_config(const void *blob, int node, if (host->dev_index > 4) { printf("DWMMC%d: Can't get the dev index\n", host->dev_index); + free(priv); return -EINVAL; } @@ -178,6 +179,7 @@ static int exynos_dwmci_get_config(const void *blob, int node, base = fdtdec_get_addr(blob, node, "reg"); if (!base) { printf("DWMMC%d: Can't get base address\n", host->dev_index); + free(priv); return -EINVAL; } host->ioaddr = (void *)base; @@ -187,6 +189,7 @@ static int exynos_dwmci_get_config(const void *blob, int node, if (err) { printf("DWMMC%d: Can't get sdr-timings for devider\n", host->dev_index); + free(priv); return -EINVAL; } -- 1.9.1

3 6

[U-Boot] Fwd: u-boot.img size limit for spl fat load ?
by Ayoub Zaki 18 Oct '17

18 Oct '17

Hello Albert, First tank you so much for inversting your time for replying. I put some printf in the code and SPL is hanging in spl_load_image_fat function. I also enable the DEBUG messages here the complete log file : http://pastebin.com/raw.php?i=BwUJXDDb So I suspect that SPL is not allocating enough memory to load u-boot.img but I can't find where this size limit is set and where I can change it. Cheers, Ayoub > 2015-01-19 8:08 GMT+01:00 Albert ARIBAUD <albert.u.boot(a)aribaud.net>: > > > Hello Ayoub, > > > > On Fri, 16 Jan 2015 15:42:37 +0100, Ayoub Zaki > > <ayoub.zaki(a)googlemail.com> wrote: > > > Hello list, > > > > > > I'm using u-boot-2014.10 and trying to build it with LCD support for the > > > Beaglebone black to include a Boot logo image. > > > It seems that spl hangs while fat loading a 2.8MB sized u-boot.img ! > > > I reduced the the logo header file and rebuild u-boot, that worked for a > > > 1.6MB sized u-boot.img. > > > Is there any size limit for u-boot ? how to increase the memory allocated > > > by spl ? > > > > There should not be a size limit for SPL fat load. > > > > What may happen is that SPL code is overwritten before it exits, or > > U-Boot itself is corrupted after being loaded. > > > > I assume you've seen the SPL banner and not the U-Boot one; that alone > > does not tell us whether SPL or U-Boot did hang. Can you build U-boot > > with debug enabled? If this results in too big an SPL image, then try > > and at least enable debug for the image chainloading parts, so that you > > can see how far SPL code gets run. > > > > > Thanks you. > > > > No problem. > > > > Amicalement, > > -- > > Albert.

3 7

[U-Boot] ImportError: No module named _libfdt
by Jean-Marc Beaune 06 Oct '17

06 Oct '17

Hello, I am new to U-Boot and trying to compile source code in order to get U-Boot working on a BananaPi. I get the following error while compiling the latest version of master branch: ImportError: No module named _libfdt Has anyone an idea about why Python is not happy? Thank you, JM

3 2

[U-Boot] [PATCH] rockchip: Set up default PWM flags
by Simon Glass 06 Oct '17

06 Oct '17

At present if the PWM set_invert() method is not called then the flags are not set up and the driver does not work properly. Fix this by setting up the default flags when probing. Signed-off-by: Simon Glass <sjg(a)chromium.org> Fixes: 874ee59 (rockchip: pwm: implement pwm_set_invert()) --- drivers/pwm/rk_pwm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index f3b2f7615d..5d78d4a67d 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -92,6 +92,7 @@ static int rk_pwm_probe(struct udevice *dev) return -EINVAL; } priv->freq = clk_get_rate(&clk); + priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE; return 0; } -- 2.13.0.219.gdb65acc882-goog

2 2

[U-Boot] [PATCH] drivers: pci: imx: add imx_pcie_remove function
by Tim Harvey 05 Oct '17

05 Oct '17

There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/imx-common/cpu.c | 3 +++ drivers/pci/pcie_imx.c | 38 ++++++++++++++++++++++++++++++++++++++ include/pci.h | 4 ++++ 3 files changed, 45 insertions(+) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 40fe813..74bdd24 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -275,6 +275,9 @@ u32 get_ahb_clk(void) void arch_preboot_os(void) { +#if defined(CONFIG_PCIE_IMX) + imx_pcie_remove(); +#endif #if defined(CONFIG_CMD_SATA) sata_stop(); #if defined(CONFIG_MX6) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 732d59d..eab0a2b 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -42,6 +42,9 @@ /* PCIe Port Logic registers (memory-mapped) */ #define PL_OFFSET 0x700 +#define PCIE_PL_PFLR (PL_OFFSET + 0x08) +#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) +#define PCIE_PL_PFLR_FORCE_LINK (1 << 15) #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) @@ -445,6 +448,36 @@ static int imx6_pcie_assert_core_reset(void) /* Power up PCIe PHY */ setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); #else + /* + * If the bootloader already enabled the link we need some special + * handling to get the core back into a state where it is safe to + * touch it for configuration. As there is no dedicated reset signal + * wired up for MX6QDL, we need to manually force LTSSM into "detect" + * state before completely disabling LTSSM, which is a prerequisite + * for core configuration. + * + * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong + * indication that the bootloader activated the link. + */ + if (is_mx6dq()) { + u32 val, gpr1, gpr12; + + gpr1 = readl(&iomuxc_regs->gpr[1]); + gpr12 = readl(&iomuxc_regs->gpr[12]); + if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) && + (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) { + val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR); + val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; + val |= PCIE_PL_PFLR_FORCE_LINK; + + imx_pcie_fix_dabt_handler(true); + writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR); + imx_pcie_fix_dabt_handler(false); + + gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2; + writel(val, &iomuxc_regs->gpr[12]); + } + } setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); #endif @@ -652,6 +685,11 @@ void imx_pcie_init(void) } } +void imx_pcie_remove(void) +{ + imx6_pcie_assert_core_reset(); +} + /* Probe function. */ void pci_init_board(void) { diff --git a/include/pci.h b/include/pci.h index d3c955e..c8ef997 100644 --- a/include/pci.h +++ b/include/pci.h @@ -754,6 +754,10 @@ int pci_last_busno(void); extern void pci_mpc85xx_init (struct pci_controller *hose); #endif +#ifdef CONFIG_PCIE_IMX +extern void imx_pcie_remove(void); +#endif + #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) /** * pci_write_bar32() - Write the address of a BAR including control bits -- 2.7.4

7 14

[U-Boot] [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO
by Suresh Gupta 25 Sep '17

25 Sep '17

In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Signed-off-by: Suresh Gupta <suresh.gupta(a)nxp.com> Signed-off-by: Anupam Kumar <anupam.kumar_1(a)nxp.com> --- drivers/spi/fsl_qspi.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e61c67b..d596377 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -659,22 +659,20 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) tx_size = (len > TX_BUFFER_SIZE) ? TX_BUFFER_SIZE : len; - size = tx_size / 4; - for (i = 0; i < size; i++) { + size = tx_size / 16; + /* + * There must be atleast 128bit data + * available in TX FIFO for any pop operation + */ + if (tx_size % 16) + size++; + for (i = 0; i < size * 4; i++) { memcpy(&data, txbuf, 4); data = qspi_endian_xchg(data); qspi_write32(priv->flags, &regs->tbdr, data); txbuf += 4; } - size = tx_size % 4; - if (size) { - data = 0; - memcpy(&data, txbuf, size); - data = qspi_endian_xchg(data); - qspi_write32(priv->flags, &regs->tbdr, data); - } - qspi_write32(priv->flags, &regs->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) -- 1.9.3

2 2

[U-Boot] [PATCH] sunxi: gpio: add missing compatible strings
by Andre Przywara 18 Sep '17

18 Sep '17

The sunxi GPIO driver is missing some compatible strings for recent SoCs. While most of the sunxi GPIO code seems to not rely on this (and so works anyway), the sunxi_name_to_gpio() function does and fails at the moment (for instance when resolving the MMC CD pin name). Add the compatible strings for the A64, H5 and V3s, which were missing from the list. This now covers all pinctrl nodes in our own DTs. Strictly speaking the V3s has only ports B, C, E, F and G, but I think the other SoCs have gaps in there as well and for the pin number computation this does not matter. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- drivers/gpio/sunxi_gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index b47cc66..d20a7e7 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -353,12 +353,16 @@ static const struct udevice_id sunxi_gpio_ids[] = { ID("allwinner,sun8i-a83t-pinctrl", a_all), ID("allwinner,sun8i-h3-pinctrl", a_all), ID("allwinner,sun8i-r40-pinctrl", a_all), + ID("allwinner,sun8i-v3s-pinctrl", a_all), ID("allwinner,sun9i-a80-pinctrl", a_all), + ID("allwinner,sun50i-a64-pinctrl", a_all), + ID("allwinner,sun50i-h5-pinctrl", a_all), ID("allwinner,sun6i-a31-r-pinctrl", l_2), ID("allwinner,sun8i-a23-r-pinctrl", l_1), ID("allwinner,sun8i-a83t-r-pinctrl", l_1), ID("allwinner,sun8i-h3-r-pinctrl", l_1), ID("allwinner,sun9i-a80-r-pinctrl", l_3), + ID("allwinner,sun50i-a64-r-pinctrl", l_1), { } }; -- 2.9.0

4 3

[U-Boot] [PATCH 00/22] mmc: Add support for HS200 and UHS modes
by Jean-Jacques Hiblot 16 Sep '17

16 Sep '17

This series brings support for HS200 and UHS modes to the mmc core. It has been tested with the hsmmc driver on several platforms (DRA7, AM57x, AM437x, beaglebone black). Some modifications are required in the host driver to take advantage of this (voltage switching, tuning). The changes to the host driver will be posted a another series as this one is already long enough. The series starts with a small refactoring of th sd/mmc startup. The first 4 commits are mostly moving code around with little or no functionnal change. Then the notion of "mode" is introduced. Until now, this information wasn't kept in struct mmc. Only the clock and a flag for ddr was kept. Later the mode information will be used to select the clock frequency, the ddr flag and the tuning procedure. It will be also be check against the host capabilities. Then comes the big refactoring job in: "mmc: refactor MMC startup to make it easier to support new modes" and "mmc: refactor SD startup to make it easier to support new modes" Since the number of modes is increasing, it makes sense to try them in a more organized way. those commits use a list of supported modes and iterate through them to find the best working one. It also allows to switch more easilly from one mode to another (switching from HS200 to DDR52 to access boot partitions for example) Then there are a couple of new callback added to: - enable/disable Vdd - check if the card is busy (used during UHS voltage switching) - select the IO voltage Then Power cycle is added. Without power cycle, if a UHS card fails to enumerate in UHS mode, it can't fall back to high speed mode and card enumeration will fail. And finally the last commits add the support for HS200 and UHS. I haven't been able to test the UHS SDR104 mode by lack of compatible sdcard. With this in place and the required changes in the HSMMC (including DAM), we observe significant improvements in the performances on a DRA7 evm: eMMC HS200: 130 MB/s eMMC DDR52: 80 MB/s sd SDR50: 80 MB/s cheers, Jean-Jacques Jean-Jacques Hiblot (18): mmc: split mmc_startup() mmc: move the MMC startup for version above v4.0 in a separate function mmc: make ext_csd part of struct mmc mmc: add a function to read and test the ext csd (mmc >= 4) mmc: introduces mmc modes. mmc: Add a fonction to dump the mmc capabilities mmc: use mmc modes to select the correct bus speed cmd: mmc: display the mode name and current bus speed in the mmc info mmc: refactor SD startup to make it easier to support new modes mmc: refactor MMC startup to make it easier to support new modes mmc: make mmc_set_ios() return status mmc: add power cyle support in mmc core mmc: add a new mmc parameter to disable mmc clock mmc: Add a execute_tuning() callback to the mmc operations. mmc: add HS200 support in MMC core mmc: Add a new callback function to check if the card is busy mmc: Add support for UHS modes mmc: Change mode when switching to a boot partition Kishon Vijay Abraham I (3): mmc: Enable signal voltage to be selected from mmc core mmc: Add a new callback function to enable/disable vdd mmc: disable the mmc clock during power off Vignesh R (1): mmc: Retry some MMC cmds on failure cmd/mmc.c | 3 +- drivers/mmc/fsl_esdhc.c | 2 +- drivers/mmc/mmc-uclass.c | 42 ++ drivers/mmc/mmc.c | 1220 +++++++++++++++++++++++++++++++++------------- include/mmc.h | 138 +++++- 5 files changed, 1058 insertions(+), 347 deletions(-) -- 1.9.1

8 84

[U-Boot] [PATCH 01/14] armv7: Add workaround for USB erratum A-009008
by yinbo.zhu 14 Sep '17

14 Sep '17

From: Suresh Gupta <suresh.gupta(a)freescale.com> USB High Speed (HS) EYE Height Adjustment This patch is adding the erratum for LS1021. Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu(a)nxp.com> --- arch/arm/cpu/armv7/ls102xa/Kconfig | 2 ++ arch/arm/cpu/armv7/ls102xa/soc.c | 12 ++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index b61f3cd..df539e9 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -14,6 +14,8 @@ config ARCH_LS1021A select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE + select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009942 menu "LS102xA architecture" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 52fb6f8..c54daee 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void) return major; } +static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4); + val &= ~(0xF << 6); + out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6)); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + void s_init(void) { } @@ -146,6 +156,8 @@ int arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20042); + /* Erratum */ + erratum_a009008(); return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index c34fd63..f474cfd 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -172,6 +172,10 @@ struct ccsr_gur { #define SCFG_PMCINTECR_ETSECERRG0 0x00080000 #define SCFG_PMCINTECR_ETSECERRG1 0x00040000 #define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 +#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR 0x070 +#define USB_TXVREFTUNE 0x9 + /* Supplemental Configuration Unit */ struct ccsr_scfg { -- 2.1.0.27.g96db324

3 15

[U-Boot] [PATCH] config: remove CONFIG_SPI_FLASH_BAR from some platforms
by Suresh Gupta 13 Sep '17

13 Sep '17

ls1012ardb, ls1046ardb, ls2080ardb has S25FS512S flash which do not support Bank Address Register commands Signed-off-by: Suresh Gupta <suresh.gupta(a)nxp.com> --- include/configs/ls1012a_common.h | 1 - include/configs/ls1046ardb.h | 1 - include/configs/ls2080ardb.h | 1 - 3 files changed, 3 deletions(-) diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 09f890d..0db926f 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -55,7 +55,6 @@ #define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_BAR #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 67ee626..66af039 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -208,7 +208,6 @@ #define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SPI_FLASH_BAR #endif #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 2155a89..79a3d94 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -265,7 +265,6 @@ unsigned long get_board_sys_clk(void); /* SPI */ #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_BAR #define CONFIG_SPI_FLASH_STMICRO #endif -- 1.9.3

5 22