June 2017 - U-Boot

[U-Boot] [PATCH 0/2] x86: Convert all boards to use MMC to driver model
by Simon Glass 27 Jun '17

27 Jun '17

This serial converts x86 boards to use MMC for driver model. It has to disable SCSI to make this work, for now. Once SCSI is sorted out, we can apply the patch. Simon Glass (2): WIP: Disable SCSI on x86 x86: Convert MMC to driver model arch/Kconfig | 1 + arch/x86/cpu/baytrail/valleyview.c | 12 ------ arch/x86/cpu/quark/quark.c | 10 ----- arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/topcliff.c | 20 --------- drivers/mmc/pci_mmc.c | 86 ++++++++++++++++++++++++++------------ include/configs/x86-common.h | 6 ++- include/mmc.h | 12 ------ 8 files changed, 66 insertions(+), 83 deletions(-) delete mode 100644 arch/x86/cpu/queensbay/topcliff.c -- 2.12.2.715.g7642488e1d-goog

3 21

[U-Boot] I found 'board/samsung/smdk2410' was removed after 2017.01 version, does it mean u-boot no longer support smdk2410?
by 发面 27 Jun '17

27 Jun '17

I found the directory 'board/samsung/smdk2410' was removed after 2017.01 version, does it mean u-boot no longer support smdk2410?

1 0

[U-Boot] armv8: cache_v8: mmu setup have the wrong pte attribute
by Cao Jie 27 Jun '17

27 Jun '17

Hi all I do some test on my board which have two armv8 CA53 core, and I found some region (1MB size) don't be correctly mapped by MMU. Through ds5 I can't find this region were mapped. I did some deep debug and found add_map function in cache_v8.c files maybe have some wrong operation for Some region which size equal to 1MB. For 1MB size region need three level translation and the descriptor of level 3 is different with level 1 and level 2. Look like current add_map function can't handle this case. Did someone hit this bug? By the way I use the 2017.05 version. Any feedback would be appreciate. Thanks, Jay

1 1

[U-Boot] [PATCH] bdinfo: print fdt_blob
by Heiko Schocher 26 Jun '17

26 Jun '17

for debugging it is handy to know the fdt_blob address. So print it in bdinfo. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- cmd/bdinfo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index ff3cce0..ef11e72 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -376,6 +376,8 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr, CONFIG_SYS_MALLOC_F_LEN); #endif + if (gd->fdt_blob) + printf("fdt_blob = %p\n", gd->fdt_blob); return 0; } -- 2.7.4

4 3

[U-Boot] [PATCH v7 0/8] rk3328: add support of usb host and gadget
by Meng Dongyang 26 Jun '17

26 Jun '17

Add support of usb host and gadget function for rk3328. Changed in v7: - Romove unused variable ‘prop’ in dwc2 driver Changed in v6: - Rebase on the newest code of master branch - Make xhci-rockchip driver depend on DM_REGULATOR and DM_USB - Remove #ifdef DM_RERULATOR and DM_USB in xhci-rockchip driver - Use dev_read_boot() instead of fdt_getprop() in dwc2 driver Changes in v5: - Propagate return value and print error message when failed Changes in v4: - Splite patch [U-boot,v3,04/10] into two patches - Define set vbus as empty function if the macros aren't set - Prepare a mask and set capabilities in GUSBCFG register once Changes in v3: - Revert change of macro definition in dwc2 driver - Support host mode without HNP/SRP capability through DTS Changes in v2: - Add commit messages - Split patch [U-boot,7/8] into two patches - Use fixed regulator to control vbus instead of gpio Meng Dongyang (8): usb: Kconfig: config USB_XHCI_ROCKCHIP depends on DM_REGULATOR and DM_USB usb: host: xhci-rockchip: use fixed regulator to control vbus rockchip: dts: rk3328: add fixed regulator node for xhci rockchip: configs: rk3328: enable dwc2 driver and config fastboot usb: dwc2: use dev_read_bool() instead of fdt_getprop() rockchip: rk3328: board: add support of dwc2 gadget rockchip: dts: rk3328: support and enable dwc2 rockchip: dts: rk3399: control vbus of typec by fixed regulator arch/arm/dts/rk3328-evb.dts | 25 +++++++++++++++++++- arch/arm/dts/rk3328.dtsi | 10 ++++++++ arch/arm/dts/rk3399-evb.dts | 16 +++++++++++-- board/rockchip/evb_rk3328/evb-rk3328.c | 42 ++++++++++++++++++++++++++++++++++ configs/evb-rk3328_defconfig | 19 +++++++++++++-- drivers/usb/host/Kconfig | 2 ++ drivers/usb/host/dwc2.c | 16 +++++-------- drivers/usb/host/xhci-rockchip.c | 36 ++++++++++++++--------------- include/configs/rk3328_common.h | 3 +++ 9 files changed, 136 insertions(+), 33 deletions(-) -- 1.9.1

2 24

[U-Boot] [PATCH] arc: Add support for HS Development Kit board
by Alexey Brodkin 26 Jun '17

26 Jun '17

ARC HS Development Kit board is a new low-cost development platform sporting ARC HS38 in real silicon with nice set of features such as: * Quad-core ARC HS38 with 512 kB L2 cache and running @1GHz * 4Gb of DDR (we use only lowest 1Gb out of it now) * Lots of DesigWare peripherals * Different connectivity modules: - Synopsys HAPS HT3 - Arduino-compatible connector - MikroBUS This initial commit supports the following peripherals: * UART (DW 8250) * Ethernet (DW GMAC) * SD/MMC (DW Mobile Storage) * USB 1.1 & 2.0 Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- arch/arc/Kconfig | 4 ++ arch/arc/dts/Makefile | 1 + arch/arc/dts/hsdk.dts | 50 ++++++++++++++++++++++ board/synopsys/hsdk/Kconfig | 12 ++++++ board/synopsys/hsdk/MAINTAINERS | 5 +++ board/synopsys/hsdk/Makefile | 7 ++++ board/synopsys/hsdk/hsdk.c | 74 ++++++++++++++++++++++++++++++++ configs/hsdk_defconfig | 37 ++++++++++++++++ include/configs/hsdk.h | 93 +++++++++++++++++++++++++++++++++++++++++ 9 files changed, 283 insertions(+) create mode 100644 arch/arc/dts/hsdk.dts create mode 100644 board/synopsys/hsdk/Kconfig create mode 100644 board/synopsys/hsdk/MAINTAINERS create mode 100644 board/synopsys/hsdk/Makefile create mode 100644 board/synopsys/hsdk/hsdk.c create mode 100644 configs/hsdk_defconfig create mode 100644 include/configs/hsdk.h diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 6e4b1d0e2290..e3f9db7b2972 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -132,10 +132,14 @@ config TARGET_AXS101 config TARGET_AXS103 bool "Support Synopsys Designware SDP board AXS103" +config TARGET_HSDK + bool "Support Synpsys HS DevelopmentKit board" + endchoice source "board/abilis/tb100/Kconfig" source "board/synopsys/Kconfig" source "board/synopsys/axs10x/Kconfig" +source "board/synopsys/hsdk/Kconfig" endmenu diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index 218a6475dd59..63a669471280 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_TARGET_AXS101) += axs101.dtb dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb +dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb targets += $(dtb-y) diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts new file mode 100644 index 000000000000..a7b276c01eb2 --- /dev/null +++ b/arch/arc/dts/hsdk.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + console = &uart0; + }; + + cpu_card { + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000000>; + u-boot,dm-pre-reloc; + }; + }; + + uart0: serial0@f0005000 { + compatible = "snps,dw-apb-uart"; + reg = <0xf0005000 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + ethernet@f0008000 { + #interrupt-cells = <1>; + compatible = "altr,socfpga-stmmac"; + reg = <0xf0008000 0x2000>; + phy-mode = "gmii"; + }; + + ehci@0xf0040000 { + compatible = "generic-ehci"; + reg = <0xf0040000 0x100>; + }; + + ohci@0xf0060000 { + compatible = "generic-ohci"; + reg = <0xf0060000 0x100>; + }; +}; diff --git a/board/synopsys/hsdk/Kconfig b/board/synopsys/hsdk/Kconfig new file mode 100644 index 000000000000..e8c00a6e7d07 --- /dev/null +++ b/board/synopsys/hsdk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_HSDK + +config SYS_BOARD + default "hsdk" + +config SYS_VENDOR + default "synopsys" + +config SYS_CONFIG_NAME + default "hsdk" + +endif diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS new file mode 100644 index 000000000000..d034bc479d06 --- /dev/null +++ b/board/synopsys/hsdk/MAINTAINERS @@ -0,0 +1,5 @@ +AXS10X BOARD +M: Alexey Brodkin <abrodkin(a)synopsys.com> +S: Maintained +F: board/synopsys/hsdk/ +F: configs/hsdk_defconfig diff --git a/board/synopsys/hsdk/Makefile b/board/synopsys/hsdk/Makefile new file mode 100644 index 000000000000..d84dd0326524 --- /dev/null +++ b/board/synopsys/hsdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2017 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += hsdk.o diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c new file mode 100644 index 000000000000..7b562556e6bc --- /dev/null +++ b/board/synopsys/hsdk/hsdk.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dwmmc.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000) +#define CREG_PAE (CREG_BASE + 0x180) +#define CREG_PAE_UPDATE (CREG_BASE + 0x194) +#define CREG_CPU_START (CREG_BASE + 0x400) + +int board_early_init_f(void) +{ + /* In current chip PAE support for DMA is broken, disabling it. */ + writel(0, (void __iomem *) CREG_PAE); + + /* Really apply settings made above */ + writel(1, (void __iomem *) CREG_PAE_UPDATE); + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc fail!\n"); + return 1; + } + + memset(host, 0, sizeof(struct dwmci_host)); + host->name = "Synopsys Mobile storage"; + host->ioaddr = (void *)ARC_DWMMC_BASE; + host->buswidth = 4; + host->dev_index = 0; + host->bus_hz = 100000000; + + add_dwmci(host, host->bus_hz / 2, 400000); + + return 0; +} + +#define RESET_VECTOR_ADDR 0x0 + +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + /* All cores have reset vector pointing to 0 */ + writel(addr, (void __iomem *)RESET_VECTOR_ADDR); + + /* Make sure other cores see written value in memory */ + flush_dcache_all(); +} + +void smp_kick_all_cpus(void) +{ +#define BITS_START_CORE1 1 +#define BITS_START_CORE2 2 +#define BITS_START_CORE3 3 + + int cmd = readl((void __iomem *)CREG_CPU_START); + + cmd |= (1 << BITS_START_CORE1) | + (1 << BITS_START_CORE2) | + (1 << BITS_START_CORE3); + writel(cmd, (void __iomem *)CREG_CPU_START); +} diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig new file mode 100644 index 000000000000..0018c0482e04 --- /dev/null +++ b/configs/hsdk_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARC=y +CONFIG_ISA_ARCV2=y +CONFIG_TARGET_HSDK=y +CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_CLK_FREQ=1000000000 +CONFIG_DEFAULT_DEVICE_TREE="hsdk" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="hsdk# " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_MMC=y +CONFIG_MMC_DW=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h new file mode 100644 index 000000000000..28ac090c052c --- /dev/null +++ b/include/configs/hsdk.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_HSDK_H_ +#define _CONFIG_HSDK_H_ + +#include <linux/sizes.h> + +/* + * CPU configuration + */ +#define ARC_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) +#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_1G + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTM_LEN SZ_32M +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * This board might be of different versions so handle it + */ +#define CONFIG_BOARD_TYPES + +/* + * UART configuration + */ +#define CONFIG_DW_SERIAL +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 33330000 +#define CONFIG_SYS_NS16550_MEM32 + +/* + * Ethernet PHY configuration + */ +#define CONFIG_MII + +/* + * USB 1.1 configuration + */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +/* + * Environment settings + */ +#define CONFIG_ENV_SIZE SZ_16K +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE + +/* + * Environment configuration + */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE SZ_256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Misc utility configuration + */ +#define CONFIG_BOUNCE_BUFFER + +#endif /* _CONFIG_HSDK_H_ */ -- 2.7.5

1 0

[U-Boot] [PATCH] usb: increase usb delay
by Rob Clark 26 Jun '17

26 Jun '17

This makes booting off the USB disks I have go from 50% reliable to 100% reliable. I'm no USB expert so maybe there is a better way. But one way or another we aren't waiting long enough after power-on for the usb device to be ready. Signed-off-by: Rob Clark <robdclark(a)gmail.com> --- common/usb_storage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/usb_storage.c b/common/usb_storage.c index 03171f7..0e3de90 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -1019,7 +1019,7 @@ static int usb_test_unit_ready(ccb *srb, struct us_data *ss) if ((srb->sense_buf[2] == 0x02) && (srb->sense_buf[12] == 0x3a)) return -1; - mdelay(100); + mdelay(250); } while (retries--); return -1; -- 2.9.4

2 1

[U-Boot] [PATCH] arcv2: Set IOC aperture so it covers available DDR
by Alexey Brodkin 26 Jun '17

26 Jun '17

We used to use the same memory layout and size for a couple of boards and thus we just hardcoding IOC aperture start and size. Now when we're getting more boards with more memory on board we need to have an ability to set IOC so it matches real DDR layout and size. Even though it is not really a must but for simplicity we assume IOC covers all the DDR we have, that gives us a chance to not bother where DMA buffers are allocated - any part of DDR is OK. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- arch/arc/lib/cache.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index f1436bf19992..cbae27e9fcec 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -8,6 +8,7 @@ #include <common.h> #include <linux/compiler.h> #include <linux/kernel.h> +#include <linux/log2.h> #include <asm/arcregs.h> #include <asm/cache.h> @@ -215,17 +216,33 @@ void cache_init(void) read_decode_cache_bcr_arcv2(); if (ioc_exists) { + /* IOC Aperture start is equal to DDR start */ + unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + /* IOC Aperture size is equal to DDR size */ + long ap_size = CONFIG_SYS_SDRAM_SIZE; + flush_dcache_all(); invalidate_dcache_all(); - /* IO coherency base - 0x8z */ - write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000); - /* IO coherency aperture size - 512Mb: 0x8z-0xAz */ - write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 0x11); - /* Enable partial writes */ + if (!is_power_of_2(ap_size) || ap_size < 4096) + panic("IOC Aperture size must be power of 2 and bigger 4Kib"); + + /* + * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, + * so setting 0x11 implies 512M, 0x12 implies 1G... + */ + write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, + order_base_2(ap_size/1024) - 2); + + + /* IOC Aperture start must be aligned to the size of the aperture */ + if (ap_base % ap_size != 0) + panic("IOC Aperture start must be aligned to the size of the aperture"); + + write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); - /* Enable IO coherency */ write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); + } #endif } -- 2.7.5

1 0

[U-Boot] saveenv on qemu vexpress-a9 flash problem
by Yonghao Wang 26 Jun '17

26 Jun '17

Hello, For learning and education purposes, I am trying to use qemu-arm to run u-boot. After reading online materials, my question is that if it is possible to save the environment variables on simulated Flash "permanently". I use raw file "pflash0.img" as simulated flash. So far, after modify some #defines in the header file, now I can run the following: " qemu-system-arm -M vexpress-a9 -kernel u-boot -m 512M -nographic -drive file=pflash0.img,format=raw,if=pflash " u-boot boots ok, and I can save the env variables. It takes effects after "reset" u-boot. However, the values does not get written into the flash image file. So next time I run qemu using same "pflash0.img" file. The environment variables get lost. you will have "bad CRC" message again. I have these two questions: 1. Is it possible to save the environment variables to qemu simulated flash file "permanently"? 2. u-boot seems only report the flash size that links to config header files and does not link to the qemu simulated flash image size, that is to say no matter how big or small I created the ""pflash0.img" file, uboot only reports 128MiB flash. Maybe I am doing something very stupid here. Please anybody can give some suggestions. Thank you all! -- Yonghao (Leo) Wang

1 1

[U-Boot] [ANN] U-Boot v2017.05-rc2 released
by Tom Rini 26 Jun '17

26 Jun '17

Hey all, It's release day and v2017.05-rc2 is out. I think my patchwork queue is looking good currently. I have some outstanding removal patches to take from Masahiro related to architectures that I removed as promised. The release is bigger than I really wanted, but since I was on vacation for most of the normal -rc1 window, stuff came in that would have come in then now, instead. Things are on track for -rc3 on the 1st. Thanks all! -- Tom

7 24