May 2017 - U-Boot

[U-Boot] [PATCH v2 1/3] arm: ls1021a: Adjust memory mapping for Flash/SD card on LS1021AQDS/TWR
by Alison Wang 25 May '17

25 May '17

This patch is to adjust the memory mapping for FLash/SD card on LS1021AQDS and LS1021ATWR, such as U-Boot start address on serial Flash, QE firmware load address and environment address. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- Changes: - None include/configs/ls1021aqds.h | 10 +++++----- include/configs/ls1021atwr.h | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index c3224c8..97f6c43 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -69,7 +69,7 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_TEXT_BASE 0x40100000 #endif #ifdef CONFIG_NAND_BOOT @@ -499,7 +499,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DEVICE_DISABLE -#define CONFIG_SYS_QE_FW_ADDR 0x600c0000 +#define CONFIG_SYS_QE_FW_ADDR 0x60940000 #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -550,14 +550,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET 0x300000 #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_QSPI_BOOT) #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_NAND_BOOT) #define CONFIG_ENV_IS_IN_NAND @@ -565,7 +565,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 1d0b469..aecbee0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -133,7 +133,7 @@ #endif #ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_TEXT_BASE 0x40100000 #endif #ifndef CONFIG_SYS_TEXT_BASE @@ -410,7 +410,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif -#define CONFIG_SYS_QE_FW_ADDR 0x600c0000 +#define CONFIG_SYS_QE_FW_ADDR 0x60940000 /* * Environment @@ -418,18 +418,18 @@ #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET 0x300000 #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x20000 #elif defined(CONFIG_QSPI_BOOT) #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET 0x300000 #define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -- 2.1.0.27.g96db324

2 6

[U-Boot] [PATCH 1/2][v2] armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support
by Priyanka Jain 25 May '17

25 May '17

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A-72 CPUs and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2081A has one more similar personality which has four CPUs: LS2041A Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> --- Changes for v2: Uddated copyright arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 +++- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 11 +++++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 3 +++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ drivers/pci/pcie_layerscape.c | 7 +++++-- drivers/pci/pcie_layerscape.h | 3 +++ drivers/pci/pcie_layerscape_fixup.c | 7 +++++-- 7 files changed, 33 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c24f3f1..970e759 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ @@ -102,7 +103,8 @@ static void fix_pcie_mmu_map(void) /* Fix PCIE base and size for LS2088A */ if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || - (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) { + (ver == SVR_LS2048A) || (ver == SVR_LS2044A) || + (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { for (i = 0; i < ARRAY_SIZE(final_map); i++) { switch (final_map[i].phys) { case CONFIG_SYS_PCIE1_PHYS_ADDR: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index c7496c0..3ae16ae 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -5,6 +5,7 @@ SoC overview 3. LS1012A 4. LS1046A 5. LS2088A + 6. LS2081A LS1043A --------- @@ -227,3 +228,13 @@ LS2088A SoC has 3 more similar SoC personalities 3)LS2044A, few difference w.r.t. LS2084A: a) Four 64-bit ARM v8 Cortex-A72 CPUs + +LS2081A +-------- +LS2081A is 40-pin derivative of LS2084A. +So feature-wise it is same as LS2084A. +Refer to LS2084A(LS2088A) section above for details. + +It has one more similar SoC personality +1)LS2041A, few difference w.r.t. LS2081A: + a) Four 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 95c3e2f..d0e42c5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015, Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@ -15,6 +16,8 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), + CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), + CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 426fe8e..6ac534e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@ -54,6 +55,8 @@ struct cpu_type { #define SVR_LS2084A 0x870910 #define SVR_LS2048A 0x870920 #define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870919 +#define SVR_LS2041A 0x870915 #define SVR_DEV_LS2080A 0x8701 diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 1c5a33a..5b5651a 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver * @@ -170,7 +171,8 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie) /* Fix the pcie memory map for LS2088A series SoCs */ svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A) { + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) { if (io) io->phys_start = (io->phys_start & (PCIE_PHYS_SIZE - 1)) + @@ -531,7 +533,8 @@ static int ls_pcie_probe(struct udevice *dev) svr = get_svr(); svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A) { + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) { pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + LS2088A_PCIE_PHYS_SIZE * pcie->idx; pcie->ctrl = pcie->lut + 0x40000; diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index e3324a5..07a7014 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver * @@ -117,6 +118,8 @@ #define SVR_LS2084A 0x870910 #define SVR_LS2048A 0x870920 #define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870919 +#define SVR_LS2041A 0x870915 /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index d504bbd..f08c152 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver * @@ -82,7 +83,8 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A) + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) compat = "fsl,ls2088a-pcie"; else compat = CONFIG_FSL_PCIE_COMPAT; @@ -217,7 +219,8 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A) + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) compat = "fsl,ls2088a-pcie"; else compat = CONFIG_FSL_PCIE_COMPAT; -- 1.7.4.1

2 4

[U-Boot] [PATCH 1/2][v7] board: freescale: ls2080ardb: Update QIXIS code
by Priyanka Jain 25 May '17

25 May '17

Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS flag is enabled As per board documentation, default sysclk is 100MHz. In case QIXIS code is not enabled, update default sysclk value to 100MHz Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v4: Added changes for default sysclk as 100MHz board/freescale/ls2080ardb/ls2080ardb.c | 21 +++++++++++++++++---- 1 files changed, 17 insertions(+), 4 deletions(-) diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 52adca0..1379b81 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -23,8 +23,10 @@ #include <asm/arch/ppa.h> #include <fsl_sec.h> +#ifdef CONFIG_FSL_QIXIS #include "../common/qixis.h" #include "ls2080ardb_qixis.h" +#endif #include "../common/vid.h" #define PIN_MUX_SEL_SDHC 0x00 @@ -58,12 +60,15 @@ unsigned long long get_qixis_addr(void) int checkboard(void) { +#ifdef CONFIG_FSL_QIXIS u8 sw; +#endif char buf[15]; cpu_name(buf); printf("Board: %s-RDB, ", buf); +#ifdef CONFIG_FSL_QIXIS sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); @@ -79,7 +84,7 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - +#endif puts("SERDES1 Reference : "); printf("Clock1 = 156.25MHz "); printf("Clock2 = 156.25MHz"); @@ -93,6 +98,7 @@ int checkboard(void) unsigned long get_board_sys_clk(void) { +#ifdef CONFIG_FSL_QIXIS u8 sysclk_conf = QIXIS_READ(brdcfg[1]); switch (sysclk_conf & 0x0F) { @@ -111,7 +117,8 @@ unsigned long get_board_sys_clk(void) case QIXIS_SYSCLK_166: return 166666666; } - return 66666666; +#endif + return 100000000; } int select_i2c_ch_pca9547(u8 ch) @@ -134,6 +141,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel) int config_board_mux(int ctrl_type) { +#ifdef CONFIG_FSL_QIXIS u8 reg5; reg5 = QIXIS_READ(brdcfg[5]); @@ -151,7 +159,7 @@ int config_board_mux(int ctrl_type) } QIXIS_WRITE(brdcfg[5], reg5); - +#endif return 0; } @@ -181,8 +189,9 @@ int board_init(void) #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +#ifdef CONFIG_FSL_QIXIS QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); - +#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -319,6 +328,7 @@ int ft_board_setup(void *blob, bd_t *bd) void qixis_dump_switch(void) { +#ifdef CONFIG_FSL_QIXIS int i, nr_of_cfgsw; QIXIS_WRITE(cms[0], 0x00); @@ -329,6 +339,7 @@ void qixis_dump_switch(void) QIXIS_WRITE(cms[0], i); printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } +#endif } /* @@ -339,6 +350,7 @@ void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr) { +#ifdef CONFIG_FSL_QIXIS u8 sw; sw = QIXIS_READ(arch); @@ -348,4 +360,5 @@ void update_spd_address(unsigned int ctrl_num, else if (ctrl_num == 1 && slot == 1) *addr = SPD_EEPROM_ADDRESS3; } +#endif } -- 1.7.4.1

2 3

[U-Boot] [PATCH][v3] driver: net: fsl-mc: Update fsl_mc_ldpaa_exit() path
by Yogesh Gaur 25 May '17

25 May '17

Earlier when MC is loaded but DPL is not deployed results in FDT fix-up code execution hang. For this case now print message on console and returns success instead of return -ENODEV. This update allows to continue fdt fixup execution. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur(a)nxp.com> Signed-off-by: Priyanka Jain <Priyanka.jain(a)nxp.com> --- Changes for v3: Incorporated York's review comments. drivers/net/fsl-mc/mc.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 079082a..a0fbdcb 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1,4 +1,5 @@ /* + * Copyright (C) 2017 NXP Semiconductors * Copyright (C) 2014 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@ -1258,6 +1259,7 @@ err: int fsl_mc_ldpaa_exit(bd_t *bd) { int err = 0; + bool is_dpl_apply_status = false; if (bd && mc_lazy_dpl_addr && !fsl_mc_ldpaa_exit(NULL)) { mc_apply_dpl(mc_lazy_dpl_addr); @@ -1268,14 +1270,18 @@ int fsl_mc_ldpaa_exit(bd_t *bd) if (bd && get_mc_boot_status() != 0) return 0; - if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) { - printf("ERROR: fsl-mc: DPL is not applied\n"); - err = -ENODEV; - return err; - } + /* If DPL is deployed, set is_dpl_apply_status as TRUE. */ + if (!get_dpl_apply_status()) + is_dpl_apply_status = true; - if (bd && !get_mc_boot_status() && !get_dpl_apply_status()) - return err; + /* + * For case MC is loaded but DPL is not deployed, return success and + * print message on console. Else FDT fix-up code execution hanged. + */ + if (bd && !get_mc_boot_status() && !is_dpl_apply_status) { + printf("fsl-mc: DPL not deployed, DPAA2 ethernet not work\n"); + return 0; + } err = dpbp_exit(); if (err < 0) { -- 1.9.1

2 1

[U-Boot] [PATCH 1/2] armv8: ls1046ardb: Make NET independent of FMan
by York Sun 25 May '17

25 May '17

This allows using PCIe NIC without enabling DPAA FMan. Signed-off-by: York Sun <york.sun(a)nxp.com> CC: Mingkai Hu <mingkai.hu(a)nxp.com> --- board/freescale/ls1046ardb/Makefile | 2 +- include/configs/ls1046ardb.h | 15 +++++++++------ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile index b92ed0b..4076558 100644 --- a/board/freescale/ls1046ardb/Makefile +++ b/board/freescale/ls1046ardb/Makefile @@ -7,6 +7,6 @@ obj-y += ddr.o obj-y += ls1046ardb.o ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o +obj-$(CONFIG_NET) += eth.o obj-y += cpld.o endif diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 67ee626..40a5635 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -178,18 +178,20 @@ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ #endif +#define AQR105_IRQ_MASK 0x80000000 /* FMan */ #ifndef SPL_NO_FMAN -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET + +#ifdef CONFIG_NET #define CONFIG_PHYLIB -#define CONFIG_PHYLIB_10G #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ - #define CONFIG_PHY_REALTEK -#define CONFIG_PHY_AQUANTIA -#define AQR105_IRQ_MASK 0x80000000 +#endif +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHY_AQUANTIA +#define CONFIG_PHYLIB_10G #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 @@ -200,6 +202,7 @@ #define CONFIG_ETHPRIME "FM1@DTSEC3" #endif + #endif /* QSPI device */ -- 2.7.4

3 5

[U-Boot] [PATCH][v2] board: freescale: ls2080ardb: Enable SD interface for RevF board
by Priyanka Jain 25 May '17

25 May '17

LS2080ARDB/LS2088ARDB RevF board has smart voltage translator which needs to be programmed to enable high speed SD interface by setting GPIO4_10 output to zero Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> --- Changes for v2: Added NXP copyright .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ board/freescale/ls2080ardb/ls2080ardb.c | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 80c421f..59410aa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -1,6 +1,7 @@ /* * LayerScape Internal Memory Map * + * Copyright (C) 2017 NXP Semiconductors * Copyright 2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ @@ -45,6 +46,9 @@ #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) +#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) +#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index ea05ec6..c2aa101 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -1,4 +1,5 @@ /* + * Copyright (C) 2017 NXP Semiconductors * Copyright 2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@ -205,6 +206,23 @@ int board_early_init_f(void) int misc_init_r(void) { +#ifdef CONFIG_FSL_QIXIS + u8 sw; + + sw = QIXIS_READ(arch); + /* + * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator + * which needs to be programmed to enable high speed SD interface + * by setting GPIO4_10 output to zero + */ + if ((sw & 0xf) == 0x5) { + out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | + in_le32(GPIO4_GPDIR_ADDR))); + out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & + in_le32(GPIO4_GPDAT_ADDR))); + } +#endif + if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); -- 1.7.4.1

2 1

[U-Boot] [PATCH] armv8: ls1046a: enable PCI command tool
by Zhiqiang Hou 25 May '17

25 May '17

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- include/configs/ls1046a_common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 8ec1247..2779bb4 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -109,6 +109,16 @@ #define CONFIG_SYS_I2C_MXC_I2C3 #define CONFIG_SYS_I2C_MXC_I2C4 +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#endif + /* Command line configuration */ #define CONFIG_CMD_ENV -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] mmc: sdhci-cadence: set timing mode register depending on frequency
by Masahiro Yamada 25 May '17

25 May '17

The MMC framework in U-Boot does not support a systematic API for timing switch like mmc_set_timing() in Linux. U-Boot just provides a hook to change the clock frequency via mmc_set_clock(). It is up to drivers if additional register settings are needed. This driver needs to set a correct timing mode into a register when it migrates to a different speed mode. Only increasing clock frequency could result in setup/hold timing violation. The timing mode should be decided by checking MMC_TIMING_* like drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not supported by U-Boot for now. Just use mmc->clock to decide the timing mode. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/mmc/sdhci-cadence.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index dc86d108a698..4e1c5f78a419 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -23,6 +23,18 @@ #define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 #define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 +#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) +#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8 +#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f +#define SDHCI_CDNS_HRS06_MODE_MASK 0x7 +#define SDHCI_CDNS_HRS06_MODE_SD 0x0 +#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 +#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 + /* SRS - Slot Register Set (SDHCI-compatible) */ #define SDHCI_CDNS_SRS_BASE 0x200 @@ -111,6 +123,41 @@ static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat, return 0; } +static void sdhci_cdns_set_control_reg(struct sdhci_host *host) +{ + struct mmc *mmc = host->mmc; + struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev); + unsigned int clock = mmc->clock; + u32 mode, tmp; + + /* + * REVISIT: + * The mode should be decided by MMC_TIMING_* like Linux, but + * U-Boot does not support timing. Use the clock frequency instead. + */ + if (clock <= 26000000) + mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */ + else if (clock <= 52000000) { + if (mmc->ddr_mode) + mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; + else + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; + } else { + /* The IP supports HS200/HS400, but U-Boot does not. */ + printf("unsupported frequency %d\n", clock); + return; + } + + tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06); + tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK; + tmp |= mode; + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06); +} + +static const struct sdhci_ops sdhci_cdns_ops = { + .set_control_reg = sdhci_cdns_set_control_reg, +}; + static int sdhci_cdns_bind(struct udevice *dev) { struct sdhci_cdns_plat *plat = dev_get_platdata(dev); @@ -137,6 +184,7 @@ static int sdhci_cdns_probe(struct udevice *dev) host->name = dev->name; host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; + host->ops = &sdhci_cdns_ops; host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev->of_offset); -- 2.7.4

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[U-Boot] mmc: meson: increase max block number per request
by Heiner Kallweit 25 May '17

25 May '17

Number of blocks is a 9 bit field where 0 stands for a unlimited number of blocks. Therefore the max number of blocks which can be set is 511. Signed-off-by: Heiner Kallweit <hkallweit1(a)gmail.com> --- drivers/mmc/meson_gx_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 8e28ab7..2dda1b7 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -244,7 +244,7 @@ static int meson_mmc_probe(struct udevice *dev) MMC_MODE_HS_52MHz | MMC_MODE_HS; cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); cfg->f_max = 100000000; /* 100 MHz */ - cfg->b_max = 256; /* max 256 blocks */ + cfg->b_max = 511; /* max 512 - 1 blocks */ cfg->name = dev->name; mmc->priv = pdata; -- 2.12.2

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[U-Boot] [PATCH 1/2] regulator: pfuze100: add SPDX License
by Peng Fan 25 May '17

25 May '17

Add SPDX license Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/power/regulator/pfuze100.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index 4702161..88b1b72 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -1,3 +1,11 @@ +/* + * Copyright 2017 NXP + * + * Peng Fan <peng.fan(a)nxp.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + #include <common.h> #include <fdtdec.h> #include <errno.h> -- 2.6.2

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