May 2017 - U-Boot

[U-Boot] [PATCH 0/4] mips: bmips: add HSSPI support
by Álvaro Fernández Rojas 22 Jan '18

22 Jan '18

BCM63xx HSSPI controller has the same issue as BCM63xx SPI controller: it doesn't allow keeping CS active between transfers. However, this controller allows changing CS polarities, which is used in the linux upstream driver to manage CS as desired. Álvaro Fernández Rojas (4): dm: spi: add BCM63xx HSSPI driver mips: bmips: add bcm63xx-hsspi driver support for BCM6328 mips: bmips: add bcm63xx-hsspi driver support for BCM63268 mips: bmips: enable the SPI flash on the Comtrend AR-5387un arch/mips/dts/brcm,bcm63268.dtsi | 21 ++ arch/mips/dts/brcm,bcm6328.dtsi | 24 ++ arch/mips/dts/comtrend,ar-5387un.dts | 12 + configs/comtrend_ar5387un_ram_defconfig | 8 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 392 ++++++++++++++++++++++++++++++++ 7 files changed, 466 insertions(+) create mode 100644 drivers/spi/bcm63xx_hsspi.c -- 2.1.4

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[U-Boot] [PATCHv6 00/28] Retrieve MAC address from EEPROM
by Olliver Schinagl 05 Dec '17

05 Dec '17

This patch-series introduces methods to retrieve the MAC address from an onboard EEPROM. The series does a few small cleanups at the start, as either I ran into them while doing this series and fixed them along the way or actually depended on them. A manufacturer wants to produce boards and may even have MAC addresses for boards. Maintaining unique environments on a per-board basis however is horrible. Also this data should be very persistent, and not easily deletable by simply wiping the environment or device tree. Finally there are chips available on the market with a pre-programmed MAC address chips (proms) that a board manufacturer wants to use. Because of this, the MAC needs to be stored be able to read from such an 'external' source. The current idea of the eeprom layout, is to skip the first 8 bytes, so that other information can be stored there if needed, for example a header with some magic to identify the EEPROM. Or equivalent purposes. After those 8 bytes the MAC address follows the first macaddress. The macaddress is appended by a CRC8 byte and then padded to make for nice 8 bytes. Following the first macaddress one can store a second, or a third etc etc macaddress. The CRC8 is optional (via a define) but is strongly recommended to have. It helps preventing user error and more importantly, checks if the bytes read are actually a user inserted address. E.g. only writing 1 macaddress into the eeprom but trying to consume 2. These patches where tested on Olimex OLinuXino Lime1 (A10/A20), Lime2 (NAND and eMMC) and A20-OLinuXino-MICRO-4G variants and have been in use internally on our production systems since v2 of this patch set. TODO in a follow up series: * Replace the I2C specific read function to a generic function using Maxime Ripard's EEPROM uclass once merged. * Upgrade to use the EERPOM layout functionality as suggested by Igor Grinberg * Add EEPROM/Mac commands suggested by York Sun The series was initially based ontop of Joe's u-boot_net/next branches, but I rebased it ontop of u-boot/master to get the latest sunxi changes, including: sun7i: Add support for Olimex A20-OLinuXino-LIME2-eMMC ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc Which are on their way to being merged in master. So once those land into master this all should apply cleanly. Sorry Joe! ======= Changes since v5: * Removed changes to eth_legacy as per Simon's request * Adapted, improved and fixed the emac/gmac Kconfig conversion * Renamed sunxi_[eg]mac to sun[47]_mac to be more clear and allowing preparing to merge common parts into sunxi_common * Added a few more MAC helpers * Added PHY_GIGE as Kconfig symbol Changes since v4: * Some patches have been merged, so those are no longer included in the set. * Reworked review comments * Added the source of a MAC address * Made sunxi-gmac a subclassed driver * Switch sunxi-[eg]mac to Kconfig * Drop the FDT injection code for now, this needs more thought/discussion Changes since v3: * Split off board specific stuff and only modify the generic functions * Make reading of an eeprom available to every board. By default this is unconfigure and thus should just fall through * Clean some minor bits up (ARP_HLEN) and use it more generically * Update the gen_ethaddr_crc as suggested by simon * Let the fixup_ethernet from fdt_common insert mac addresses to the environment for unconfigured devices. There is a small caveat here however as described in the TODO above. * Print the mac address that u-boot assigned to each device. Changes since v2: * Drop the id byte altogether and just mark it as reserved. The 'index' can be used to indicate the interface instead * Addopt the read_rom_hwaddr hooks * Renamed crc8 tool to gen_ethaddr_crc * Improved the layout EEPROM example * Made a function out of the hwaddress writing function in sunxi_emac so it can be re-used as the write_hwaddr net_ops hook. * No longer handle fdt parameters in board.c Changes since v1: * Do not CRC the id byte, move it just after the crc byte. One of the reasons I decided to move it after the crc8 was mostly due to mass generation of MAC + CRC combo's where the ID is still unknown. Also not crc-ing the ID means that it is much easier for a user to change it (via the u-boot i2c cmd line or from within linux) without having to worry about the crc. * Add a generator to convert a MAC address from the input to a MAC + CRC8 on the output. Emmanuel Vadot (1): ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc Olliver Schinagl (27): sun7i: Add support for Olimex A20-OLinuXino-LIME2-eMMC net: core: Add PHY_GIGE as a Kconfig symbol net: sunxi simplify defconfig net: sunxi: Re-add RTL8211X_PHY_FORCE_MASTER net: sunxi: Restore sunxi_[eg]mac behavior net: sunxi: Move GMAC_TX_DELAY to the driver net: cosmetic: Do not use magic values for ARP_HLEN net: core: Sanitize get/set operations for enetaddr net: core: Inform the user of the device MAC address net: core: Add MAC address helper functions net: Add ability to set MAC address via EEPROM net: core: print the source of the MAC address net: cosmetic: A MAC address is not limited to SROM net: core: Check return value of read_rom_hwaddr fdt: fixup_eth: Remove code duplication with a function fdt: fixup_eth: improve error catching/reduce identation arm: sunxi: Expose function to generate sunxi-specific a MAC address net: sunxi_emac: Write HW address via net_ops hook net: sunxi: Rename sunxi_emac to a more specific sun4i_mac net: sunxi: Have sunxi common functions together net: sun4i_mac: Add read_rom_hwaddr hook net: sun7i_mac: Make the sun7i a dw driver subclass net: dw: Expose designware_eth_start net: sun7i_mac: Add read_rom_hwaddr hook net: sun8i_gmac: Add read_rom_hwaddr hook net: sun8i: fix whitespace net: sunxi: Enable eeprom on OLinuXino Lime boards (again) arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 2 +- arch/arm/include/asm/arch-sunxi/sys_proto.h | 4 +- arch/arm/mach-sunxi/Kconfig | 14 +- arch/arm/mach-sunxi/board.c | 1 - board/sunxi/MAINTAINERS | 5 + board/sunxi/Makefile | 1 - board/sunxi/board.c | 146 ++++++++----- common/fdt_support.c | 33 ++- configs/A10-OLinuXino-Lime_defconfig | 4 +- configs/A20-OLinuXino-Lime2-eMMC_defconfig | 36 ++++ configs/A20-OLinuXino-Lime2_defconfig | 8 +- configs/A20-OLinuXino-Lime_defconfig | 8 +- configs/A20-OLinuXino_MICRO_defconfig | 8 +- configs/A20-Olimex-SOM-EVB_defconfig | 4 +- configs/Bananapi_defconfig | 3 +- configs/Bananapro_defconfig | 3 +- configs/CSQ_CS908_defconfig | 4 +- configs/Colombus_defconfig | 3 +- configs/Cubieboard2_defconfig | 4 +- configs/Cubietruck_defconfig | 3 +- configs/Hummingbird_A31_defconfig | 3 +- configs/Itead_Ibox_A20_defconfig | 4 +- configs/Lamobo_R1_defconfig | 3 +- configs/Linksprite_pcDuino3_Nano_defconfig | 3 +- configs/Linksprite_pcDuino3_defconfig | 4 +- configs/Mele_A1000G_quad_defconfig | 4 +- configs/Mele_I7_defconfig | 4 +- configs/Mele_M3_defconfig | 4 +- configs/Mele_M5_defconfig | 4 +- configs/Mele_M9_defconfig | 4 +- configs/Orangepi_defconfig | 3 +- configs/Orangepi_mini_defconfig | 3 +- configs/Sinlinx_SinA31s_defconfig | 4 +- configs/Sinovoip_BPI_M2_defconfig | 3 +- configs/Wits_Pro_A20_DKT_defconfig | 3 +- configs/i12-tvbox_defconfig | 4 +- configs/icnova-a20-swac_defconfig | 4 +- configs/mixtile_loftq_defconfig | 3 +- doc/README.enetaddr | 95 +++++++++ drivers/net/Kconfig | 76 +++++-- drivers/net/Makefile | 5 +- drivers/net/designware.c | 3 +- drivers/net/designware.h | 1 + drivers/net/{sunxi_emac.c => sun4i_mac.c} | 267 +++++++++++++----------- board/sunxi/gmac.c => drivers/net/sun7i_mac.c | 54 ++++- drivers/net/sun8i_emac.c | 15 +- drivers/net/sunxi_common.c | 33 +++ drivers/net/sunxi_common.h | 13 ++ include/configs/sunxi-common.h | 13 +- include/net.h | 76 ++++++- net/Kconfig | 59 ++++++ net/eth-uclass.c | 65 +++--- net/eth_common.c | 53 ++++- net/eth_legacy.c | 4 +- scripts/config_whitelist.txt | 2 - 55 files changed, 842 insertions(+), 350 deletions(-) create mode 100644 configs/A20-OLinuXino-Lime2-eMMC_defconfig rename drivers/net/{sunxi_emac.c => sun4i_mac.c} (59%) rename board/sunxi/gmac.c => drivers/net/sun7i_mac.c (67%) create mode 100644 drivers/net/sunxi_common.c create mode 100644 drivers/net/sunxi_common.h -- 2.11.0

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[U-Boot] [PATCH v1 0/9] Enable falcon boot for LS1043ARDB SDCARD boot
by York Sun 29 Nov '17

29 Nov '17

With two previous sets, "Add FIT support for falcon boot" and "Enable PPA in SPL for ARMv8 Layerscape SoCs", this set enables falcon boot for LS1043ARDB SDCARD boot and related secure boot. Ruchika Gupta (2): fsl: secure boot: Remove dependency of command line for fsl_validate.c fsl: secure boot: Add fsl_rsa_modexp_raw function for scenarios without DM model York Sun (7): armv8: ls1043ardb: Use static DDR setting for SPL secure boot armv8: layerscape: Eanble falcon boot armv8: ls1043ardb_sdcard: Enable falcon boot crypto: fsl: Allocate memory for descriptor from main memory armv8: fsl-layerscape: Enable secure boot valiation for SPL boot armv8: layerscape: falcon: Implement FIT image validation armv8: ls1043ardb: Enable loading PPA and falcon boot for SD secure boot .../arm/cpu/armv8/fsl-layerscape/doc/README.falcon | 86 ++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/spl.c | 58 +++++++++++++++ arch/arm/include/asm/fsl_secure_boot.h | 5 +- arch/arm/include/asm/system.h | 2 +- arch/arm/lib/spl.c | 11 +++ board/freescale/common/Makefile | 5 +- board/freescale/common/fsl_validate.c | 19 +++-- board/freescale/ls1043ardb/ddr.c | 46 ++++++++++++ board/freescale/ls1043ardb/ddr.h | 67 +++++++++++++++++ configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 10 ++- configs/ls1043ardb_sdcard_defconfig | 8 +- drivers/crypto/fsl/fsl_rsa.c | 43 ++++++++++- include/configs/ls1043a_common.h | 9 ++- include/configs/ls1043ardb.h | 14 +++- 14 files changed, 360 insertions(+), 23 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon -- 2.7.4

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[U-Boot] [PATCH v2 1/3] x86: congatec: add secureboot enabled defconfig for conga-qeval20-qa3-e3845
by Anatolij Gustschin 16 Nov '17

16 Nov '17

From: Markus Valentin <mv(a)denx.de> Signed-off-by: Markus Valentin <mv(a)denx.de> [agust: rebased, fixed to build with v2017.05] Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - add Reviewed-by tag ...0-qa3-e3845-internal-uart-secure-boot_defconfig | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 configs/conga-qeval20-qa3-e3845-internal-uart-secure-boot_defconfig diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart-secure-boot_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart-secure-boot_defconfig new file mode 100644 index 0000000..b78f90e --- /dev/null +++ b/configs/conga-qeval20-qa3-e3845-internal-uart-secure-boot_defconfig @@ -0,0 +1,77 @@ +CONFIG_X86=y +CONFIG_VENDOR_CONGATEC=y +CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y +CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845" +CONFIG_INTERNAL_UART=y +CONFIG_HAVE_INTEL_ME=y +CONFIG_BAYTRAIL_SECURE_BOOT=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_VGA_BIOS_ADDR=0xfffa0000 +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SEABIOS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_INTEL=y +CONFIG_WINBOND_W83627=y +CONFIG_MMC=y +CONFIG_MMC_PCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_114=y +CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_USE_PRIVATE_LIBGCC=y -- 2.7.4

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[U-Boot] [PATCH v1 0/1] arm64: enable SPL with ATF support
by Kever Yang 25 Oct '17

25 Oct '17

This patch needs work with some patch for SPL support multi binary in FIT which is from Andre. The entry point of bl31 and bl33 is still using hard code because we still can not get them from the FIT image information. Changes in v1: - license update - split out as separate patch Kever Yang (1): spl: add support to booting with ATF common/spl/Kconfig | 14 +++ common/spl/Makefile | 1 + common/spl/spl.c | 4 + common/spl/spl_atf.c | 92 +++++++++++++++++ include/atf_common.h | 276 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/spl.h | 1 + 6 files changed, 388 insertions(+) create mode 100644 common/spl/spl_atf.c create mode 100644 include/atf_common.h -- 1.9.1

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[U-Boot] Fwd: u-boot.img size limit for spl fat load ?
by Ayoub Zaki 18 Oct '17

18 Oct '17

Hello Albert, First tank you so much for inversting your time for replying. I put some printf in the code and SPL is hanging in spl_load_image_fat function. I also enable the DEBUG messages here the complete log file : http://pastebin.com/raw.php?i=BwUJXDDb So I suspect that SPL is not allocating enough memory to load u-boot.img but I can't find where this size limit is set and where I can change it. Cheers, Ayoub > 2015-01-19 8:08 GMT+01:00 Albert ARIBAUD <albert.u.boot(a)aribaud.net>: > > > Hello Ayoub, > > > > On Fri, 16 Jan 2015 15:42:37 +0100, Ayoub Zaki > > <ayoub.zaki(a)googlemail.com> wrote: > > > Hello list, > > > > > > I'm using u-boot-2014.10 and trying to build it with LCD support for the > > > Beaglebone black to include a Boot logo image. > > > It seems that spl hangs while fat loading a 2.8MB sized u-boot.img ! > > > I reduced the the logo header file and rebuild u-boot, that worked for a > > > 1.6MB sized u-boot.img. > > > Is there any size limit for u-boot ? how to increase the memory allocated > > > by spl ? > > > > There should not be a size limit for SPL fat load. > > > > What may happen is that SPL code is overwritten before it exits, or > > U-Boot itself is corrupted after being loaded. > > > > I assume you've seen the SPL banner and not the U-Boot one; that alone > > does not tell us whether SPL or U-Boot did hang. Can you build U-boot > > with debug enabled? If this results in too big an SPL image, then try > > and at least enable debug for the image chainloading parts, so that you > > can see how far SPL code gets run. > > > > > Thanks you. > > > > No problem. > > > > Amicalement, > > -- > > Albert.

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[U-Boot] [PATCH] rockchip: Set up default PWM flags
by Simon Glass 06 Oct '17

06 Oct '17

At present if the PWM set_invert() method is not called then the flags are not set up and the driver does not work properly. Fix this by setting up the default flags when probing. Signed-off-by: Simon Glass <sjg(a)chromium.org> Fixes: 874ee59 (rockchip: pwm: implement pwm_set_invert()) --- drivers/pwm/rk_pwm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index f3b2f7615d..5d78d4a67d 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -92,6 +92,7 @@ static int rk_pwm_probe(struct udevice *dev) return -EINVAL; } priv->freq = clk_get_rate(&clk); + priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE; return 0; } -- 2.13.0.219.gdb65acc882-goog

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[U-Boot] [PATCH] drivers: pci: imx: add imx_pcie_remove function
by Tim Harvey 05 Oct '17

05 Oct '17

There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/imx-common/cpu.c | 3 +++ drivers/pci/pcie_imx.c | 38 ++++++++++++++++++++++++++++++++++++++ include/pci.h | 4 ++++ 3 files changed, 45 insertions(+) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 40fe813..74bdd24 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -275,6 +275,9 @@ u32 get_ahb_clk(void) void arch_preboot_os(void) { +#if defined(CONFIG_PCIE_IMX) + imx_pcie_remove(); +#endif #if defined(CONFIG_CMD_SATA) sata_stop(); #if defined(CONFIG_MX6) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 732d59d..eab0a2b 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -42,6 +42,9 @@ /* PCIe Port Logic registers (memory-mapped) */ #define PL_OFFSET 0x700 +#define PCIE_PL_PFLR (PL_OFFSET + 0x08) +#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) +#define PCIE_PL_PFLR_FORCE_LINK (1 << 15) #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) @@ -445,6 +448,36 @@ static int imx6_pcie_assert_core_reset(void) /* Power up PCIe PHY */ setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); #else + /* + * If the bootloader already enabled the link we need some special + * handling to get the core back into a state where it is safe to + * touch it for configuration. As there is no dedicated reset signal + * wired up for MX6QDL, we need to manually force LTSSM into "detect" + * state before completely disabling LTSSM, which is a prerequisite + * for core configuration. + * + * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong + * indication that the bootloader activated the link. + */ + if (is_mx6dq()) { + u32 val, gpr1, gpr12; + + gpr1 = readl(&iomuxc_regs->gpr[1]); + gpr12 = readl(&iomuxc_regs->gpr[12]); + if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) && + (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) { + val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR); + val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; + val |= PCIE_PL_PFLR_FORCE_LINK; + + imx_pcie_fix_dabt_handler(true); + writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR); + imx_pcie_fix_dabt_handler(false); + + gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2; + writel(val, &iomuxc_regs->gpr[12]); + } + } setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); #endif @@ -652,6 +685,11 @@ void imx_pcie_init(void) } } +void imx_pcie_remove(void) +{ + imx6_pcie_assert_core_reset(); +} + /* Probe function. */ void pci_init_board(void) { diff --git a/include/pci.h b/include/pci.h index d3c955e..c8ef997 100644 --- a/include/pci.h +++ b/include/pci.h @@ -754,6 +754,10 @@ int pci_last_busno(void); extern void pci_mpc85xx_init (struct pci_controller *hose); #endif +#ifdef CONFIG_PCIE_IMX +extern void imx_pcie_remove(void); +#endif + #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) /** * pci_write_bar32() - Write the address of a BAR including control bits -- 2.7.4

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[U-Boot] [PATCH 00/22] mmc: Add support for HS200 and UHS modes
by Jean-Jacques Hiblot 16 Sep '17

16 Sep '17

This series brings support for HS200 and UHS modes to the mmc core. It has been tested with the hsmmc driver on several platforms (DRA7, AM57x, AM437x, beaglebone black). Some modifications are required in the host driver to take advantage of this (voltage switching, tuning). The changes to the host driver will be posted a another series as this one is already long enough. The series starts with a small refactoring of th sd/mmc startup. The first 4 commits are mostly moving code around with little or no functionnal change. Then the notion of "mode" is introduced. Until now, this information wasn't kept in struct mmc. Only the clock and a flag for ddr was kept. Later the mode information will be used to select the clock frequency, the ddr flag and the tuning procedure. It will be also be check against the host capabilities. Then comes the big refactoring job in: "mmc: refactor MMC startup to make it easier to support new modes" and "mmc: refactor SD startup to make it easier to support new modes" Since the number of modes is increasing, it makes sense to try them in a more organized way. those commits use a list of supported modes and iterate through them to find the best working one. It also allows to switch more easilly from one mode to another (switching from HS200 to DDR52 to access boot partitions for example) Then there are a couple of new callback added to: - enable/disable Vdd - check if the card is busy (used during UHS voltage switching) - select the IO voltage Then Power cycle is added. Without power cycle, if a UHS card fails to enumerate in UHS mode, it can't fall back to high speed mode and card enumeration will fail. And finally the last commits add the support for HS200 and UHS. I haven't been able to test the UHS SDR104 mode by lack of compatible sdcard. With this in place and the required changes in the HSMMC (including DAM), we observe significant improvements in the performances on a DRA7 evm: eMMC HS200: 130 MB/s eMMC DDR52: 80 MB/s sd SDR50: 80 MB/s cheers, Jean-Jacques Jean-Jacques Hiblot (18): mmc: split mmc_startup() mmc: move the MMC startup for version above v4.0 in a separate function mmc: make ext_csd part of struct mmc mmc: add a function to read and test the ext csd (mmc >= 4) mmc: introduces mmc modes. mmc: Add a fonction to dump the mmc capabilities mmc: use mmc modes to select the correct bus speed cmd: mmc: display the mode name and current bus speed in the mmc info mmc: refactor SD startup to make it easier to support new modes mmc: refactor MMC startup to make it easier to support new modes mmc: make mmc_set_ios() return status mmc: add power cyle support in mmc core mmc: add a new mmc parameter to disable mmc clock mmc: Add a execute_tuning() callback to the mmc operations. mmc: add HS200 support in MMC core mmc: Add a new callback function to check if the card is busy mmc: Add support for UHS modes mmc: Change mode when switching to a boot partition Kishon Vijay Abraham I (3): mmc: Enable signal voltage to be selected from mmc core mmc: Add a new callback function to enable/disable vdd mmc: disable the mmc clock during power off Vignesh R (1): mmc: Retry some MMC cmds on failure cmd/mmc.c | 3 +- drivers/mmc/fsl_esdhc.c | 2 +- drivers/mmc/mmc-uclass.c | 42 ++ drivers/mmc/mmc.c | 1220 +++++++++++++++++++++++++++++++++------------- include/mmc.h | 138 +++++- 5 files changed, 1058 insertions(+), 347 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 01/14] armv7: Add workaround for USB erratum A-009008
by yinbo.zhu 14 Sep '17

14 Sep '17

From: Suresh Gupta <suresh.gupta(a)freescale.com> USB High Speed (HS) EYE Height Adjustment This patch is adding the erratum for LS1021. Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu(a)nxp.com> --- arch/arm/cpu/armv7/ls102xa/Kconfig | 2 ++ arch/arm/cpu/armv7/ls102xa/soc.c | 12 ++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index b61f3cd..df539e9 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -14,6 +14,8 @@ config ARCH_LS1021A select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE + select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009942 menu "LS102xA architecture" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 52fb6f8..c54daee 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void) return major; } +static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4); + val &= ~(0xF << 6); + out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6)); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + void s_init(void) { } @@ -146,6 +156,8 @@ int arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20042); + /* Erratum */ + erratum_a009008(); return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index c34fd63..f474cfd 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -172,6 +172,10 @@ struct ccsr_gur { #define SCFG_PMCINTECR_ETSECERRG0 0x00080000 #define SCFG_PMCINTECR_ETSECERRG1 0x00040000 #define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 +#define SCFG_BASE 0x01570000 +#define SCFG_USB3PRM1CR 0x070 +#define USB_TXVREFTUNE 0x9 + /* Supplemental Configuration Unit */ struct ccsr_scfg { -- 2.1.0.27.g96db324

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