April 2017 - U-Boot

[U-Boot] [PATCH v2] imx: i.mx6q: add the initial support for LogicPD i.MX6Q SOM
by Adam Ford 03 Apr '17

03 Apr '17

Logic PD has an i.MX6Q system on module (SOM) with a development kit. The SOM has a built-in microSD socket, DDR and NAND flash. The development kit has an SMSC Ethernet PHY, serial debug port and a variety of peripherals. This have been verified to boot the i.MX6Q version over either SD on the development kit or NAND built into the SOM. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- Changes in V2: - Alphabetize the modified Kconfig file - Clean up README file. - Elminate fdt_high and initrd_high and add bootm_size - Changed MTDPARTS_DEFAULT to increase the kernel size to 16MB - Cleaned up the mx6q_2x_MT41K512M16HA.cfg to include headers, replace hard-coded addresses with human-readable ones, and remove dead code - Updated mx6q_2x_MT41K512M16HA.cfg to use BOOT_OFFSET since SD and NAND have the same offset - Removed 'ifdef' references that were always true. - Removed CPU references that didn't exist. - And made local variables static - Add reference to worked used to derrive this code diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 190e5c6..507c70e 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -155,6 +155,13 @@ config TARGET_MX6CUBOXI select BOARD_LATE_INIT select SUPPORT_SPL +config TARGET_MX6LOGICPD + bool "mx6logicpd" + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select DM + select DM_THERMAL + config TARGET_MX6QARM2 bool "mx6qarm2" @@ -404,6 +411,7 @@ source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" source "board/liebherr/mccmon6/Kconfig" +source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig new file mode 100644 index 0000000..f5e2f58 --- /dev/null +++ b/board/logicpd/imx6/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6LOGICPD + +config SYS_BOARD + default "imx6" + +config SYS_VENDOR + default "logicpd" + +config SYS_CONFIG_NAME + default "imx6_logic" + +endif diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS new file mode 100644 index 0000000..5db7d2c --- /dev/null +++ b/board/logicpd/imx6/MAINTAINERS @@ -0,0 +1,6 @@ +MX6LOGICPD BOARD +M: Adam Ford <aford173(a)gmail.com> +S: Maintained +F: board/logicpd/imx6/ +F: include/configs/imx6_logic.h +F: configs/imx6q_logic_defconfig diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile new file mode 100644 index 0000000..397bc5e --- /dev/null +++ b/board/logicpd/imx6/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg(a)denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := imx6logic.o +obj-$(CONFIG_POWER_PFUZE100) += ../../freescale/common/pfuze.o + diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README new file mode 100644 index 0000000..7c9b6bd --- /dev/null +++ b/board/logicpd/imx6/README @@ -0,0 +1,37 @@ +U-Boot for LogicPD i.MX6 Development Kit +---------------------------------------- + +This file contains information for the port of U-Boot to the Logic PD Development kit. + +Logic PD has an i.MX6 System On Module (SOM) and a correspondong development +board. SOM has a built-in microSD socket, DDR and NAND flash. The development kit has +an SMSC Ethernet PHY, serial debug port and a variety of peripherals. + +On the intial release, the SOM came with an i.MX6D and i.MX6Q. + +For more details about Logic PD i.MX6 Development kit, visit: +https://www.logicpd.com/ + +Building U-Boot for Logic PD Development Kit +-------------------------------------------- +To build U-Boot for the Dual and Quad variants: + + make imx6q_logic_defconfig + make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux- + + +Flashing U-Boot into the SD card +-------------------------------- + +See README.imximage for details on booting from SD + +Flashing U-Boot into NAND +------------------------- +Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following: +with: + + kobs-ng init -v -x u-boot.imx + +Additional Support Documentation can be found at: +https://support.logicpd.com/ + diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c new file mode 100644 index 0000000..0efa65c --- /dev/null +++ b/board/logicpd/imx6/imx6logic.c @@ -0,0 +1,343 @@ +/* + * Copyright (C) 2017 Logic PD, Inc. + * + * Author: Adam Ford <aford173(a)gmail.com> + * + * Based on SabreSD by Fabio Estevam <fabio.estevam(a)freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <linux/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../../freescale/common/pfuze.h" +#include <asm/arch/mx6-ddr.h> +#include <usb.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL ( \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_60ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_SLOW) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PMIC 2 +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* LAN8710A PHY Reset */ + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + /* LAN8710A nINT Signal */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Set GPIO_16 as ENET_REF_CLK_OUT */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + /* Ensure nINT is input */ + gpio_direction_input(IMX_GPIO_NR(4, 7)); + + /* Reset LAN8710A PHY */ + gpio_direction_output(IMX_GPIO_NR(4, 9) , 0); + udelay(150); + gpio_set_value(IMX_GPIO_NR(4, 9), 1); + mdelay(50); +} + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + + +static struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(3, 18) + } +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); +} + +static iomux_v3_cfg_t const pmic_pads[] = { + MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_pmic_pins(void) +{ + imx_iomux_v3_setup_multiple_pads(pmic_pads, ARRAY_SIZE(pmic_pads)); +} + +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + +static void setup_nand_pins(void) +{ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); +} + + +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR}, +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(6, 16) +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 SOM + * mmc1 Baseboard + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers"); + printf("(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_pmic_pins(); + setup_nand_pins(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + enable_fec_anatop_clock(0, ENET_50MHZ); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, &i2c_pad_info3); + return 0; +} + +int power_init_board(void) +{ + struct pmic *p; + + p = pfuze_common_init(I2C_PMIC); + if (!p) + return -ENODEV; + + return pfuze_mode_init(p, APS_PFM); +} + +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {NULL, 0}, +}; + + +int board_late_init(void) +{ + add_board_boot_modes(board_boot_modes); + setenv("board_name", "imx6logic"); + + if (is_mx6dq()) { + setenv("board_rev", "MX6DQ"); + setenv("fdt_file", "imx6q-logicpd.dtb"); + } + return 0; +} + +int checkboard(void) +{ + puts("Board: Logic PD i.MX6 SOM\n"); + return 0; +} diff --git a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg new file mode 100644 index 0000000..b206548 --- /dev/null +++ b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2017 Logic PD, Inc. + * Adam Ford <aford173(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#include <asm/imx-common/imximage.cfg> + +/* image version */ +IMAGE_VERSION 2 + +BOOT_OFFSET FLASH_OFFSET_STANDARD + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch-mx6/mx6-ddr.h" +#include "asm/arch-mx6/iomux.h" +#include "asm/arch-mx6/crm_regs.h" + +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 +DATA 4, CCM_CCGR5, 0x0F0000F3 +DATA 4, CCM_CCGR6, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 MX6_IOMUXC_GPR4 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 MX6_IOMUXC_GPR6 0x007F007F +DATA 4 MX6_IOMUXC_GPR7 0x007F007F diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig new file mode 100644 index 0000000..1526d38 --- /dev/null +++ b/configs/imx6q_logic_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6LOGICPD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="i.MX6 Logic # " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_NAND_MXS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h new file mode 100644 index 0000000..cb09407 --- /dev/null +++ b/include/configs/imx6_logic.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2017 Logic PD, Inc. + * + * Configuration settings for the LogicPD i.MX6 SOM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX6LOGIC_CONFIG_H +#define __IMX6LOGIC_CONFIG_H + +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONSOLE_DEV "ttymxc0" + +#include <config_distro_defaults.h> +#include "mx6_common.h" + +#define CONFIG_IMX_THERMAL + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_MXC_UART + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* Dev kit SD card */ + +/* Ethernet Configs */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +/* Command definition */ +#define CONFIG_CMD_BMODE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_file=rootfs.cpio.uboot\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONSOLE_DEV "\0" \ + "mmcdev=1\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate}" \ + " root=${mmcroot} ${mtdparts}\0" \ + "nandargs=setenv bootargs console=${console},${baudrate}" \ + " ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \ + "ramargs=setenv bootargs console=${console},${baudrate}" \ + " root=/dev/ram rw ${mtdparts}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...;" \ + " source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \ + " setenv kernelsize ${filesize}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdiskaddr} ${ramdisk_file};" \ + " setenv ramdisksize ${filesize}\0" \ + "mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \ + " run loadfdt; bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcramboot=run ramargs; run loadimage;" \ + " run loadfdt; run loadramdisk;" \ + " bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \ + "nandboot=echo Booting from nand ...; " \ + " run nandargs;" \ + " nand read ${loadaddr} kernel ${kernelsize};" \ + " nand read ${fdt_addr} dtb;" \ + " bootz ${loadaddr} - ${fdt_addr}\0" \ + "nandramboot=echo Booting RAMdisk from nand ...; " \ + " nand read ${ramdiskaddr} fs ${ramdisksize};" \ + " nand read ${loadaddr} kernel ${kernelsize};" \ + " nand read ${fdt_addr} dtb;" \ + " run ramargs;" \ + " bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs" \ + " ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "autoboot=mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#define CONFIG_BOOTCOMMAND \ + "run autoboot" + +#define CONFIG_ARP_TIMEOUT 200UL + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x400000 +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE + + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C2 +#define CONFIG_SYS_I2C_MXC_I2C3 +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x8 + +/* NAND flash command */ + +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +/* MTD device */ +# define CONFIG_MTD_DEVICE +# define CONFIG_CMD_MTDPARTS +# define CONFIG_MTD_PARTITIONS +# define MTDIDS_DEFAULT "nand0=gpmi-nand" +# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:4m(uboot)," \ + "1m(env),16m(kernel),1m(dtb),-(fs)" + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +#endif /* __IMX6LOGIC_CONFIG_H */ -- 2.7.4

2 2

[U-Boot] [PATCH v6 1/1] usb: gadget: avoid variable name clipping in cb_getvar
by Nicolas le bayon 03 Apr '17

03 Apr '17

From: Nicolas Le Bayon <nlebayon(a)gmail.com> Instead of using a fixed-size array to store variable name, preferring a dynamic allocation treats correctly all variable name lengths. Variable names are growing through releases and features. By this way, name clipping is prevented. Signed-off-by: Nicolas Le Bayon <nlebayon(a)gmail.com> Reviewed-by: Marek Vasut <marex(a)denx.de> --- Changes in v2: - instead of using a bigger fixed size, use malloc to fit with size needs Changes in v3: - v2 was an error (intermediate version), so propose a complete one Changes in v4: - be more explicit and detailed in label and description fields - remove intermediate variable only used one time - be more explicit in error message - fix indent issue Changes in v5: - drop an unuseful error() call Changes in v6: - add Marek review approval drivers/usb/gadget/f_fastboot.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_ fastboot.c index 2160b1c..7cd6d24 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -432,9 +432,15 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) else strcpy(response, "FAILValue not set"); } else { - char envstr[32]; + char *envstr; - snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd); + envstr = malloc(strlen("fastboot.") + strlen(cmd) + 1); + if (!envstr) { + fastboot_tx_write_str("FAILmalloc error"); + return; + } + + sprintf(envstr, "fastboot.%s", cmd); s = getenv(envstr); if (s) { strncat(response, s, chars_left); @@ -442,6 +448,8 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) printf("WARNING: unknown variable: %s\n", cmd); strcpy(response, "FAILVariable not implemented"); } + + free(envstr); } fastboot_tx_write_str(response); } -- 1.9.1

3 4

[U-Boot] [PATCH 00/10] sunxi: Add basic PSCI support to enable SMP on the A80's first cluster
by Chen-Yu Tsai 03 Apr '17

03 Apr '17

Hi everyone, This series adds basic PSCI support for the A80 to enable SMP on the first cluster. This at least allows people to use more than one core. The term "basic" is used because the series does not add support for multi-cluster cache and power management. The PSCI code is based on existing code for all the single cluster SoCs, and the kernel patches for MCPM SMP I did some time ago. Unfortunately only SMP works at this time. The last patch does not actually work. While the system is indeed booted non-secure, tested by trying to write to secure SRAM and the results not sticking, reads from the GIC CPU interface shows that it's still returning the secure copy of registers, and since we use a secure monitor FIQ to do core power down, the FIQ gets passed to the kernel. The patch is included so people with in-depth ARM knowledge could probably help work out what is wrong. Regards ChenYu Chen-Yu Tsai (10): ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80 sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80 sunxi: Add base address of secure SRAM B for sun9i/A80 sunxi: Use secure SRAM B for secure RAM for sun9i/A80 sunxi: Add PRCM register definition for sun9i/A80 sunxi: Add CPUCFG register definitions for sun9i/A80 sunxi: Add support for TZPC on sun9i/A80 sunxi: Add basic PSCI implementation for A80 sunxi: Enable PSCI on sun9i/A80 sunxi: Add PSCI core power off support for A80's first cluster arch/arm/cpu/armv7/Kconfig | 1 + arch/arm/cpu/armv7/sunxi/Makefile | 5 + arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 322 +++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/tzpc.c | 6 + arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 5 + arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 51 ++++ arch/arm/include/asm/arch-sunxi/prcm_sun9i.h | 55 +++++ arch/arm/include/asm/arch-sunxi/tzpc.h | 4 + arch/arm/mach-sunxi/board.c | 3 +- board/sunxi/Kconfig | 4 + include/configs/sun9i.h | 4 + 11 files changed, 459 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h -- 2.10.2

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[U-Boot] [PATCH 0/4] Switch odroid to use distro_bootcmd.
by Vagrant Cascadian 03 Apr '17

03 Apr '17

Using distro_bootcmd standardizes board behavior across many platforms. This is particularly useful for distributions supporting multiple boards without requiring custom configuration for each board. There are a few changes needed to support distro_bootcmd, such as fixing the default value for the console setting, increasing the environment size, and allowing distro bootcmd to set the default bootdelay. These patches have been used in Debian's u-boot packaging since May of 2016. Vagrant Cascadian (4): Fix default console on odroid to only specify the device, as "console=" is redundant with the boot environment. Increase the default environment size on odroid, as config_distro_bootcmd requires a more space for the environment. Switch odroid to use config_distro_bootcmd. Inherit default value for bootdelay from distro_bootcmd on odroid. include/configs/odroid.h | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) -- 2.11.0

2 5

[U-Boot] [PATCH v4 0/3] arm: tegra: apalis-tk1 and ext clock loopback
by Marcel Ziswiler 03 Apr '17

03 Apr '17

This series adds support for the Toradex Apalis TK1 and introduces a new option to disable the external clock loopback on SDMMC3. The whole series is also available here: http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next Changes in v4: - Re-based. - Drop patches 2 and 3: mmc: tegra: move CONFIG_TEGRA_MMC from headers to defconfigs mmc: tegra: introduce CONFIG_TEGRA_MMC to Kconfig in favor of commit 1d2c0506d31a9997e5ffc22e90942902f673b107 mmc: move more driver config options to Kconfig from Masahiro. - Meld patch 6 apalis-tk1: clean-up defconfig into first one. - Add distro boot fallback. - Enable FIT and device tree overlay support. - Explicitly drop EFI loader support. - Re-based. Changes in v3: - Changes involved now dropped patches. Changes in v2: - Added Simon's reviewed-by. - Added TODO(email) as suggested by Simon so it is clear this is temporary and will be moved to device tree controlled approach once proper kernel integration made it mainline. Marcel Ziswiler (3): arm: tegra: initial support for apalis tk1 mmc: tegra: allow disabling external clock loopback apalis-tk1: disable external clock loopback on SDMMC3 arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra124-apalis.dts | 2203 ++++++++++++++++++++ arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 + arch/arm/mach-tegra/tegra124/Kconfig | 7 + board/toradex/apalis-tk1/Kconfig | 30 + board/toradex/apalis-tk1/MAINTAINERS | 7 + board/toradex/apalis-tk1/Makefile | 5 + board/toradex/apalis-tk1/apalis-tk1.c | 175 ++ board/toradex/apalis-tk1/as3722_init.c | 117 ++ board/toradex/apalis-tk1/as3722_init.h | 41 + .../toradex/apalis-tk1/pinmux-config-apalis-tk1.h | 287 +++ configs/apalis-tk1_defconfig | 48 + drivers/mmc/Kconfig | 11 + drivers/mmc/tegra_mmc.c | 16 + include/configs/apalis-tk1.h | 176 ++ 15 files changed, 3126 insertions(+) create mode 100644 arch/arm/dts/tegra124-apalis.dts create mode 100644 board/toradex/apalis-tk1/Kconfig create mode 100644 board/toradex/apalis-tk1/MAINTAINERS create mode 100644 board/toradex/apalis-tk1/Makefile create mode 100644 board/toradex/apalis-tk1/apalis-tk1.c create mode 100644 board/toradex/apalis-tk1/as3722_init.c create mode 100644 board/toradex/apalis-tk1/as3722_init.h create mode 100644 board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h create mode 100644 configs/apalis-tk1_defconfig create mode 100644 include/configs/apalis-tk1.h -- 2.9.3

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[U-Boot] [PATCH] odroid: dts: change the buck8 min-microvolt value
by Jaehoon Chung 03 Apr '17

03 Apr '17

Change the buck8's min-microvolt to 750000. Whent thor protocol is used, board_usb_init() should be tried to set to 750000. But it was returned -EINVAL, because '750000' too lower than 2850000. (thor command doesn't work fine because of this problem.) Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/arm/dts/exynos4412-odroid.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index 188cb93..8710747 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -213,7 +213,7 @@ buck8_reg: BUCK8 { regulator-name = "VCC_P3V3_2.85V"; - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <750000>; regulator-max-microvolt = <3300000>; }; }; -- 2.10.2

2 1

[U-Boot] [PATCH 0/6] trats: convert to driver model
by Jaehoon Chung 03 Apr '17

03 Apr '17

This patchset is for converting to driver model. This task is working in progress. Some codes should be remained to legacy mode, it will be converted in future. Jaehoon Chung (6): configs: trats: enable the CONFIG_DM_PMIC and PMIC_MAX8997 board: samsung: trats: remove the unnecessary codes board: samsung: trats: convert to driver model for controlling phy arm: dts: trats: add i2c_fg node for fuelgauge board: samsung: trats: remove the i2c_init function configs: trats: enable the CONFIG_DM_I2C_GPIO arch/arm/dts/exynos4210-trats.dts | 9 ++ board/samsung/trats/trats.c | 249 ++++++++------------------------------ configs/trats_defconfig | 4 + 3 files changed, 62 insertions(+), 200 deletions(-) -- 2.10.2

4 11

[U-Boot] [PATCH v3 00/19] Add Intel Arria 10 SoC support
by Ley Foon Tan 03 Apr '17

03 Apr '17

This is the 3rd version of patchset to adds support for Intel Arria 10 SoC. This version mainly resolved comments from Marek in [v2]. This is initial patchset enables the basic support for Arria 10 and other features will come after this. This series is working on top of “arm: socfpga: Move to using distro boot” series [1] from Dalon Westergreen. [1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg239560.html v2 -> v3 changes: ----------------- - Drop "[PATCH v2 02/20] arm: socfpga: Update clock for Gen5" in [v2] from this A10 patch series, since it is non Arria 10 related. - Add socfpga_ prefix for exported functions in reset driver. - Check return value from wait_for_bit(). - Remove extra parenthesis around statement - Refactor cm_calc_safe_pll_numer() clock driver. - Use BIT(n) for bit shifting. - Resolved warnings and errors from checkpatch.pl. Patchset history ---------------- [v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg240052.html [v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg241249.html Ley Foon Tan (19): arm: socfpga: Restructure clock manager driver arm: socfpga: Restructure reset manager driver arm: socfpga: Restructure system manager arm: socfpga: Restructure misc driver arm: socfpga: Add A10 macros arm: socfpga: Add reset driver support for Arria 10 arm: socfpga: Add clock driver for Arria 10 arm: socfpga: Add system manager for Arria 10 arm: socfpga: Add sdram header file for Arria 10 arm: socfpga: Add misc support for Arria 10 arm: socfpga: Add pinmux for Arria 10 fdt: Add compatible strings for Arria 10 arm: dts: Add dts and dtsi for Arria 10 arm: socfpga: Add SPL support for Arria 10 drivers: fpga: Add compile switch for Gen5 only registers arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig arm: socfpga: Add config and defconfig for Arria 10 arm: socfpga: Add board files for the Arria10 arm: socfpga: Enable build for Arria 10 arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria10.dtsi | 859 +++++++++++++++ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 30 + .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 481 +++++++++ arch/arm/mach-socfpga/Kconfig | 10 + arch/arm/mach-socfpga/Makefile | 41 +- arch/arm/mach-socfpga/clock_manager.c | 525 +--------- arch/arm/mach-socfpga/clock_manager_arria10.c | 1096 ++++++++++++++++++++ .../{clock_manager.c => clock_manager_gen5.c} | 104 +- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 317 +----- .../include/mach/clock_manager_arria10.h | 224 ++++ .../mach/{clock_manager.h => clock_manager_gen5.h} | 151 +-- arch/arm/mach-socfpga/include/mach/misc.h | 31 + arch/arm/mach-socfpga/include/mach/pinmux.h | 15 + arch/arm/mach-socfpga/include/mach/reset_manager.h | 50 +- .../include/mach/reset_manager_arria10.h | 144 +++ .../mach-socfpga/include/mach/reset_manager_gen5.h | 47 + arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 380 +++++++ .../arm/mach-socfpga/include/mach/system_manager.h | 202 ++-- .../include/mach/system_manager_arria10.h | 81 ++ .../{system_manager.h => system_manager_gen5.h} | 39 +- arch/arm/mach-socfpga/misc.c | 361 +------ arch/arm/mach-socfpga/misc_arria10.c | 258 +++++ arch/arm/mach-socfpga/{misc.c => misc_gen5.c} | 149 +-- arch/arm/mach-socfpga/pinmux_arria10.c | 96 ++ arch/arm/mach-socfpga/reset_manager.c | 93 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 389 +++++++ .../{reset_manager.c => reset_manager_gen5.c} | 51 +- arch/arm/mach-socfpga/spl.c | 74 +- .../{system_manager.c => system_manager_gen5.c} | 6 +- board/altera/arria10-socdk/Kconfig | 18 + board/altera/arria10-socdk/Makefile | 7 + board/altera/arria10-socdk/socfpga.c | 7 + configs/socfpga_arria10_defconfig | 28 + drivers/Kconfig | 2 + drivers/ddr/Kconfig | 1 + drivers/ddr/altera/Kconfig | 6 + drivers/ddr/altera/Makefile | 4 +- drivers/fpga/socfpga.c | 6 + include/configs/socfpga_arria10_socdk.h | 66 ++ include/configs/socfpga_common.h | 33 +- include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 ++ include/fdtdec.h | 8 + lib/fdtdec.c | 8 + 45 files changed, 4824 insertions(+), 1786 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria10.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (88%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h copy arch/arm/mach-socfpga/include/mach/{clock_manager.h => clock_manager_gen5.h} (80%) create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_arria10.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_arria10.h copy arch/arm/mach-socfpga/include/mach/{system_manager.h => system_manager_gen5.h} (73%) create mode 100644 arch/arm/mach-socfpga/misc_arria10.c copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (73%) create mode 100644 arch/arm/mach-socfpga/pinmux_arria10.c create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (75%) rename arch/arm/mach-socfpga/{system_manager.c => system_manager_gen5.c} (94%) create mode 100644 board/altera/arria10-socdk/Kconfig create mode 100644 board/altera/arria10-socdk/Makefile create mode 100644 board/altera/arria10-socdk/socfpga.c create mode 100644 configs/socfpga_arria10_defconfig create mode 100644 drivers/ddr/Kconfig create mode 100644 drivers/ddr/altera/Kconfig create mode 100644 include/configs/socfpga_arria10_socdk.h create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h -- 2.2.0

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[U-Boot] fatls returncode
by Mirza Krak 03 Apr '17

03 Apr '17

Hi. I am running U-boot 2015.04 and experiencing some issues with "fatls" command. We use the "fatls" command to detect if there is an USB storage device plugged in the port during boot (might be better ways of doing this). So on boot we have: fatls usb 0:1 && <do something> Normally "fatls" returns "0" when it does a successful list. But we have found a case where it does not even though everything seems to work fine. Below is a log with debug enabled (obfuscated filenames since I got this flash drive from a customer). MX-4 C61 # fatls usb 0:1 VFAT Support enabled FAT32, fat_sect: 1146, fatlength: 7619 Rootdir begins at cluster: 2, sector: 16384, offset: 800000 Data begins at: 16368 Sector size: 512, cluster size: 8 FAT read(sect=16384, cnt:8), clust_size=8, DIRENTSPERBLOCK=16 system volume information/ bin/ boot/ etc/ i4m/ lib/ sbin/ share/ 1530 file1.sh 15542 file2.sh 1745 file3.sh 4609 file4.sh END LOOP: buffer_blk_cnt=0 clust_size=8 1547 file5.sh 22361 file6.sh 385078 file7.sh 33279 file8.sh 1152054 file9.sh 158132 file10.sh 1473 file11.sh 9739 file12.sh 318780 file13.sh END LOOP: buffer_blk_cnt=1 clust_size=8 34027520 file14.sh 1246 file15.sh 1246 file16.sh END LOOP: buffer_blk_cnt=2 clust_size=8 END LOOP: buffer_blk_cnt=3 clust_size=8 END LOOP: buffer_blk_cnt=4 clust_size=8 END LOOP: buffer_blk_cnt=5 clust_size=8 END LOOP: buffer_blk_cnt=6 clust_size=8 END LOOP: buffer_blk_cnt=7 clust_size=8 FAT32: entry: 0x0002 = 2, offset: 0x0002 = 2 FAT32: ret: 0fffffff, offset: 0002 16 file(s), 8 dir(s) MX-4 C61 # echo $? 1 Even though the file list seems to be OK, the return code indicates an error. I am wondering if we need to set "ret = 0" in below code-path (which the exit path in above output) fs/fat/fat.c: 1139 /* If end of rootdir reached */ 1140 if (rootdir_end) { 1141 if (dols == LS_ROOT) { 1142 printf("\n%d file(s), %d dir(s)\n\n", 1143 files, dirs); 1144 *size = 0; 1145 } 1146 goto exit; 1147 } -- Med Vänliga Hälsningar / Best Regards ******************************************************************* Mirza Krak Host Mobility AB mirza.krak(a)hostmobility.com Anders Personsgatan 12, 416 64 Göteborg Sweden http://www.hostmobility.com Direct: +46 31 31 32 704 Phone: +46 31 31 32 700 Fax: +46 31 80 67 51 Mobile: +46 730 28 06 22 *******************************************************************

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[U-Boot] [PATCH] net: eth_common: Don't use %pM when USE_TINY_PRINTF is enabled
by Vignesh R 03 Apr '17

03 Apr '17

Tiny printf doesn't support %pM, so when CONFIG_USE_TINY_PRINTF is enabled use %x to manually print MAC address. Signed-off-by: Vignesh R <vigneshr(a)ti.com> --- net/eth_common.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/net/eth_common.c b/net/eth_common.c index 58fa29577102..cd67a21585c6 100644 --- a/net/eth_common.c +++ b/net/eth_common.c @@ -37,7 +37,14 @@ int eth_setenv_enetaddr(const char *name, const uchar *enetaddr) if (eth_getenv_enetaddr(name, (uchar *)buf)) return -EEXIST; +#ifndef CONFIG_USE_TINY_PRINTF sprintf(buf, "%pM", enetaddr); +#else + sprintf(buf, "%x:%x:%x:%x:%x:%x", (unsigned int)enetaddr[0], + (unsigned int)enetaddr[1], (unsigned int)enetaddr[2], + (unsigned int)enetaddr[3], (unsigned int)enetaddr[4], + (unsigned int)enetaddr[5]); +#endif return setenv(name, buf); } -- 2.11.0

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