March 2017 - U-Boot

[U-Boot] [PATCH 0/8] Stop AXP from crashing when enabeling LDO3
by Olliver Schinagl 21 Apr '17

21 Apr '17

Hi list, When powering up an AXP209, the default value for LDO3 output is enabled. This works fine. However if for whatever reason, LDO3 is disabled, for example by OS during reboot and u-boot enables LDO3 again, the PMIC shutsdown (without setting an interrupt) causing the board to hang. This behavior has been seen from Linux as well, u-boot disables LDO3 as a default value, the kernel enables it per its DTS, the kernel hangs as the PMIC gets shut down. The root cause is that some boards have to high capacitance on the LDO3 output port causing inrush currents exceeding the maximum of the AXP209. The fix is to turn on the LDO3 at the lowest possible voltage and then set the final voltage. If the capacitance is really big (due to a connected device for example) the AXP209 also features VRC, or Voltage Rate Control, which allows the voltage ramp up to be even slower. This patch series implements the above with a few tiny, cleanups I ran into underway. The initial discussion with some scope screenshots can be found in the linux-sunxi mailing list [0]. Signed-off-by: Olliver Schinagl <oliver(a)schinagl.nl> [0] https://groups.google.com/forum/m/#!topic/linux-sunxi/EDvEsbHHqQI Olliver Schinagl (8): sunxi: board: Print error after power initialization fails sunxi: pmic_bus: Decrease boot time by not writing duplicate data power: axp209: Use BIT() macro power: axp209: Define the chip version mask power: axp209: Reduce magic values by adding defines for LDO[234] power: axp209: Add support for voltage rate control on LDO3 power: axp209: Limit inrush current for broken boards arm: sunxi: Enable inrush quirk on Olimex OLinuXino-A20-Lime2 arch/arm/mach-sunxi/pmic_bus.c | 6 ++++ board/sunxi/board.c | 14 ++++---- configs/A20-OLinuXino-Lime2_defconfig | 1 + drivers/power/Kconfig | 42 ++++++++++++++++++++++ drivers/power/axp209.c | 61 ++++++++++++++++++++++++++------ include/axp209.h | 66 ++++++++++++++++++++++++++--------- 6 files changed, 158 insertions(+), 32 deletions(-) -- 2.11.0

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[U-Boot] [PATCH 0/2] sunxi: power: Add AXP806 and AXP808 support
by Rask Ingemann Lambertsen 21 Apr '17

21 Apr '17

The X-Powers AXP806 and AXP808 PMICs are usually found on boards featuring the Allwinner A80 ARM SoC. The so far supported features are the same on the two chips. A lack of data sheets to compare makes it impossible to know for sure what the differences are, but at least two of the power-up voltages (bldo2 and dcdce) differ. Patch 1 adds support for the regulators and also sets up the master/slave mode addressing to match the way it is wired on the board. This is necessary for the PMIC to respond to register accesses and hopefully solves the AXP806 problems for the Linux 4.9 and 4.10 kernels on Cubieboard4 and A80 Optimus boards, where the AXP806 is wired for slave mode addressing. Patch 2 goes on top of "ARM: sunxi: Add defconfig for Sunchip CX-A99". It updates the defconfig for the Sunchip CX-A99 board. Now that the CPU core voltage can be controlled, the board is configured for 1200 MHz at 1020 mV, which is the maximum according to the vendor's sys_config.fex file, instead of the previous 1008 MHz at 900 mV. Rask Ingemann Lambertsen (2): sunxi: power: Add AXP806 and AXP808 support sunxi: defconfig: Sunchip CX-A99: Raise CPU voltage and clock frequency arch/arm/include/asm/arch-sunxi/pmic_bus.h | 4 + arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/pmic_bus.c | 107 ++++++++++--- board/sunxi/board.c | 20 +++ configs/Sunchip_CX-A99_defconfig | 2 + drivers/power/Kconfig | 226 +++++++++++++++++++++++++++- drivers/power/Makefile | 1 + drivers/power/axp806.c | 231 +++++++++++++++++++++++++++++ include/axp806.h | 50 +++++++ include/axp_pmic.h | 13 ++ 10 files changed, 625 insertions(+), 30 deletions(-) create mode 100644 drivers/power/axp806.c create mode 100644 include/axp806.h -- 2.10.2

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[U-Boot] [PATCH v2 00/14] STiH410-B2260: add reset, usb and fastboot support
by patrice.chotard＠st.com 21 Apr '17

21 Apr '17

From: Patrice Chotard <patrice.chotard(a)st.com> This series adds : _ add reset driver _ update existing sdhci driver to use reset framework _ add usb phy driver _ add ehci support _ add ohci support _ add xhci support _ add fastboot support With all this feature enable, it's now possible to _ boot on usb mass storage device _ boot from kernel image and dtb previously loaded using tftp _ update mmc partiton using fastboot v2: _ add Reviewed-by: Jaehoon Chung <jh80.chung(a)samsung.com> in patches 2,3 and 4 _ fix remarks done by Marek Vasut : _ patch 5 : replace bitfield_replace() by clrsetbits_le32() _ patch 6 : update error messages and add remove callback _ patch 8 : put board specific defines in a separate patch _ patch 7: use setbits_le32() instead of read, modify, write sequence and add missing parenthesis _ squash previous patches 7,9,11,12,14,16,17,18,19,20 and 21 in patch 14 Patrice Chotard (14): reset: Add STi reset support mmc: sti_sdhci: Rework sti_mmc_core_config() ARM: dts: stih410-family: Add missing reset_names for mmc1 node mmc: sti_sdhci: Use reset framework phy: Add STi phy usb support usb: ehci: Add STi ehci support usb: ohci: Add STi ohci support board: STiH410-B2260: add OHCI related defines usb: xhci: Add STi xhci support board: STiH410-B2260: add XHCI related define usb: dwc3: Add dwc3 support for STi board: STiH410-B2260: add fastboot support STiH410-B2260: enable USB Host Networking STiH410-B2260: enable USB, fastboot, reset related flags arch/arm/Kconfig | 1 + arch/arm/dts/stih407-family.dtsi | 1 + arch/arm/include/asm/arch-stih410/sys_proto.h | 11 + board/st/stih410-b2260/board.c | 44 ++++ configs/stih410-b2260_defconfig | 36 ++- drivers/mmc/sti_sdhci.c | 60 +++-- drivers/reset/Kconfig | 8 + drivers/reset/Makefile | 1 + drivers/reset/sti-reset.c | 320 ++++++++++++++++++++++++++ drivers/usb/Kconfig | 4 + drivers/usb/dwc3/Kconfig | 8 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-sti.c | 135 +++++++++++ drivers/usb/host/Kconfig | 26 +++ drivers/usb/host/Makefile | 3 + drivers/usb/host/ehci-sti.c | 115 +++++++++ drivers/usb/host/ohci-sti.c | 90 ++++++++ drivers/usb/host/xhci-sti.c | 156 +++++++++++++ drivers/usb/phy/Kconfig | 11 + drivers/usb/phy/Makefile | 1 + drivers/usb/phy/sti_phy_usb.c | 153 ++++++++++++ include/configs/stih410-b2260.h | 16 ++ include/dwc3-sti-uboot.h | 50 ++++ 23 files changed, 1225 insertions(+), 26 deletions(-) create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h create mode 100644 drivers/reset/sti-reset.c create mode 100644 drivers/usb/dwc3/dwc3-sti.c create mode 100644 drivers/usb/host/ehci-sti.c create mode 100644 drivers/usb/host/ohci-sti.c create mode 100644 drivers/usb/host/xhci-sti.c create mode 100644 drivers/usb/phy/Kconfig create mode 100644 drivers/usb/phy/sti_phy_usb.c create mode 100644 include/dwc3-sti-uboot.h -- 1.9.1

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[U-Boot] [PATCH v1 0/4] sf: add ADDR_4B for 4byte address support
by Yuan Yao 20 Apr '17

20 Apr '17

From: Yuan Yao <yao.yuan(a)nxp.com> Some new flash don't support bar but use 4bytes address to direct support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address. Yuan Yao (4): sf: add ADDR_4B for 4byte address support spi: fsl_qspi: Add 4bytes address support armv8: ls1012a: update the flash size to 64M. armv8: ls1046a: update the flash size to 64M. drivers/mtd/spi/sf_internal.h | 4 +++- drivers/mtd/spi/sf_params.c | 2 +- drivers/mtd/spi/spi_flash.c | 38 +++++++++++++++++++++++++------------- drivers/spi/fsl_qspi.c | 8 ++++++-- include/configs/ls1012a_common.h | 3 +-- include/configs/ls1046ardb.h | 3 +-- include/spi_flash.h | 1 + 7 files changed, 38 insertions(+), 21 deletions(-) -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] usb: lpc32xx: Add i2c DM support
by Sylvain Lemieux 19 Apr '17

19 Apr '17

From: Liam Beguin <lbeguin(a)tycoint.com> Add DM support for i2c functions. Signed-off-by: Liam Beguin <lbeguin(a)tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- Note: * This patch is require as part of the DM support of the LPC32xx I2C driver. All I2C drivers should be converted, to DM, by the end of June 2017. * The USB driver is supporting the DM and non-DM API. * This patch depend on the following patchset: https://lists.denx.de/pipermail/u-boot/2017-March/283672.html drivers/usb/host/ohci-lpc32xx.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c index 9245126ed6..51be4c90c7 100644 --- a/drivers/usb/host/ohci-lpc32xx.c +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -14,8 +14,10 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clk.h> +#include <asm/arch/i2c.h> #include <usb.h> #include <i2c.h> +#include <dm.h> /* OTG I2C controller module register structures */ struct otgi2c_regs { @@ -83,12 +85,35 @@ static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE; static int isp1301_set_value(int reg, u8 value) { +#ifndef CONFIG_DM_I2C return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1); +#else + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, + 1, &dev); + if (ret) + return ret; + + return dm_i2c_write(dev, reg, &value, 1); +#endif } -static void isp1301_configure(void) +static int isp1301_configure(void) { +#ifndef CONFIG_DM_I2C i2c_set_bus_num(I2C_2); +#else + int ret; + struct udevice *bus; + + ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_2, &bus); + if (ret) { + debug("%s: No bus %d\n", __func__, I2C_2); + return ret; + } +#endif /* * LPC32XX only supports DAT_SE0 USB mode @@ -116,6 +141,8 @@ static void isp1301_configure(void) /* Enable usb_need_clk clock after transceiver is initialized */ setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); + + return 0; } static int usbpll_setup(void) @@ -167,7 +194,9 @@ int usb_cpu_init(void) return ret; /* Configure ISP1301 */ - isp1301_configure(); + ret = isp1301_configure(); + if (ret) + return ret; /* setup USB clocks and PLL */ ret = usbpll_setup(); -- 2.11.0

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[U-Boot] [PATCH] Add 8 and 16-bit single register pin controller support
by James Balean 19 Apr '17

19 Apr '17

Enables the pinctrl-single driver to support 8 and 16-bit registers. Only 32-bit registers were supported previously. Signed-off-by: James Balean <james(a)balean.com.au> Cc: Felix Brack <fb(a)ltec.ch> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/pinctrl/pinctrl-single.c | 58 ++++++++++++++++++++++++++++++++++------ 1 file changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index d2dcec0..63fec8d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -24,6 +24,36 @@ struct single_fdt_pin_cfg { fdt32_t val; /* configuration register value */ }; +static fdt32_t pcs_readb(fdt32_t reg) +{ + return readb(reg); +} + +static fdt32_t pcs_readw(fdt32_t reg) +{ + return readw(reg); +} + +static fdt32_t pcs_readl(fdt32_t reg) +{ + return readl(reg); +} + +static void pcs_writeb(fdt32_t val, fdt32_t reg) +{ + writeb(val, reg); +} + +static void pcs_writew(fdt32_t val, fdt32_t reg) +{ + writew(val, reg); +} + +static void pcs_writel(fdt32_t val, fdt32_t reg) +{ + writel(val, reg); +} + /** * single_configure_pins() - Configure pins based on FDT data * @@ -46,28 +76,40 @@ static int single_configure_pins(struct udevice *dev, int count = size / sizeof(struct single_fdt_pin_cfg); int n, reg; u32 val; + fdt32_t (*pcs_read)(fdt32_t reg); + void (*pcs_write)(fdt32_t val, fdt32_t reg); - for (n = 0; n < count; n++) { + for (n = 0; n < count; n++, pins++) { reg = fdt32_to_cpu(pins->reg); if ((reg < 0) || (reg > pdata->offset)) { dev_dbg(dev, " invalid register offset 0x%08x\n", reg); - pins++; continue; } reg += pdata->base; switch (pdata->width) { + case 8: + pcs_read = pcs_readb; + pcs_write = pcs_writeb; + break; + case 16: + pcs_read = pcs_readw; + pcs_write = pcs_writew; + break; case 32: - val = readl(reg) & ~pdata->mask; - val |= fdt32_to_cpu(pins->val) & pdata->mask; - writel(val, reg); - dev_dbg(dev, " reg/val 0x%08x/0x%08x\n", - reg, val); + pcs_read = pcs_readl; + pcs_write = pcs_writel; break; default: dev_warn(dev, "unsupported register width %i\n", pdata->width); + continue; } - pins++; + + val = pcs_read(reg) & ~pdata->mask; + val |= fdt32_to_cpu(pins->val) & pdata->mask; + pcs_write(val, reg); + dev_dbg(dev, " reg/val 0x%08x/0x%08x\n", + reg, val); } return 0; } -- 2.7.4

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[U-Boot] [PATCH] armv8: ls1046aqds: added ppa support
by Yuantian Tang 19 Apr '17

19 Apr '17

PPA is used on ls1046aqds to support sleep, hotplug feature. Add PPA support to enable them. Signed-off-by: Tang Yuantian <andy.tang(a)nxp.com> --- board/freescale/ls1046aqds/ls1046aqds.c | 5 +++++ include/configs/ls1046aqds.h | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index af3f70a..470e61a 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -22,6 +22,7 @@ #include <fsl_esdhc.h> #include <fsl_ifc.h> #include <spl.h> +#include <asm/arch/ppa.h> #include "../common/vid.h" #include "../common/qixis.h" @@ -265,6 +266,10 @@ int board_init(void) if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + return 0; } diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 4b3b21e..f8f74aa 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -9,6 +9,17 @@ #include "ls1046a_common.h" +#if defined(CONFIG_FSL_LS_PPA) +#define CONFIG_ARMV8_PSCI +#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#define SEC_FIRMWARE_ERET_ADDR_REVERT + +#define CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 +#endif +#endif + #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) #define CONFIG_SYS_TEXT_BASE 0x82000000 #elif defined(CONFIG_QSPI_BOOT) -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 00/21] STiH410-B2260: add reset, usb and fastboot support
by patrice.chotard＠st.com 19 Apr '17

19 Apr '17

From: Patrice Chotard <patrice.chotard(a)st.com> This series adds : _ add reset driver _ update existing sdhci driver to use reset framework _ add usb phy driver _ add ehci support _ add ohci support _ add xhci support _ add fastboot support With all this feature enable, it's now possible to _ boot on usb mass storage device _ boot from kernel image and dtb previously loaded using tftp _ update mmc partiton using fastboot Patrice Chotard (21): reset: Add STi reset support mmc: sti_sdhci: Rework sti_mmc_core_config() ARM: dts: stih410-family: Add missing reset_names for mmc1 node mmc: sti_sdhci: Use reset framework phy: Add STi phy usb support usb: ehci: Add STi ehci support STiH410-B2260: enable USB related flags usb: ohci: Add STi ohci support STiH410-B2260: enable OHCI related flags usb: xhci: Add STi xhci support STiH410-B2260: enable XHCI related flags STiH410-B2260: Enabling USB Host Networking usb: dwc3: Add dwc3 support for STi STiH410-B2260: enable DWC3 support board: STiH410-B2260: add fastboot support STiH410-B2260: enable USB download gadget related flags STiH410-B2260: enable FASTBOOT related flags STiH410-B2260: enable OF_LIBFDT_OVERLAY STiH410-B2260: enable CMD_EXT4_WRITE STiH410-B2260: enable CMD_GPT STiH410-B2260: enable CMD_PART arch/arm/Kconfig | 1 + arch/arm/dts/stih407-family.dtsi | 1 + arch/arm/include/asm/arch-stih410/sys_proto.h | 11 + board/st/stih410-b2260/board.c | 44 ++++ configs/stih410-b2260_defconfig | 33 +++ drivers/mmc/sti_sdhci.c | 60 +++-- drivers/reset/Kconfig | 8 + drivers/reset/Makefile | 1 + drivers/reset/sti-reset.c | 321 ++++++++++++++++++++++++++ drivers/usb/Kconfig | 4 + drivers/usb/dwc3/Kconfig | 8 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-sti.c | 137 +++++++++++ drivers/usb/host/Kconfig | 26 +++ drivers/usb/host/Makefile | 3 + drivers/usb/host/ehci-sti.c | 91 ++++++++ drivers/usb/host/ohci-sti.c | 90 ++++++++ drivers/usb/host/xhci-sti.c | 156 +++++++++++++ drivers/usb/phy/Kconfig | 11 + drivers/usb/phy/Makefile | 1 + drivers/usb/phy/sti_phy_usb.c | 158 +++++++++++++ include/configs/stih410-b2260.h | 16 ++ include/dwc3-sti-uboot.h | 50 ++++ 23 files changed, 1210 insertions(+), 22 deletions(-) create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h create mode 100644 drivers/reset/sti-reset.c create mode 100644 drivers/usb/dwc3/dwc3-sti.c create mode 100644 drivers/usb/host/ehci-sti.c create mode 100644 drivers/usb/host/ohci-sti.c create mode 100644 drivers/usb/host/xhci-sti.c create mode 100644 drivers/usb/phy/Kconfig create mode 100644 drivers/usb/phy/sti_phy_usb.c create mode 100644 include/dwc3-sti-uboot.h -- 1.9.1

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Re: [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
by york sun 18 Apr '17

18 Apr '17

On 02/16/2017 01:12 PM, york.sun(a)nxp.com wrote: > On 02/03/2017 06:08 AM, Suresh Gupta wrote: <snip> >> +static void erratum_a009007(void) >> +{ >> +/* TODO:implement the out_be16 instead of writew which is taking >> +little endian style */ > > Did you mean to remind yourself to finish this before sending this > patch? You know we already have out_be16(), don't you? > Suresh, Are you going to send an update? York

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[U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram
by Ruchika Gupta 18 Apr '17

18 Apr '17

Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/unlocks both L1 as well as L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)nxp.com> --- arch/powerpc/cpu/mpc85xx/start.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index c3e1234..b9a4cb5 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1145,8 +1145,9 @@ switch_as: li r0,0 1: dcbz r0,r3 -#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */ dcbtls 2, r0, r3 + dcbtls 0, r0, r3 #else dcbtls 0, r0, r3 #endif @@ -1790,8 +1791,9 @@ unlock_ram_in_cache: slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 -#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */ dcblc 2, r0, r3 + dcblc 0, r0, r3 #else dcblc r0,r3 #endif -- 1.9.1

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