March 2017 - U-Boot

[U-Boot] Fwd: u-boot.img size limit for spl fat load ?
by Ayoub Zaki 18 Oct '17

18 Oct '17

Hello Albert, First tank you so much for inversting your time for replying. I put some printf in the code and SPL is hanging in spl_load_image_fat function. I also enable the DEBUG messages here the complete log file : http://pastebin.com/raw.php?i=BwUJXDDb So I suspect that SPL is not allocating enough memory to load u-boot.img but I can't find where this size limit is set and where I can change it. Cheers, Ayoub > 2015-01-19 8:08 GMT+01:00 Albert ARIBAUD <albert.u.boot(a)aribaud.net>: > > > Hello Ayoub, > > > > On Fri, 16 Jan 2015 15:42:37 +0100, Ayoub Zaki > > <ayoub.zaki(a)googlemail.com> wrote: > > > Hello list, > > > > > > I'm using u-boot-2014.10 and trying to build it with LCD support for the > > > Beaglebone black to include a Boot logo image. > > > It seems that spl hangs while fat loading a 2.8MB sized u-boot.img ! > > > I reduced the the logo header file and rebuild u-boot, that worked for a > > > 1.6MB sized u-boot.img. > > > Is there any size limit for u-boot ? how to increase the memory allocated > > > by spl ? > > > > There should not be a size limit for SPL fat load. > > > > What may happen is that SPL code is overwritten before it exits, or > > U-Boot itself is corrupted after being loaded. > > > > I assume you've seen the SPL banner and not the U-Boot one; that alone > > does not tell us whether SPL or U-Boot did hang. Can you build U-boot > > with debug enabled? If this results in too big an SPL image, then try > > and at least enable debug for the image chainloading parts, so that you > > can see how far SPL code gets run. > > > > > Thanks you. > > > > No problem. > > > > Amicalement, > > -- > > Albert.

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[U-Boot] [PATCH v4 0/4] rk3399: enable dwc3 gadget and fastboot
by Kever Yang 12 Sep '17

12 Sep '17

This patch set enable rk3399 dwc3 controller and gadget driver for fastboot. Changes in v4: - parse DT for quirk, base address and maximum speed - use 1 bit for usb2_phyif_utmi_width instead of 5bit Changes in v3: - remove utmi width DT parse from borad init - Parse the DT for utmi+ interface width in dwc3 driver - move the config into Kconfig file. Changes in v2: - parse dt for utmi width - use a variable to identify utmi+ bus width instead of CONFIG MACRO - remove config for USB2PHY UTMI BITS Kever Yang (4): rk3399: add a empty "sys_proto.h" header file board: evb-rk3399: add api to support dwc3 gadget usb: dwc3: add support for 16 bit UTMI+ interface config: rk3399: add support for dwc3 gadget arch/arm/include/asm/arch-rockchip/sys_proto.h | 10 +++++ board/rockchip/evb_rk3399/evb-rk3399.c | 51 ++++++++++++++++++++++++++ configs/evb-rk3399_defconfig | 17 +++++++++ drivers/usb/dwc3/core.c | 19 ++++++++++ drivers/usb/dwc3/core.h | 12 ++++++ 5 files changed, 109 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/sys_proto.h -- 1.9.1

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[U-Boot] [PATCH] video: ipu_common: fix build error
by Peng Fan 07 Sep '17

07 Sep '17

Some toolchains fail to build "clk->rate = (u64)(clk->parent->rate * 16) / div;" And the cast usage is wrong. Use the following code to fix the issue, " do_div(parent_rate, div); clk->rate = parent_rate; " Reported-by: Peter Robinson <pbrobinson(a)gmail.com> Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Anatolij Gustschin <agust(a)denx.de> Cc: Peter Robinson <pbrobinson(a)gmail.com> --- Hi Peter, Please help test this patch to see whether this fix your issue or not. Thanks for pointing out this issue. Thanks, Peng. drivers/video/ipu_common.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 36d4b23..5676a0f 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -352,7 +352,9 @@ static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) */ __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); - clk->rate = (u64)(clk->parent->rate * 16) / div; + do_div(parent_rate, div); + + clk->rate = parent_rate; return 0; } -- 2.6.2

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[U-Boot] [PATCH 1/3] video: ipu: avoid overflow issue
by Peng Fan 06 Sep '17

06 Sep '17

Multiplication, as "clk->parent->rate * 16" may overflow. So use do_div to avoid such issue. Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Signed-off-by: Sandor Yu <sandor.yu(a)nxp.com> Cc: Anatolij Gustschin <agust(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> --- drivers/video/ipu_common.c | 73 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 54 insertions(+), 19 deletions(-) diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 9f85102..36d4b23 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -19,6 +19,7 @@ #include <asm/errno.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> +#include <div64.h> #include "ipu.h" #include "ipu_regs.h" @@ -275,50 +276,84 @@ static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum, static void ipu_pixel_clk_recalc(struct clk *clk) { - u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); - if (div == 0) - clk->rate = 0; - else - clk->rate = (clk->parent->rate * 16) / div; + u32 div; + u64 final_rate = (unsigned long long)clk->parent->rate * 16; + + div = __raw_readl(DI_BS_CLKGEN0(clk->id)); + debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n", + div, final_rate, clk->parent->rate); + + clk->rate = 0; + if (div != 0) { + do_div(final_rate, div); + clk->rate = final_rate; + } } static unsigned long ipu_pixel_clk_round_rate(struct clk *clk, unsigned long rate) { - u32 div, div1; - u32 tmp; + u64 div, final_rate; + u32 remainder; + u64 parent_rate = (unsigned long long)clk->parent->rate * 16; + /* * Calculate divider * Fractional part is 4 bits, * so simply multiply by 2^4 to get fractional part. */ - tmp = (clk->parent->rate * 16); - div = tmp / rate; - + div = parent_rate; + remainder = do_div(div, rate); + /* Round the divider value */ + if (remainder > (rate / 2)) + div++; if (div < 0x10) /* Min DI disp clock divider is 1 */ div = 0x10; if (div & ~0xFEF) div &= 0xFF8; else { - div1 = div & 0xFE0; - if ((tmp/div1 - tmp/div) < rate / 4) - div = div1; - else - div &= 0xFF8; + /* Round up divider if it gets us closer to desired pix clk */ + if ((div & 0xC) == 0xC) { + div += 0x10; + div &= ~0xF; + } } - return (clk->parent->rate * 16) / div; + final_rate = parent_rate; + do_div(final_rate, div); + + return final_rate; } static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) { - u32 div = (clk->parent->rate * 16) / rate; + u64 div, parent_rate; + u32 remainder; + + parent_rate = (unsigned long long)clk->parent->rate * 16; + div = parent_rate; + remainder = do_div(div, rate); + /* Round the divider value */ + if (remainder > (rate / 2)) + div++; + + /* Round up divider if it gets us closer to desired pix clk */ + if ((div & 0xC) == 0xC) { + div += 0x10; + div &= ~0xF; + } + if (div > 0x1000) + debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div); __raw_writel(div, DI_BS_CLKGEN0(clk->id)); - /* Setup pixel clock timing */ + /* + * Setup pixel clock timing + * Down time is half of period + */ __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); - clk->rate = (clk->parent->rate * 16) / div; + clk->rate = (u64)(clk->parent->rate * 16) / div; + return 0; } -- 2.6.2

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[U-Boot] [PATCH v2] driver: net: ldpaa: Update priv->phydev after free()
by Ashish Kumar 14 Aug '17

14 Aug '17

From: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Even after memory free of phydev, priv is still pointing to the obsolete address. So update priv->phydev as NULL after memory free. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- v2: Add signoff drivers/net/ldpaa_eth/ldpaa_eth.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 4e61700..f235b62 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -587,8 +587,10 @@ static void ldpaa_eth_stop(struct eth_device *net_dev) #ifdef CONFIG_PHYLIB if (priv->phydev && bus != NULL) phy_shutdown(priv->phydev); - else + else { free(priv->phydev); + priv->phydev = NULL; + } #endif ldpaa_dpbp_free(); -- 1.9.1

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[U-Boot] [PATCH] driver: net: ldpaa: Update priv->phydev after free()
by Ashish Kumar 11 Aug '17

11 Aug '17

From: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Even after memory free of phydev, priv is still pointing to the obsolete address. So update priv->phydev as NULL after memory free. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- drivers/net/ldpaa_eth/ldpaa_eth.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 4e61700..f235b62 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -587,8 +587,10 @@ static void ldpaa_eth_stop(struct eth_device *net_dev) #ifdef CONFIG_PHYLIB if (priv->phydev && bus != NULL) phy_shutdown(priv->phydev); - else + else { free(priv->phydev); + priv->phydev = NULL; + } #endif ldpaa_dpbp_free(); -- 1.9.1

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[U-Boot] [PATCH v1 0/2] Add support for the A64-uQ7 modules
by Philipp Tomsich 11 Aug '17

11 Aug '17

This changeset adds support for the A64-uQ7 modules from Theobroma Systems, which is based on Allwinner's A64 (sun50iw1p1). It depends on the device-model support for the sunxi subarchitecture and the DM-based, dual-IO capable SPI driver which we submitted over the last couple of days. Given that these other patches are unmerged, this will (at this stage) mainly serve as a reference point to better point these other patchsets into perspective. Philipp Tomsich (2): dts: lynx: add sun50i-a64-lynx.dts for the A64-uQ7 lynx_defconfig: add defconfig for A64-uQ7 module arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-a64-lynx.dts | 247 +++++++++++++++++++++++++++++++++++++++ configs/lynx_defconfig | 84 +++++++++++++ 3 files changed, 332 insertions(+) create mode 100644 arch/arm/dts/sun50i-a64-lynx.dts create mode 100644 configs/lynx_defconfig -- 1.9.1

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[U-Boot] [PATCH v4 00/26] sunxi: Allwinner A64: SPL support
by Andre Przywara 11 Aug '17

11 Aug '17

Hi, hopefully the final version of the SPL support series for the Allwinner A64 SoC. Actually no real code changes this time, just rebased on top of recent master, adding some comments in patches 16/26 and 19/26 following Maxime's suggestions and adding Acked-by:s and Reviewed-by:s. I left the final patch 26/26 in for the sake of completeness, but don't expect it to be merged. We need a clever solution to unify 32-bit and 64-bit board configurations, but that shouldn't hold back this series for now. Merging everything until and including patch 21/26 (sunxi: A64: enable SPL) would be great, the other patches until 25/26 can go in as well, I think. ------------- As the previous versions this one includes support for both AArch64 and AArch32 SPL builds. The FIT support is still missing, which means the functionality is limited. Due to the missing ARM Trusted Firmware (ATF) in this firmware chain we lose Ethernet and SMP, among other minor things. A full 64-bit build can be written to an SD card as expected and will boot the U-Boot proper prompt. However Linux will crash on boot, as PSCI is missing. Building the 32-bit version of the SPL and combining this with an ATF build and the 64-bit U-Boot proper allows to use FEL booting now: # sunxi-fel spl sunxi-spl.bin write 0x4a000000 u-boot-dtb.bin \ write 0x44000 bl31.bin reset64 0x44000 This way of booting the board gives full functionality. The first patch is a rather simple fix (with no changes to v2). Patches 2-8 prepare the SPL code to be compiled for 64-bit in general and AArch64 in particular. Patches 9-11 refactor the existing boot0 header functionality to be used by patch 12, which introduces the 64-bit switch in the first SPL instructions. Patches 13-20 then introduce the actual core of the SPL support: the DRAM initialization, courtesy of Jens. This piggy backs on the existing H3 DRAM code, deviating where needed. This has been reworked compared to v2: I added a patch from Philipp to replace the rather uninspired register writes in the MBUS priority setup function with some meaningful code, explaining the various bits. Also the actual A64 DRAM code is no longer #ifdef'ed into the H3 driver, but uses parameters to (static) functions. The compiler detects this and removes the dead code from the other variant, resulting in the same binary size for the H3. Patch 21 finally enables the 64-bit SPL support. So now building the existing pine64_plus_defconfig will generate a sunxi-spl.bin, which can be prepended to the U-Boot proper image (not .bin) to boot from an SD card. Due to the missing ATF support this is of limited usability at the moment, though. Also FEL support requires more love - to switch back to AArch32 before returning to FEL (without crashing, that is ;-), so this is disabled. On my setup this results in a 26KB SPL binary, which is close to the 28K limit mksunxiboot imposes at the moment. Adding anything (like FIT support or DEBUG) will exceed this, and although I have patches to let mksunxiboot get close to 32KB, this is the ulimate frontier. So patches 22-25 then teach the SPL how to detect an U-Boot image file of a different bitness and do the RMR switch from AArch32 to AArch64, if needed. This is used by the final patch 26, which creates another _defconfig to let the SPL compile for AArch32 using the Thumb2 encoding. This results in a binary of less than 17KB in my case, so has plenty of room for extensions. Cheers, Andre. Changelog v3 .. v4: - rebased on top of latest HEAD - add various Reviewed-by: and Acked-by: tags - add comments about register bit meanings in non-ODT-setting fix - clarify meaning of delay values in single bit delay support patch - removing stray semicolons from boot0.h header Changelog v2 .. v3: - add various Reviewed-by: and Acked-by: tags - split tiny-printf fix to handle "-" separately - add various comments and extend commit messages - add assembly file to re-create the embedded RMR switch code - add patch 14/26 to explain the MBUS priority setup - move DRAM r/w delay values into #defines to simplify re-usablity - replace #ifdef'ed addition of A64 support to the H3 DRAM driver with an approach using static parameters Changelog v1 .. v2: - drop SPI build fix (already merged) - confine A31 register init change to H3 and A64 - use IS_ENABLED() instead of #idef to guard MBUS2 clock init - fix tiny-printf (proper sign extension for 32-bit integers) - add "size" output in commit msg to document tiny-printf size impact - fix sdelay(): use only one register, add "cc" clobber - update RMR switch code to provide easy access to RVBAR register address - drop redundant DRAM frequency setting from Pine64 defconfig - minor changes as requested by reviewers Andre Przywara (21): sun6i: Restrict some register initialization to Allwinner A31 SoC armv8: prevent using THUMB armv8: add lowlevel_init.S SPL: tiny-printf: add "l" modifier SPL: tiny-printf: ignore "-" modifier move UL() macro from armv8/mmu.h into common.h SPL: make struct spl_image 64-bit safe armv8: add simple sdelay implementation armv8: move reset branch into boot hook ARM: boot0 hook: remove macro, include whole header file sunxi: introduce extra config option for boot0 header sunxi: A64: do an RMR switch if started in AArch32 mode sunxi: provide default DRAM config for sun50i in Kconfig sunxi: H3/A64: fix non-ODT setting sunxi: DRAM: fix H3 DRAM size display on aarch64 sunxi: A64: enable SPL SPL: read and store arch property from U-Boot image Makefile: use "arm64" architecture for U-Boot image files ARM: SPL/FIT: differentiate between arm and arm64 arch properties sunxi: introduce RMR switch to enter payloads in 64-bit mode sunxi: A64: add 32-bit SPL support Jens Kuske (3): sunxi: H3: add and rename some DRAM contoller registers sunxi: H3: add DRAM controller single bit delay support sunxi: A64: use H3 DRAM initialization code for A64 as well Philipp Tomsich (2): sunxi: H3: Rework MBUS priority setup sunxi: clocks: Use the correct pattern register for PLL11 Makefile | 9 +- arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cpu.c | 14 + arch/arm/cpu/armv8/lowlevel_init.S | 44 +++ arch/arm/cpu/armv8/start.S | 5 +- arch/arm/include/asm/arch-bcm235xx/boot0.h | 8 +- arch/arm/include/asm/arch-bcm281xx/boot0.h | 8 +- arch/arm/include/asm/arch-sunxi/boot0.h | 37 ++- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + arch/arm/include/asm/arch-sunxi/cpu.h | 3 + arch/arm/include/asm/arch-sunxi/dram.h | 2 +- arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 53 ++-- arch/arm/include/asm/armv8/mmu.h | 8 - arch/arm/lib/Makefile | 2 + arch/arm/lib/spl.c | 15 + arch/arm/lib/vectors.S | 1 - arch/arm/mach-omap2/boot-common.c | 2 +- arch/arm/mach-sunxi/Makefile | 2 + arch/arm/mach-sunxi/board.c | 2 +- arch/arm/mach-sunxi/clock_sun6i.c | 10 +- arch/arm/mach-sunxi/dram_sun8i_h3.c | 400 +++++++++++++++++------- arch/arm/mach-sunxi/rmr_switch.S | 41 +++ arch/arm/mach-sunxi/spl_switch.c | 81 +++++ arch/arm/mach-tegra/spl.c | 2 +- board/sunxi/Kconfig | 41 ++- common/spl/spl.c | 9 +- common/spl/spl_fit.c | 8 + common/spl/spl_mmc.c | 2 +- configs/pine64_plus_defconfig | 7 +- configs/sun50i_spl32_defconfig | 10 + include/common.h | 13 +- include/configs/sunxi-common.h | 4 +- include/spl.h | 19 +- lib/tiny-printf.c | 50 ++- 34 files changed, 713 insertions(+), 201 deletions(-) create mode 100644 arch/arm/cpu/armv8/lowlevel_init.S create mode 100644 arch/arm/mach-sunxi/rmr_switch.S create mode 100644 arch/arm/mach-sunxi/spl_switch.c create mode 100644 configs/sun50i_spl32_defconfig -- 2.8.2

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[U-Boot] [PATCH 0/3] mx6: ddr: updates for dynamic DDR calibration
by Eric Nelson 28 Jul '17

28 Jul '17

This set of patches updates the interface to the DDR calibration in preparation for the addition of a pseudo-board for calibration on i.MX6. The first patch fixes an ommission in the use of the DG_CMP_CYC flag in register MPDGCTRL0. The second patch cleans up the handling of bus widths by passing the system configuration information to the calibration routines. The third routine adds support for returning the calibration data written to the MMDC registers. Eric Nelson (3): mx6: ddr: allow 32 cycles for DQS gating calibration mx6: ddr: pass mx6_ddr_sysinfo to calibration routines mx6: ddr: add mmdc_read_calibration routine to return dynamic data arch/arm/cpu/armv7/mx6/ddr.c | 128 +++++++++++++++++++++----------- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 6 +- board/kosagi/novena/novena_spl.c | 4 +- 3 files changed, 92 insertions(+), 46 deletions(-) -- 2.7.4

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[U-Boot] [PATCH] armv8: ls2080aqds: enable PPA support for SD boot
by Santan Kumar 26 Jul '17

26 Jul '17

Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> --- Depends on Add support for SD boot https://patchwork.ozlabs.org/patch/734572/ Zhiqiang Hou's patch https://patchwork.ozlabs.org/patch/740194/ configs/ls2080aqds_sdcard_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 874d49e..5667072 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_FSL_LS_PPA=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -- 1.9.1

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