February 2017 - U-Boot

[U-Boot] [PATCH v3] arm: use common instructions applicable to armv7m & other arm archs
by Vikas Manocha 18 Mar '17

18 Mar '17

This patch cleans the code by using instructions allowed for armv7m as well as other Arm archs. Signed-off-by: Vikas Manocha <vikas.manocha(a)st.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Heiko Schocher <hs(a)denx.de> --- Changes in v3: moved the comment to right location. Changes in v2: reword message commit. Removed info regarding BIC instruction on SP, was creating confusion. arch/arm/lib/crt0.S | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 2f4c14e..d9078aa 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -71,18 +71,12 @@ ENTRY(_main) */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) - ldr sp, =(CONFIG_SPL_STACK) + ldr r0, =(CONFIG_SPL_STACK) #else - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) #endif -#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ - mov r3, sp - bic r3, r3, #7 - mov sp, r3 -#else - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ -#endif - mov r0, sp + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 bl board_init_f_alloc_reserve mov sp, r0 /* set up gd here, outside any C code */ @@ -100,14 +94,9 @@ ENTRY(_main) * 'here' but relocated. */ - ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ -#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ - mov r3, sp - bic r3, r3, #7 - mov sp, r3 -#else - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ -#endif + ldr r0, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ sub r9, r9, #GD_SIZE /* new GD is below bd */ -- 1.9.1

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[U-Boot] [PATCH v2] dtoc: make ScanTree recurse into subnodes
by Philipp Tomsich 17 Mar '17

17 Mar '17

Previously, dtoc could only process the top-level nodes which led to device nodes in hierarchical trees to be ignored. E.g. the mmc0 node in the following example would be ignored, as only the soc node was processed: / { soc { mmc0 { /* ... */ }; }; }; This introduces a recursive helper method ScanNode, which is used by ScanTree to recursively parse the entire tree hierarchy. Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- tools/dtoc/dtoc.py | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index 6df7b0d..fe8b0c2 100755 --- a/tools/dtoc/dtoc.py +++ b/tools/dtoc/dtoc.py @@ -170,6 +170,21 @@ class DtbPlatdata: """ self.fdt = fdt_select.FdtScan(self._dtb_fname) + def ScanNode(self, root): + for node in root.subnodes: + if 'compatible' in node.props: + status = node.props.get('status') + if (not options.include_disabled and not status or + status.value != 'disabled'): + self._valid_nodes.append(node) + phandle_prop = node.props.get('phandle') + if phandle_prop: + phandle = phandle_prop.GetPhandle() + self._phandle_node[phandle] = node + + # recurse to handle any subnodes + self.ScanNode(node); + def ScanTree(self): """Scan the device tree for useful information @@ -178,8 +193,10 @@ class DtbPlatdata: _valid_nodes: A list of nodes we wish to consider include in the platform data """ - node_list = [] self._phandle_node = {} + self._valid_nodes = [] + return self.ScanNode(self.fdt.GetRoot()); + for node in self.fdt.GetRoot().subnodes: if 'compatible' in node.props: status = node.props.get('status') -- 1.9.1

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[U-Boot] [PATCH 0/3] driver: ti_qspi: Use a SYSCON device to map the ctrl_mod_mmap register
by Jean-Jacques Hiblot 17 Mar '17

17 Mar '17

This series allows the ti_qspi driver to use the same dts description as the linux kernel. In Linux since 4.6 the ctrl_mod_mmap is described in the DTS as a syscon. It used to be the 3rd memory range in "reg". The first patch of this series is a generic one. It changes the regmap initialization to take in account the required address translation. The second patch adds the mechanism in the ti_qspi driver to get the address of ctrl_mod_mmap from the syscon The last patch simply enable the SYSCON feature in the default config for the dra7xx and am57xx evms. Jean-Jacques Hiblot (3): regmap: use fdt address translation drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register configs: dra7x/am57x: Enable the SYSCON and REGMAP features configs/am57xx_evm_defconfig | 2 ++ configs/am57xx_hs_evm_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ drivers/core/regmap.c | 14 ++++++------ drivers/spi/ti_qspi.c | 47 ++++++++++++++++++++++++++++++++++++----- 6 files changed, 58 insertions(+), 11 deletions(-) -- 1.9.1

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[U-Boot] [PATCH v2] dm: core: Fix Handling of global_data moving in SPL
by Lokesh Vutla 17 Mar '17

17 Mar '17

commit 2f11cd9121658 ("dm: core: Handle global_data moving in SPL") handles relocation of GD in SPL if spl_init() is called before board_init_r(). So, uclass_root.next need not be initialized always and accessing uclass_root.next->prev gives an abort. Update the uclass_root only if it is available. Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- drivers/core/root.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/core/root.c b/drivers/core/root.c index 9edfc1efb6..4c935f40b6 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -44,8 +44,10 @@ struct udevice *dm_root(void) void dm_fixup_for_gd_move(struct global_data *new_gd) { /* The sentinel node has moved, so update things that point to it */ - new_gd->uclass_root.next->prev = &new_gd->uclass_root; - new_gd->uclass_root.prev->next = &new_gd->uclass_root; + if (gd->dm_root) { + new_gd->uclass_root.next->prev = &new_gd->uclass_root; + new_gd->uclass_root.prev->next = &new_gd->uclass_root; + } } fdt_addr_t dm_get_translation_offset(void) -- 2.11.0

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[U-Boot] [RFC PATCH] driver: pci: Fix regions for local memory
by York Sun 17 Mar '17

17 Mar '17

When adding local memory to PCI region, gd->ram_size is correct only if the memory is in one continuous block. In case memory is split into several banks, each bank should be added separately. Signed-off-by: York Sun <york.sun(a)nxp.com> CC: Simon Glass <sjg(a)chromium.org> --- It was spotted when I was rewriting the code to reserve secure memory and forgot to reduce gd->ram_size. PCIe resumes working after fixing gd->ram_size. For my case, the memory is split into two banks. So base + gd->ram_size is not in memory. I don't know how it worked before. This change seems reasonable without digging into PCI code. drivers/pci/pci-uclass.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 3b00e6a..eb80198 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -814,7 +814,22 @@ static int decode_regions(struct pci_controller *hose, const void *blob, pci_set_region(hose->regions + pos, pci_addr, addr, size, type); } - /* Add a region for our local memory */ + /* Add region(s) for our local memory */ +#ifdef CONFIG_NR_DRAM_BANKS + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + base = gd->bd->bi_dram[i].start; + size = gd->bd->bi_dram[i].size; + if (gd->pci_ram_top && + gd->pci_ram_top >= base && + gd->pci_ram_top < base + size) + size = gd->pci_ram_top - base; + if (size) { + pci_set_region(hose->regions + hose->region_count++, + base, base, size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + } + } +#else size = gd->ram_size; #ifdef CONFIG_SYS_SDRAM_BASE base = CONFIG_SYS_SDRAM_BASE; @@ -823,6 +838,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob, size = gd->pci_ram_top - base; pci_set_region(hose->regions + hose->region_count++, base, base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); +#endif return 0; } -- 2.7.4

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[U-Boot] [PATCH v7 0/9] Add STMicroelectronics STiH410-B2260 board
by patrice.chotard＠st.com 16 Mar '17

16 Mar '17

From: Patrice Chotard <patrice.chotard(a)st.com> v7: _ typo: replace "Slow" by "Low" in patch 9 Kconfig's help v6: _ fix last minute bug in pinctrl driver v5: _ Add Simon Glass's reviewed-by _ move board Kconfig description from patch 1 to 9 v4: _ fix STi serial driver to be fully DT compliant _ remove arch/arm/include/asm/arch-stih410/sti.h and include/dm/platform_data/serial_sti_asc.h which became useless _ board file cleanup _ fix some nits in sti_sdhci.c _ rebased on top of v2017.03-rc2 v3: _ add reviewed-by _ add top level MAINTAINERS entry and in the board MAINTAINERS _ use the fallback table from include/config_fallbacks.h _ minor update in sti_sdhci.c _ reorder patches with functionnal board and defconfig in last _ remove arch/arm/mach-sti/cpu.c and replace it by a sysreset DM driver _ remove arch/arm/mach-sti/timer.c by a timer DM driver _ remove useless arch/arm/include/asm/arch-stih410/syscfg.h _ remove useless arch/arm/include/asm/arch-stih410/gpio.h and update arch/arm/include/asm/gpio.h for ARCH_STI in patch 5 v2: _ fix remarks from Jaechon Chung on SDHCI patch _ fix remarks from Antonio Borneo on board patch _ replace some macro by U-boot generic's one _ add missing maintainers in recipients Patrice Chotard (9): arm: Add support for STMicroelectronics STiH410 soc STiH410: Add STi timer driver STiH410: Add STi sysreset driver STiH410: Add STi serial driver gpio: do not include <asm/arch/gpio.h> for ARCH_STI STiH410: Add STi SDHCI driver STiH410: Add STi pinctrl driver STiH410-B2260: Add device tree board: Add STMicroelectronics STiH410-B2260 support MAINTAINERS | 6 + arch/arm/Kconfig | 13 + arch/arm/dts/Makefile | 2 + arch/arm/dts/st-pincfg.h | 71 ++ arch/arm/dts/stih407-clock.dtsi | 326 ++++++ arch/arm/dts/stih407-family.dtsi | 977 +++++++++++++++ arch/arm/dts/stih407-pinctrl.dtsi | 1303 +++++++++++++++++++++ arch/arm/dts/stih410-b2260.dts | 226 ++++ arch/arm/dts/stih410-clock.dtsi | 347 ++++++ arch/arm/dts/stih410-pinctrl.dtsi | 34 + arch/arm/dts/stih410.dtsi | 454 +++++++ arch/arm/include/asm/arch-stih410/sdhci.h | 68 ++ arch/arm/include/asm/gpio.h | 2 +- arch/arm/mach-sti/Kconfig | 31 + board/st/stih410-b2260/Kconfig | 19 + board/st/stih410-b2260/MAINTAINERS | 7 + board/st/stih410-b2260/Makefile | 8 + board/st/stih410-b2260/board.c | 28 + configs/stih410-b2260_defconfig | 26 + drivers/mmc/Kconfig | 7 + drivers/mmc/Makefile | 1 + drivers/mmc/sti_sdhci.c | 141 +++ drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-sti.c | 320 +++++ drivers/serial/Kconfig | 8 + drivers/serial/Makefile | 1 + drivers/serial/serial_sti_asc.c | 211 ++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_sti.c | 82 ++ drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 1 + drivers/timer/sti-timer.c | 78 ++ include/configs/stih410-b2260.h | 60 + include/dt-bindings/clock/stih407-clks.h | 90 ++ include/dt-bindings/clock/stih410-clks.h | 25 + include/dt-bindings/interrupt-controller/irq-st.h | 30 + include/dt-bindings/mfd/st-lpc.h | 16 + include/dt-bindings/reset/stih407-resets.h | 65 + 39 files changed, 5102 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/st-pincfg.h create mode 100644 arch/arm/dts/stih407-clock.dtsi create mode 100644 arch/arm/dts/stih407-family.dtsi create mode 100644 arch/arm/dts/stih407-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410-b2260.dts create mode 100644 arch/arm/dts/stih410-clock.dtsi create mode 100644 arch/arm/dts/stih410-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410.dtsi create mode 100644 arch/arm/include/asm/arch-stih410/sdhci.h create mode 100644 arch/arm/mach-sti/Kconfig create mode 100644 board/st/stih410-b2260/Kconfig create mode 100644 board/st/stih410-b2260/MAINTAINERS create mode 100644 board/st/stih410-b2260/Makefile create mode 100644 board/st/stih410-b2260/board.c create mode 100644 configs/stih410-b2260_defconfig create mode 100644 drivers/mmc/sti_sdhci.c create mode 100644 drivers/pinctrl/pinctrl-sti.c create mode 100644 drivers/serial/serial_sti_asc.c create mode 100644 drivers/sysreset/sysreset_sti.c create mode 100644 drivers/timer/sti-timer.c create mode 100644 include/configs/stih410-b2260.h create mode 100644 include/dt-bindings/clock/stih407-clks.h create mode 100644 include/dt-bindings/clock/stih410-clks.h create mode 100644 include/dt-bindings/interrupt-controller/irq-st.h create mode 100644 include/dt-bindings/mfd/st-lpc.h create mode 100644 include/dt-bindings/reset/stih407-resets.h -- 1.9.1

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[U-Boot] [PATCH 1/2] igep00x0: disable environment
by Ladislav Michl 16 Mar '17

16 Mar '17

ISEE's U-Boot and Linux are using 1bit ECC scheme, while we switched to 8bit ECC to fullfill flash specification requirements. However when trying to run U-Boot on board with 1bit ECC'd data on flash, UBI code takes several minutes to pass scan as reading of every block ends with ecc error (which is also printed on console). So, until proper solution is developed, disable environment alltogether. Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- include/configs/omap3_igep00x0.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index ac0df3e08b..70d337e6f1 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -140,7 +140,7 @@ #define CONFIG_SPL_UBI_INFO_ADDR 0x88080000 /* environment organization */ -#define CONFIG_ENV_IS_IN_UBI 1 +#define CONFIG_ENV_IS_NOWHERE 1 #define CONFIG_ENV_UBI_PART "UBI" #define CONFIG_ENV_UBI_VOLUME "config" #define CONFIG_ENV_UBI_VOLUME_REDUND "config_r" -- 2.11.0

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[U-Boot] [PATCH v3] armv7m: Add SysTick timer driver
by Phil Edworthy 16 Mar '17

16 Mar '17

The SysTick is a 24-bit down counter that is found on all ARM Cortex M3, M4, M7 devices and is always located at a fixed address. The number of reference clock ticks that correspond to 10ms is normally defined in the SysTick Calibration register's TENMS field. However, on some devices this is wrong, so this driver allows the clock rate to be defined using CONFIG_SYS_HZ_CLOCK. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- v3: - Add comments about where we get the ref clock rate from. v2: - Variables & constant renamed. - Use the calibration reg to determine if we use the cpu or ref clk - Use the calibration reg to get the clk rate, unless specified --- arch/arm/cpu/armv7m/Makefile | 2 + arch/arm/cpu/armv7m/systick-timer.c | 116 ++++++++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+) create mode 100644 arch/arm/cpu/armv7m/systick-timer.c diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index aff60e8..e1a6c40 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -7,3 +7,5 @@ extra-y := start.o obj-y += cpu.o + +obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c new file mode 100644 index 0000000..23244c3 --- /dev/null +++ b/arch/arm/cpu/armv7m/systick-timer.c @@ -0,0 +1,116 @@ +/* + * ARM Cortex M3/M4/M7 SysTick timer driver + * (C) Copyright 2017 Renesas Electronics Europe Ltd + * + * Based on arch/arm/mach-stm32/stm32f1/timer.c + * (C) Copyright 2015 + * Kamil Lulko, <kamil.lulko(a)gmail.com> + * + * Copyright 2015 ATS Advanced Telematics Systems GmbH + * Copyright 2015 Konsulko Group, Matt Porter <mporter(a)konsulko.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * The SysTick timer is a 24-bit count down timer. The clock can be either the + * CPU clock or a reference clock. Since the timer will wrap around very quickly + * when using the CPU clock, and we do not handle the timer interrupts, it is + * expected that this driver is only ever used with a slow reference clock. + * + * The number of reference clock ticks that correspond to 10ms is normally + * defined in the SysTick Calibration register's TENMS field. However, on some + * devices this is wrong, so this driver allows the clock rate to be defined + * using CONFIG_SYS_HZ_CLOCK. + */ + +#include <common.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */ +#define SYSTICK_BASE 0xE000E010 + +struct cm3_systick { + uint32_t ctrl; + uint32_t reload_val; + uint32_t current_val; + uint32_t calibration; +}; + +#define TIMER_MAX_VAL 0x00FFFFFF +#define SYSTICK_CTRL_EN BIT(0) +/* Clock source: 0 = Ref clock, 1 = CPU clock */ +#define SYSTICK_CTRL_CPU_CLK BIT(2) +#define SYSTICK_CAL_NOREF BIT(31) +#define SYSTICK_CAL_SKEW BIT(30) +#define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF + +/* read the 24-bit timer */ +static ulong read_timer(void) +{ + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE; + + /* The timer counts down, therefore convert to an incrementing timer */ + return TIMER_MAX_VAL - readl(&systick->current_val); +} + +int timer_init(void) +{ + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE; + u32 cal; + + writel(TIMER_MAX_VAL, &systick->reload_val); + /* Any write to current_val reg clears it to 0 */ + writel(0, &systick->current_val); + + cal = readl(&systick->calibration); + if (cal & SYSTICK_CAL_NOREF) + /* Use CPU clock, no interrupts */ + writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, &systick->ctrl); + else + /* Use external clock, no interrupts */ + writel(SYSTICK_CTRL_EN, &systick->ctrl); + + /* + * If the TENMS field is inexact or wrong, specify the clock rate using + * CONFIG_SYS_HZ_CLOCK. + */ +#if defined(CONFIG_SYS_HZ_CLOCK) + gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#else + gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100; +#endif + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + gd->arch.lastinc = read_timer(); + + return 0; +} + +/* return milli-seconds timer value */ +ulong get_timer(ulong base) +{ + unsigned long long t = get_ticks() * 1000; + + return (ulong)((t / gd->arch.timer_rate_hz)) - base; +} + +unsigned long long get_ticks(void) +{ + u32 now = read_timer(); + + if (now >= gd->arch.lastinc) + gd->arch.tbl += (now - gd->arch.lastinc); + else + gd->arch.tbl += (TIMER_MAX_VAL - gd->arch.lastinc) + now; + + gd->arch.lastinc = now; + + return gd->arch.tbl; +} + +ulong get_tbclk(void) +{ + return gd->arch.timer_rate_hz; +} -- 2.7.4

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[U-Boot] [PATCH] tiny-printf: add static to locally used functions
by Masahiro Yamada 16 Mar '17

16 Mar '17

These two functions are only used in lib/tiny-printf.c . Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- lib/tiny-printf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c index dfa8432..6def8f9 100644 --- a/lib/tiny-printf.c +++ b/lib/tiny-printf.c @@ -22,7 +22,7 @@ struct printf_info { void (*putc)(struct printf_info *info, char ch); }; -void putc_normal(struct printf_info *info, char ch) +static void putc_normal(struct printf_info *info, char ch) { putc(ch); } @@ -52,7 +52,7 @@ static void div_out(struct printf_info *info, unsigned long *num, out_dgt(info, dgt); } -int _vprintf(struct printf_info *info, const char *fmt, va_list va) +static int _vprintf(struct printf_info *info, const char *fmt, va_list va) { char ch; char *p; -- 2.7.4

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[U-Boot] [U-Boot 0/2] add spl_early_init to fix rk3288 board broken issue
by Eddie Cai 16 Mar '17

16 Mar '17

Andrew F. Davis's below patch broke rk3288 based board. that is because we call spl_init in board_init_f which is at very early stage. What Andrew want to fix is calling spl_init very late. That patch will make malloc_base, limit, ptr not initualized in spl_init when we call spl_init in board_init_f. This patch set add spl_early_init. it can be called in board_init_f. So we can fix this issue by using spl_early_init. commit b3d2861eb20a795b99292b823c923935df26dfc6 Author: Andrew F. Davis <afd(a)ti.com> Date: Fri Jan 27 10:39:19 2017 -0600 spl: Remove overwrite of relocated malloc limit Eddie Cai (2): spl: add spl_early_init rockchip: use spl_early_init instead of spl_init arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- common/spl/spl.c | 54 ++++++++++++++++++++++++++----- include/asm-generic/global_data.h | 1 + include/spl.h | 12 ++++++- 4 files changed, 59 insertions(+), 10 deletions(-) -- 2.7.4

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