December 2017 - U-Boot

[U-Boot] WG: Linux hang
by Siegmund, Jan 07 Dec '17

07 Dec '17

Hi all, does anybody have an idea for the following problem? * FPGA is programmed using an overlay * FPGA writes to SDRAM via the FPGA2SDRAM-bridge * Linux hangs and the watchdog resets the board (the FPGA stays programmed) * After the reset and boot, the FPGA is reprogrammed using the same overlay * Now, the FPGA can write to the SDRAM without a problem The environment: *Board: DE0-NANO-SoC *U-Boot: 2017.11 *Kernel: 4.14.0-rc7 (review-v4.14-rc7-non-dt-support-v5.1 branch) The overlay: /dts-v1/; /plugin/; / { fragment@0 { target-path = "/soc/base_fpga_region"; #address-cells = <1>; #size-cells = <1>; __overlay__ { #address-cells = <1>; #size-cells = <1>; fpga-bridges = <&fpga_bridge0 &fpga_bridge1>; firmware-name = "foo_base.rbf"; fpga-bridge@ffc25080 { compatible = "altr,socfpga-fpga2sdram-bridge"; reg = <0xffc25080 0x4>; bridge-enable = <1>; }; foo@ff200000 { compatible= "altr,bar"; interrupt-parent = <&intc>; interrupts = <0 40 4>; }; }; }; }; Thanks

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[U-Boot] Please pull from u-boot-i2c
by Heiko Schocher 07 Dec '17

07 Dec '17

Hello Tom, please pull from u-boot-i2c master The following changes since commit c8e1ca3ebfd21915f6f2e399c9ca1cd3d7a4b076: tools: omapimage: fix corner-case in byteswap path (2017-12-05 21:56:29 -0500) are available in the git repository at: git://git.denx.de/u-boot-i2c.git master for you to fetch changes up to 28df8ed07f2ae936e9af28c146d555ed4d0c122a: cmd: i2c: Fix use sdram sub command with CONFIG_DM_I2C (2017-12-07 09:29:35 +0100) ---------------------------------------------------------------- Alan Ott (2): i2c: at91_i2c: Wait for TXRDY after sending the first byte i2c: at91_i2c: remove the .probe_chip function Beniamino Galvani (4): i2c: meson: improve Kconfig description i2c: meson: reduce timeout i2c: meson: fix return codes on error i2c: meson: add some comments Nobuhiro Iwamatsu (1): cmd: i2c: Fix use sdram sub command with CONFIG_DM_I2C cmd/i2c.c | 14 ++++++++++++-- drivers/i2c/Kconfig | 7 ++++++- drivers/i2c/at91_i2c.c | 24 ++---------------------- drivers/i2c/meson_i2c.c | 31 ++++++++++++++++++++++--------- 4 files changed, 42 insertions(+), 34 deletions(-) travis build looks good, see: https://travis-ci.org/hsdenx/u-boot-i2c/builds/312841815 bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs(a)denx.de

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[U-Boot] tiny printf limits
by Frank Mori Hess 07 Dec '17

07 Dec '17

Shouldn't tiny printf abort or something when it encounters a printf format string it doesn't support? Right now, it just silently skips it while leaving the associated argument in place, resulting in the arguments getting shifted onto the wrong format strings. -- Frank

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[U-Boot] [PATCH v2 0/4] sunxi: Ease eMMC usage and flashing
by Maxime Ripard 07 Dec '17

07 Dec '17

Hi, Here is a set of patches that have been sitting in some variations for quite some time now. This is mostly to ease the eMMC (and MMC, to some extent) flashing using fastboot that in turn rely on GPT. The Allwinner SoCs need to have the SPL located right in the middle of a traditional GPT, at 8kB. To deal with this, we would basically have two options: - Use the already in-tree solution to move the partition entries to another arbitrary offset in the MMC. - Use a smaller number of partitions entries Both are non-standards, but are dealt with nicely by the regular tools and users (at least on a Linux system). However, the first solution is quite confusing for users (that needs to be aware where the partitions will be), might be less flexible because not all tools will allow to create partitions for things between the GPT main entry and the partition entries, and might confuse tools if such a setup is available. In our case, using the first solution, gdisk will for example refuse to create a partition for the SPL. The second solution though seems to be well handled by all the tools, and just feels the same, except that you end up with a smaller number of partitions. In our case, that number is 56 partitions (16 sectors before the SPL, 1 sector for the protective MBR, 1 sector for the GPT header, and 4 partition entries per sector) instead of 128, which doesn't sound very impractical either. The two first patches deal with that. We then provide a default partitionning scheme. I'd like feedback on that one. I appreciate that having a good default in such a case, but I'd like to have a reasonably simple layout that works good enough to install a distro. I'm a bit short on background on what an EFI partition is supposed to look like, and what a good size would be. I'd really like some input on this. Finally, we enable fastboot flashing to be able to flash a pristine system just by using FEL, fastboot oem format, and then fastboot flash for the various components. Let me know what you think, Maxime Changes from v2: - Added Andre's tags - Rebased on 2018.01-rc1 - Changed the rootfs UUID for freedesktop's Changes from v1: - Changed the boot partition name to ESP - Used default UUID for the rootfs and esp partitions Maxime Ripard (4): part: efi: Add a Kconfig option for the number of partition entries part: efi: Add default number of partition entries for sunxi sunxi: Add default partition scheme fastboot: Enable flashing by default on sunxi cmd/fastboot/Kconfig | 1 + disk/Kconfig | 14 ++++++++++++++ include/configs/sunxi-common.h | 17 +++++++++++++++++ include/part_efi.h | 2 +- 4 files changed, 33 insertions(+), 1 deletion(-) base-commit: 9da7fb4a39149c3061cb148bfbaa76b4b52b9008 -- git-series 0.9.1

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[U-Boot] [PATCH 01/15] ARM: rmobile: Add R8A77970 SoC
by Marek Vasut 07 Dec '17

07 Dec '17

Add bits to support yet another SoC, the R8A77970 V3M . Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/arm/dts/r8a77970.dtsi | 392 ++++++++++++++++++++++++++ arch/arm/mach-rmobile/Kconfig.64 | 3 + arch/arm/mach-rmobile/cpu_info.c | 1 + arch/arm/mach-rmobile/include/mach/rmobile.h | 1 + arch/arm/mach-rmobile/memmap-gen3.c | 23 ++ include/configs/rcar-gen3-common.h | 4 + include/dt-bindings/clock/r8a77970-cpg-mssr.h | 48 ++++ include/dt-bindings/power/r8a77970-sysc.h | 32 +++ 8 files changed, 504 insertions(+) create mode 100644 arch/arm/dts/r8a77970.dtsi create mode 100644 include/dt-bindings/clock/r8a77970-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a77970-sysc.h diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi new file mode 100644 index 0000000000..15f4af15cf --- /dev/null +++ b/arch/arm/dts/r8a77970.dtsi @@ -0,0 +1,392 @@ +/* + * Device Tree Source for the r8a77970 SoC + * + * Copyright (C) 2016-2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/ { + compatible = "renesas,r8a77970"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0>; + clocks = <&cpg CPG_CORE 0>; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller { + compatible = "cache"; + power-domains = <&sysc 21>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + u-boot,dm-pre-reloc; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + u-boot,dm-pre-reloc; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + u-boot,dm-pre-reloc; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1010000 0 0x1000>, + <0 0xf1020000 0 0x20000>, + <0 0xf1040000 0 0x20000>, + <0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77970-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + u-boot,dm-pre-reloc; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77970-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77970-sysc"; + reg = <0 0xe6180000 0 0x440>; + #power-domain-cells = <1>; + }; + + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a77970"; + reg = <0 0xe6060000 0 0x50c>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc 32>; + resets = <&cpg 407>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + u-boot,dm-pre-reloc; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77970", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77970", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77970", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 96>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77970", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 96>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x37>, <&dmac1 0x36>, + <&dmac2 0x37>, <&dmac2 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 517>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77970", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77970", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77970", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x57>, <&dmac1 0x56>, + <&dmac2 0x57>, <&dmac2 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77970", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x59>, <&dmac1 0x58>, + <&dmac2 0x59>, <&dmac2 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 203>; + status = "disabled"; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77970", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc 32>; + resets = <&cpg 812>; + phy-mode = "rgmii-id"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index c79b39ded6..49949390dc 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -9,6 +9,9 @@ config R8A7795 config R8A7796 bool "Renesas SoC R8A7796" +config R8A77970 + bool "Renesas SoC R8A77970" + endchoice choice diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 5c8cb3f666..6f6116dccc 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -61,6 +61,7 @@ static const struct { { RMOBILE_CPU_TYPE_R8A7794, "R8A7794" }, { RMOBILE_CPU_TYPE_R8A7795, "R8A7795" }, { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" }, + { RMOBILE_CPU_TYPE_R8A77970, "R8A77970" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index b413859a4d..deface50ab 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -33,6 +33,7 @@ #define RMOBILE_CPU_TYPE_R8A7794 0x4C #define RMOBILE_CPU_TYPE_R8A7795 0x4F #define RMOBILE_CPU_TYPE_R8A7796 0x52 +#define RMOBILE_CPU_TYPE_R8A77970 0x54 #ifndef __ASSEMBLY__ u32 rmobile_get_cpu_type(void); diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c index f3156ab01a..eeeb270568 100644 --- a/arch/arm/mach-rmobile/memmap-gen3.c +++ b/arch/arm/mach-rmobile/memmap-gen3.c @@ -49,6 +49,26 @@ static struct mm_region r8a7796_mem_map[] = { } }; +static struct mm_region r8a77970_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe0000000UL, + .phys = 0xe0000000UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + struct mm_region *mem_map = r8a7795_mem_map; void rcar_gen3_memmap_fixup(void) @@ -62,5 +82,8 @@ void rcar_gen3_memmap_fixup(void) case RMOBILE_CPU_TYPE_R8A7796: mem_map = r8a7796_mem_map; break; + case RMOBILE_CPU_TYPE_R8A77970: + mem_map = r8a77970_mem_map; + break; } } diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 2815e241de..30a98b8ada 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -44,7 +44,11 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } /* MEMORY */ +#if defined(CONFIG_R8A77970) +#define CONFIG_SYS_TEXT_BASE 0x58280000 +#else #define CONFIG_SYS_TEXT_BASE 0x50000000 +#endif #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define DRAM_RSV_SIZE 0x08000000 diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h new file mode 100644 index 0000000000..4146395595 --- /dev/null +++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a77970 CPG Core Clocks */ +#define R8A77970_CLK_Z2 0 +#define R8A77970_CLK_ZR 1 +#define R8A77970_CLK_ZTR 2 +#define R8A77970_CLK_ZTRD2 3 +#define R8A77970_CLK_ZT 4 +#define R8A77970_CLK_ZX 5 +#define R8A77970_CLK_S1D1 6 +#define R8A77970_CLK_S1D2 7 +#define R8A77970_CLK_S1D4 8 +#define R8A77970_CLK_S2D1 9 +#define R8A77970_CLK_S2D2 10 +#define R8A77970_CLK_S2D4 11 +#define R8A77970_CLK_LB 12 +#define R8A77970_CLK_CL 13 +#define R8A77970_CLK_ZB3 14 +#define R8A77970_CLK_ZB3D2 15 +#define R8A77970_CLK_DDR 16 +#define R8A77970_CLK_CR 17 +#define R8A77970_CLK_CRD2 18 +#define R8A77970_CLK_SD0H 19 +#define R8A77970_CLK_SD0 20 +#define R8A77970_CLK_RPC 21 +#define R8A77970_CLK_RPCD2 22 +#define R8A77970_CLK_MSO 23 +#define R8A77970_CLK_CANFD 24 +#define R8A77970_CLK_CSI0 25 +#define R8A77970_CLK_FRAY 26 +#define R8A77970_CLK_CP 27 +#define R8A77970_CLK_CPEX 28 +#define R8A77970_CLK_R 29 +#define R8A77970_CLK_OSC 30 + +#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h new file mode 100644 index 0000000000..bf54779d16 --- /dev/null +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77970_PD_CA53_CPU0 5 +#define R8A77970_PD_CA53_CPU1 6 +#define R8A77970_PD_CR7 13 +#define R8A77970_PD_CA53_SCU 21 +#define R8A77970_PD_A2IR0 23 +#define R8A77970_PD_A3IR 24 +#define R8A77970_PD_A2IR1 27 +#define R8A77970_PD_A2IR2 28 +#define R8A77970_PD_A2IR3 29 +#define R8A77970_PD_A2SC0 30 +#define R8A77970_PD_A2SC1 31 + +/* Always-on power area */ +#define R8A77970_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */ -- 2.15.0

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[U-Boot] [PATCH] clk: rmobile: Fix typo in R8A7796 RPC clock table entry
by Marek Vasut 07 Dec '17

07 Dec '17

Fix a copy-paste typo in the clock table entry, s/7795/7796/. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/clk/renesas/clk-rcar-gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 5abb171827..4ef35ba47e 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -558,7 +558,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), - DEF_MOD("rpc", 917, R8A7795_CLK_RPC), + DEF_MOD("rpc", 917, R8A7796_CLK_RPC), DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), -- 2.15.0

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[U-Boot] [PATCH] arm: arm64: only use general regs
by Peng Fan 07 Dec '17

07 Dec '17

When compiling with android toolchain, there is an instruction "str q0, [x8],#16", but x8 is not 16bytes aligned, this instruction will trigger sync abort. So, following Linux kernel, only use general regs for arm64. If not, compiler may use simd registers Q[x]. We need to avoid using simd registers in U-Boot, because load/store Q[x] has restriction that 128bits aligned when str/ldr. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5881fdc8e2..4db0398dde 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -18,7 +18,7 @@ arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) -arch-$(CONFIG_ARM64) =-march=armv8-a +arch-$(CONFIG_ARM64) =-march=armv8-a -mgeneral-regs-only # On Tegra systems we must build SPL for the armv4 core on the device # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH -- 2.14.1

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[U-Boot] [PATCH] cmd: i2c: Fix use sdram sub command with CONFIG_DM_I2C
by Nobuhiro Iwamatsu 07 Dec '17

07 Dec '17

sdram sub command of i2c command does not support Drivers Model. This adds Drivers Model support to sdram sub command. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- cmd/i2c.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/cmd/i2c.c b/cmd/i2c.c index 3dd7c6ba4d..bfddf8be1b 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -1156,7 +1156,10 @@ static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) uint chip; u_char data[128]; u_char cksum; - int j; + int j, ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif static const char *decode_CAS_DDR2[] = { " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD" @@ -1210,7 +1213,14 @@ static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) */ chip = simple_strtoul (argv[1], NULL, 16); - if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) { +#ifdef CONFIG_DM_I2C + ret = i2c_get_cur_bus_chip(chip, &dev); + if (!ret) + ret = dm_i2c_read(dev, 0, data, sizeof(data)); +#else + ret = i2c_read(chip, 0, 1, data, sizeof(data)); +#endif + if (ret) { puts ("No SDRAM Serial Presence Detect found.\n"); return 1; } -- 2.15.0

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[U-Boot] [PATCH 0/2] Fix the I2C on SAMA5D3
by Alan Ott 07 Dec '17

07 Dec '17

Two patches to fix the I2C on SAMA5D3. The first fixes a race condition in pushing TX data to the hardware, and the second removes an errant probe_chip function which prevents devices from being probed properly These have been tested on master and on 2017.07 Alan Ott (2): i2c: at91_i2c: Wait for TXRDY after sending the first byte i2c: at91_i2c: remove the .probe_chip function drivers/i2c/at91_i2c.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) -- 2.9.3

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[U-Boot] [PATCH 0/4] meson i2c driver cleanups
by Beniamino Galvani 07 Dec '17

07 Dec '17

Some cleanups for the u-boot meson i2c driver. Beniamino Galvani (4): i2c: meson: improve Kconfig description i2c: meson: reduce timeout i2c: meson: fix return codes on error i2c: meson: add some comments drivers/i2c/Kconfig | 7 ++++++- drivers/i2c/meson_i2c.c | 31 ++++++++++++++++++++++--------- 2 files changed, 28 insertions(+), 10 deletions(-) -- 2.14.3

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