December 2017 - U-Boot

[U-Boot] [PATCH] arm64: zynqmp: Use only earlycon bootargs instead of full one
by Michal Simek 08 Dec '17

08 Dec '17

This is the same patch as was done earlier. Please look at Linux patch: "arm64: zynqmp: Use only earlycon bootargs instead of full one" (sha1: f3609c8d4af28b9cc22ca49bf8e529b582ec188c) Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index fbf281ed53d6..f3020a57600a 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -28,7 +28,7 @@ }; chosen { - bootargs = "earlycon=cdns,mmio,0xff000000,115200n8"; + bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; -- 1.9.1

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[U-Boot] [PATCH] arm64: zynqmp: Remove undocumented dma properties
by Michal Simek 08 Dec '17

08 Dec '17

Remove overfetch, ratectrl, include-sg and src-issue dma properties. Driver is not using them and they are also not documented in the binding doc. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Acked-by: Kedareswara rao Appana <appanad(a)xilinx.com> --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 9 --------- arch/arm/dts/zynqmp-zcu102-revA.dts | 9 --------- 5 files changed, 45 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 1f3c30277a41..04d82c4d2ec9 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -43,16 +43,10 @@ /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ - xlnx,overfetch; /* for testing purpose */ - xlnx,ratectrl = <0>; /* for testing purpose */ - xlnx,src-issue = <31>; }; &fpd_dma_chan2 { status = "okay"; - xlnx,ratectrl = <100>; /* for testing purpose */ - xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan3 { @@ -61,7 +55,6 @@ &fpd_dma_chan4 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan5 { @@ -70,7 +63,6 @@ &fpd_dma_chan6 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan7 { @@ -79,7 +71,6 @@ &fpd_dma_chan8 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &gem3 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 87df36012ed7..7dfe960135a5 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -53,16 +53,10 @@ /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ - xlnx,overfetch; /* for testing purpose */ - xlnx,ratectrl = <0>; /* for testing purpose */ - xlnx,src-issue = <31>; }; &fpd_dma_chan2 { status = "okay"; - xlnx,ratectrl = <100>; /* for testing purpose */ - xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan3 { @@ -71,7 +65,6 @@ &fpd_dma_chan4 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan5 { @@ -80,7 +73,6 @@ &fpd_dma_chan6 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan7 { @@ -89,7 +81,6 @@ &fpd_dma_chan8 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &gem2 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 799b87a04c13..648e3ba79939 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -55,16 +55,10 @@ /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ - xlnx,overfetch; /* for testing purpose */ - xlnx,ratectrl = <0>; /* for testing purpose */ - xlnx,src-issue = <31>; }; &fpd_dma_chan2 { status = "okay"; - xlnx,ratectrl = <100>; /* for testing purpose */ - xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan3 { @@ -73,7 +67,6 @@ &fpd_dma_chan4 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan5 { @@ -82,7 +75,6 @@ &fpd_dma_chan6 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan7 { @@ -91,7 +83,6 @@ &fpd_dma_chan8 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &lpd_dma_chan1 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 6de8296b7353..fbf281ed53d6 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -41,16 +41,10 @@ /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ - xlnx,overfetch; /* for testing purpose */ - xlnx,ratectrl = <0>; /* for testing purpose */ - xlnx,src-issue = <31>; }; &fpd_dma_chan2 { status = "okay"; - xlnx,ratectrl = <100>; /* for testing purpose */ - xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan3 { @@ -59,7 +53,6 @@ &fpd_dma_chan4 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan5 { @@ -68,7 +61,6 @@ &fpd_dma_chan6 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan7 { @@ -77,7 +69,6 @@ &fpd_dma_chan8 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &gem1 { diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 2e382562c496..64a883b96e3a 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -81,16 +81,10 @@ /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ - xlnx,overfetch; /* for testing purpose */ - xlnx,ratectrl = <0>; /* for testing purpose */ - xlnx,src-issue = <31>; }; &fpd_dma_chan2 { status = "okay"; - xlnx,ratectrl = <100>; /* for testing purpose */ - xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan3 { @@ -99,7 +93,6 @@ &fpd_dma_chan4 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan5 { @@ -108,7 +101,6 @@ &fpd_dma_chan6 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan7 { @@ -117,7 +109,6 @@ &fpd_dma_chan8 { status = "okay"; - xlnx,include-sg; /* for testing purpose */ }; &gem3 { -- 1.9.1

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[U-Boot] [PATCH] arm64: zynqmp: Add generic compatible string for I2C EEPROM
by Michal Simek 08 Dec '17

08 Dec '17

From: Javier Martinez Canillas <javier(a)dowhile0.org> The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas <javier(a)dowhile0.org> Acked-by: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-ep108.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index b0096f14b444..a16ffdc3f0ce 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -65,7 +65,7 @@ status = "okay"; clock-frequency = <400000>; eeprom@54 { - compatible = "at,24c64"; + compatible = "atmel,24c64"; reg = <0x54>; }; }; @@ -74,7 +74,7 @@ status = "okay"; clock-frequency = <400000>; eeprom@55 { - compatible = "at,24c64"; + compatible = "atmel,24c64"; reg = <0x55>; }; }; -- 1.9.1

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[U-Boot] Please pull u-boot-fsl-qoriq master
by York Sun 08 Dec '17

08 Dec '17

Tom, The following changes since commit 9da7fb4a39149c3061cb148bfbaa76b4b52b9008: Prepare v2018.01-rc1 (2017-12-04 18:27:17 -0500) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git d798a6ee6436c7d2bcbf3fa6bda01daa4411a493 for you to fetch changes up to d798a6ee6436c7d2bcbf3fa6bda01daa4411a493: armv8: ls1088a: Add nand support for ls1088ardb (2017-12-06 14:56:31 -0800) ---------------------------------------------------------------- Ashish Kumar (3): armv8: ls1088a: Unset USE_BOOTCOMMAND in defconfig armv8: ls1088: Add fsl_fdt_fixup_flash armv8: ls1088a: Add nand support for ls1088ardb Bhaskar Upadhaya (1): armv8: ls1012a: Modify Kernel and Environment offset Prabhakar Kushwaha (1): armv8: fsl-layerscape: Add support of disabling core prefetch Ran Wang (1): armv8: Workaround for USB erratua on LS1012A Udit Agarwal (3): armv8: LS1088A_QSPI: SECURE_BOOT: Images validation armv8: LS1088A_QSPI: Add secure boot defconfigs for QSPI boot. armv8: LS2080A_SECURE_BOOT: Enable CONFIG_FSL_LS_PPA. Vinitha Pillai-B57223 (1): SECURE BOOT: Add fall back option Yogesh Gaur (2): driver: net: fsl-mc: flib changes for MC 10.3.0 driver: fsl-mc: MC object cleanup when DPL not loaded arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 38 + .../armv8/fsl-layerscape/doc/README.core_prefetch | 20 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 27 +- board/freescale/ls1088a/Kconfig | 2 + board/freescale/ls1088a/MAINTAINERS | 12 + board/freescale/ls1088a/ls1088a.c | 35 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 47 + configs/ls1088aqds_qspi_defconfig | 1 + configs/ls1088aqds_sdcard_qspi_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 48 + configs/ls1088ardb_qspi_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 5 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 5 +- drivers/net/fsl-mc/dpbp.c | 42 +- drivers/net/fsl-mc/dpio/dpio.c | 43 +- drivers/net/fsl-mc/dpmac.c | 41 +- drivers/net/fsl-mc/dpni.c | 332 ++---- drivers/net/fsl-mc/dprc.c | 27 +- drivers/net/fsl-mc/fsl_dpmng_cmd.h | 5 +- drivers/net/fsl-mc/mc.c | 240 +++-- drivers/net/ldpaa_eth/ldpaa_eth.c | 283 +++--- drivers/net/ldpaa_eth/ldpaa_eth.h | 5 +- include/configs/ls1012a_common.h | 4 +- include/configs/ls1012afrdm.h | 2 +- include/configs/ls1021atwr.h | 33 +- include/configs/ls1043a_common.h | 31 +- include/configs/ls1046a_common.h | 12 +- include/configs/ls1046ardb.h | 8 +- include/configs/ls1088a_common.h | 3 - include/configs/ls1088aqds.h | 21 + include/configs/ls1088ardb.h | 52 +- include/fsl-mc/fsl_dpbp.h | 62 +- include/fsl-mc/fsl_dpio.h | 64 +- include/fsl-mc/fsl_dpmac.h | 69 +- include/fsl-mc/fsl_dpni.h | 1065 +++++++------------- include/fsl-mc/fsl_dprc.h | 79 +- include/fsl-mc/fsl_mc_cmd.h | 50 +- include/fsl-mc/fsl_mc_private.h | 8 +- 40 files changed, 1445 insertions(+), 1384 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.core_prefetch create mode 100644 configs/ls1088aqds_qspi_SECURE_BOOT_defconfig create mode 100644 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig Thanks. York

2 2

[U-Boot] [PATCH v2 1/2] drivers/reset: support rockchip reset drivers
by Kever Yang 08 Dec '17

08 Dec '17

From: Elaine Zhang <zhangqing(a)rock-chips.com> Create driver to support all Rockchip SoCs soft reset. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); } reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl); i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c"; Signed-off-by: Elaine Zhang <zhangqing(a)rock-chips.com> Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2: - fix Kconfig more than 80 length - use MACRO for reset bits in one reg - use rkclr/set_reg for reg access - add rockchip_reset_bind() - use dev_read_addr_size() instead of fdtdec_ drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-rockchip.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index ce46e27..97a78d7 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -74,4 +74,13 @@ config AST2500_RESET resets that are supported by watchdog. The main limitation though is that some reset signals, like I2C or MISC reset multiple devices. +config RESET_ROCKCHIP + bool "Reset controller driver for Rockchip SoCs" + depends on DM_RESET && CLK + default y + help + Support for reset controller on rockchip SoC. The main limitation + though is that some reset signals, like I2C or MISC reset multiple + devices. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 252cefe..7d7e080 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c new file mode 100644 index 0000000..01047a2 --- /dev/null +++ b/drivers/reset/reset-rockchip.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <reset-uclass.h> +#include <linux/io.h> +#include <asm/arch/hardware.h> +#include <dm/lists.h> +/* + * Each reg has 16 bits reset signal for devices + * Note: Not including rk2818 and older SoCs + */ +#define ROCKCHIP_RESET_NUM_IN_REG 16 + +struct rockchip_reset_priv { + void __iomem *base; + /* Rockchip reset reg locate at cru controller */ + u32 reset_reg_offset; + /* Rockchip reset reg number */ + u32 reset_reg_num; +}; + +static int rockchip_reset_request(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num); + + if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num) + return -EINVAL; + + return 0; +} + +static int rockchip_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int rockchip_reset_assert(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG; + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, + priv->base + (bank * 4)); + + rk_setreg(priv->base + (bank * 4), BIT(offset)); + + return 0; +} + +static int rockchip_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG; + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, + priv->base + (bank * 4)); + + rk_clrreg(priv->base + (bank * 4), BIT(offset)); + + return 0; +} + +struct reset_ops rockchip_reset_ops = { + .request = rockchip_reset_request, + .free = rockchip_reset_free, + .rst_assert = rockchip_reset_assert, + .rst_deassert = rockchip_reset_deassert, +}; + +static int rockchip_reset_probe(struct udevice *dev) +{ + struct rockchip_reset_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_read_addr_size(dev, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0)) + return -EINVAL; + + addr += priv->reset_reg_offset; + priv->base = ioremap(addr, size); + + debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__, + priv->base, priv->reset_reg_offset, priv->reset_reg_num); + + return 0; +} + +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number) +{ + struct udevice *rst_dev; + struct rockchip_reset_priv *priv; + int ret; + + ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset", + dev_ofnode(pdev), &rst_dev); + if (ret) { + debug("Warning: No rockchip reset driver: ret=%d\n", ret); + return ret; + } + priv = malloc(sizeof(struct rockchip_reset_priv)); + priv->reset_reg_offset = reg_offset; + priv->reset_reg_num = reg_number; + rst_dev->priv = priv; + + return 0; +} + +U_BOOT_DRIVER(rockchip_reset) = { + .name = "rockchip_reset", + .id = UCLASS_RESET, + .probe = rockchip_reset_probe, + .ops = &rockchip_reset_ops, + .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv), +}; -- 1.9.1

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[U-Boot] [RFC PATCH] test: py: Disable sleep test for qemu targets
by Michal Simek 08 Dec '17

08 Dec '17

Qemu for arm32/arm64 has a problem with time setup. That's why sleep test is failing. Add boardidentity marker to remove specific boards from running that test. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- If you want to add this checking in one patch and then put it to one test then it is fine for me. --- test/py/conftest.py | 28 ++++++++++++++++++++++++++++ test/py/pytest.ini | 1 + test/py/tests/test_sleep.py | 1 + 3 files changed, 30 insertions(+) diff --git a/test/py/conftest.py b/test/py/conftest.py index 6e66a48c15fd..1812ff340e6a 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -436,6 +436,33 @@ def setup_boardspec(item): if required_boards and ubconfig.board_type not in required_boards: pytest.skip('board "%s" not supported' % ubconfig.board_type) +def setup_boardidentity(item): + """Process any 'boardidentity' marker for a test. + + Such a marker lists the set of board identity that a test does/doesn't + support. If tests are being executed on an unsupported board, the test is + marked to be skipped. + + Args: + item: The pytest test item. + + Returns: + Nothing. + """ + mark = item.get_marker('boardidentity') + if not mark: + return + required_boards = [] + for board in mark.args: + if board.startswith('!'): + if ubconfig.board_identity == board[1:]: + pytest.skip('board identity not supported') + return + else: + required_boards.append(board) + if required_boards and ubconfig.board_identity not in required_boards: + pytest.skip('board identity not supported') + def setup_buildconfigspec(item): """Process any 'buildconfigspec' marker for a test. @@ -503,6 +530,7 @@ def pytest_runtest_setup(item): start_test_section(item) setup_boardspec(item) + setup_boardidentity(item) setup_buildconfigspec(item) setup_requiredtool(item) diff --git a/test/py/pytest.ini b/test/py/pytest.ini index 67e514f42058..9d64671814de 100644 --- a/test/py/pytest.ini +++ b/test/py/pytest.ini @@ -8,4 +8,5 @@ [pytest] markers = boardspec: U-Boot: Describes the set of boards a test can/can't run on. + boardidentity: U-Boot: Describes the board identity a test can/can't run on. buildconfigspec: U-Boot: Describes Kconfig/config-header constraints. diff --git a/test/py/tests/test_sleep.py b/test/py/tests/test_sleep.py index 64e057132622..02a8a85b0e22 100644 --- a/test/py/tests/test_sleep.py +++ b/test/py/tests/test_sleep.py @@ -5,6 +5,7 @@ import pytest import time +(a)pytest.mark.boardidentity("!qemu") def test_sleep(u_boot_console): """Test the sleep command, and validate that it sleeps for approximately the correct amount of time.""" -- 1.9.1

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[U-Boot] Add option to send files with y-modem protocol [from U-boot => to target host]
by Alex Rodriges 08 Dec '17

08 Dec '17

Hi, when a network connection is not available, U-Boot can load files via the serial port. The U-Boot commands for loading files over the UART all have the same options. Is it possible implement two way file transfer in xyzModem - use loady, loadb to send files from U-boot to target host? So, by analogy with using loady to load files, # Loading with the y-modem protocol board> loady [load address] [baud rate] we will use 'sendy'to send files: # Sending with the y-modem protocol from U-boot to target host sendy [offset address] [size] [baud rate] or maybe sendy /path/to/file/we/want/to/transfer [baud rate] And on target host we use Minicom, TeraTerm or Hyper Terminal to receive files. How to modify xuzModem.c, cmd_load.c for sending files? B.Regards, Alex

1 0

[U-Boot] [PATCH] sunxi: Add the TBS A711 tablet
by Maxime Ripard 08 Dec '17

08 Dec '17

The TBS Tablet sports an LVDS display, an eMMC, an external SD, USB devices and USB OTG. Signed-off-by: Maxime Ripard <maxime.ripard(a)free-electrons.com> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun8i-a83t-tbs-a711.dts | 76 ++++++++++++++++++++++++++++++++++++ configs/tbs_a711_defconfig | 23 +++++++++++ 3 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun8i-a83t-tbs-a711.dts create mode 100644 configs/tbs_a711_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f54adb21847a..f82d13695136 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -316,7 +316,8 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ sun8i-a83t-bananapi-m3.dtb \ - sun8i-a83t-cubietruck-plus.dtb + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dts dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ diff --git a/arch/arm/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/dts/sun8i-a83t-tbs-a711.dts new file mode 100644 index 000000000000..80e8b1cc9050 --- /dev/null +++ b/arch/arm/dts/sun8i-a83t-tbs-a711.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2017 Ondřej Jirman + * Ondřej Jirman <megous(a)megous.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a83t.dtsi" + +/ { + model = "TBS A711 Tablet"; + compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig new file mode 100644 index 000000000000..03deae084e90 --- /dev/null +++ b/configs/tbs_a711_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A83T=y +CONFIG_DRAM_TYPE=7 +CONFIG_DRAM_CLK=648 +CONFIG_DRAM_ZQ=15355 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH11" +CONFIG_AXP_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-tbs-a711" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_AXP_DCDC5_VOLT=1200 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y -- 2.14.3

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[U-Boot] dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init()
by Y.b. Lu 08 Dec '17

08 Dec '17

Hi Simon, I found your below patch just dropping mmc_create() for probe procedure of DM. Actually the description seemed to be not the things this patch did. dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init() Do you have any suggestion to fix it? mmc_create() will allocate mmc structure and the DM in fsl_esdhc also allocate mmc structure in fsl_esdhc_plat structure. Do we need to rework the mmc_create(), or move rest initialization of mmc_create() in to fsl_esdhc_probe() ? Thanks a lot. Best regards, Yangbo Lu

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[U-Boot] [PATCH v5 00/20] Add FPGA driver, SDRAM driver, generic firmware loader and booting U-Boot.
by tien.fong.chee＠intel.com 08 Dec '17

08 Dec '17

From: Tien Fong Chee <tien.fong.chee(a)intel.com> This patchset adding FPGA drivers, SDRAM drivers, and generic firmware loader. The patchset also enable fpga loadfs to program FPGA, SPL loading U-boot and booting to U-boot console. This version mainly resolved comments from Marek in [v4]. Please note that generic firmware loader is an independent driver, which can be used to load whatever into target location, then consumer driver would use it to program whatever, ie. the FPGA. This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-socfpga.git . [v4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg268160.html v4 -> v5 changes: ----------------- - Created generic firmware loader which is very similar to Linux firmware loader - Changed the fpga loadfs driver to use generic firmware loader for loading RBF files from flash to memory and then program FPGA. Patchset history ---------------- [v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg261831.html [v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg265192.html [v3]: https://www.mail-archive.com/u-boot@lists.denx.de/msg266981.html Tien Fong Chee (20): ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager dts: Add FPGA bitstream properties to Arria 10 DTS arm: socfpga: Add Arria 10 SoCFPGA programming interface dts: Enable fpga-mgr node build for Arria 10 SPL fs: Enable generic filesystems interface support in SPL. arm: socfpga: Remove static declaration on spl_mmc_find_device function common: Generic firmware loader for file system arm: socfpga: Fix with the correct polling on bit is set arm: socfpga: Add FPGA drivers for Arria 10 FPGA loadfs arm: socfpga: Rename the gen5 sdram driver to more specific name arm: socfpga: Add DRAM bank size initialization function arm: socfpga: Add DDR driver for Arria 10 configs: Add DDR Kconfig support for Arria 10 arm: socfpga: Enable SPL memory allocation arm: socfpga: Improve comments for Intel SoCFPGA program header arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 arm: socfpga: Adding clock frequency info for U-Boot arm: socfpga: Adding SoCFPGA info for both SPL and U-Boot arm: socfpga: Enable DDR working arm: socfpga: Enable SPL booting U-boot arch/arm/dts/socfpga_arria10.dtsi | 6 + arch/arm/mach-socfpga/Kconfig | 1 + arch/arm/mach-socfpga/board.c | 18 + arch/arm/mach-socfpga/include/mach/boot0.h | 11 +- .../include/mach/fpga_manager_arria10.h | 32 + arch/arm/mach-socfpga/include/mach/sdram.h | 434 +----------- arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 2 + .../include/mach/{sdram.h => sdram_gen5.h} | 6 +- arch/arm/mach-socfpga/misc_arria10.c | 5 - arch/arm/mach-socfpga/spl.c | 49 ++ cmd/fpga.c | 2 +- common/Makefile | 1 + common/fs_loader.c | 304 +++++++++ common/spl/Kconfig | 8 + common/spl/spl_mmc.c | 2 +- configs/socfpga_arria10_defconfig | 58 +- doc/README.SPL | 1 + .../fpga/altera-socfpga-a10-fpga-mgr.txt | 11 + drivers/ddr/altera/Kconfig | 2 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_arria10.c | 733 +++++++++++++++++++++ drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0 drivers/fpga/altera.c | 40 +- drivers/fpga/fpga.c | 8 + drivers/fpga/socfpga_arria10.c | 378 ++++++++++- fs/Makefile | 1 + include/altera.h | 6 + include/configs/socfpga_common.h | 23 +- include/fpga.h | 2 + include/fs_loader.h | 30 + include/spl.h | 2 + 31 files changed, 1716 insertions(+), 463 deletions(-) copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%) create mode 100644 common/fs_loader.c create mode 100644 drivers/ddr/altera/sdram_arria10.c rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%) create mode 100644 include/fs_loader.h -- 2.2.0

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