January 2017 - U-Boot

[U-Boot] [PATCH v3 1/2] mx6sabresd: Make SPL DDR configuration to match the DCD table
by Fabio Estevam 05 Apr '17

05 Apr '17

From: Fabio Estevam <fabio.estevam(a)nxp.com> When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code. This causes stability issues like the ones reported at 7dbda25ecd6d7c ("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also: http://lists.denx.de/pipermail/u-boot/2016-September/266355.html . As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case. The idea is simple: just use the DCD table and write directly to the DDR registers. Retrieved the DCD tables from: board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg and board/freescale/mx6sabresd/mx6qp.cfg (NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga) This method makes it easier for people converting from non-SPL to SPL code. Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- Changes since v1: - Use the correct mx6qp dcd table - Create ddr_init() to write the DCD values - Specify where the DCD tables come from board/freescale/mx6sabresd/mx6sabresd.c | 351 ++++++++++++++++++-------------- 1 file changed, 197 insertions(+), 154 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index f836ecb..3c36395 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -682,125 +682,6 @@ int checkboard(void) #include <spl.h> #include <libfdt.h> -const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_reset = 0x00020030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, -}; - -const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = { - .dram_sdclk_0 = 0x00000030, - .dram_sdclk_1 = 0x00000030, - .dram_cas = 0x00000030, - .dram_ras = 0x00000030, - .dram_reset = 0x00000030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_dqm2 = 0x00000030, - .dram_dqm3 = 0x00000030, - .dram_dqm4 = 0x00000030, - .dram_dqm5 = 0x00000030, - .dram_dqm6 = 0x00000030, - .dram_dqm7 = 0x00000030, -}; - -const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { - .grp_ddr_type = 0x000C0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -const struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x001F001F, - .p0_mpwldectrl1 = 0x001F001F, - .p1_mpwldectrl0 = 0x00440044, - .p1_mpwldectrl1 = 0x00440044, - .p0_mpdgctrl0 = 0x434B0350, - .p0_mpdgctrl1 = 0x034C0359, - .p1_mpdgctrl0 = 0x434B0350, - .p1_mpdgctrl1 = 0x03650348, - .p0_mprddlctl = 0x4436383B, - .p1_mprddlctl = 0x39393341, - .p0_mpwrdlctl = 0x35373933, - .p1_mpwrdlctl = 0x48254A36, -}; - -const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = { - .p0_mpwldectrl0 = 0x001B001E, - .p0_mpwldectrl1 = 0x002E0029, - .p1_mpwldectrl0 = 0x001B002A, - .p1_mpwldectrl1 = 0x0019002C, - .p0_mpdgctrl0 = 0x43240334, - .p0_mpdgctrl1 = 0x0324031A, - .p1_mpdgctrl0 = 0x43340344, - .p1_mpdgctrl1 = 0x03280276, - .p0_mprddlctl = 0x44383A3E, - .p1_mprddlctl = 0x3C3C3846, - .p0_mpwrdlctl = 0x2E303230, - .p1_mpwrdlctl = 0x38283E34, -}; - -/* MT41K128M16JT-125 */ -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -831,44 +712,209 @@ static void gpr_init(void) } } -/* - * This section requires the differentiation between iMX6 Sabre boards, but - * for now, it will configure only for the mx6q variant. - */ -static void spl_dram_init(void) +static int mx6q_dcd_table[] = { + 0x020e0798, 0x000C0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000030, + 0x020e05b0, 0x00000030, + 0x020e0524, 0x00000030, + 0x020e051c, 0x00000030, + 0x020e0518, 0x00000030, + 0x020e050c, 0x00000030, + 0x020e05b8, 0x00000030, + 0x020e05c0, 0x00000030, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000030, + 0x020e0788, 0x00000030, + 0x020e0794, 0x00000030, + 0x020e079c, 0x00000030, + 0x020e07a0, 0x00000030, + 0x020e07a4, 0x00000030, + 0x020e07a8, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e05ac, 0x00000030, + 0x020e05b4, 0x00000030, + 0x020e0528, 0x00000030, + 0x020e0520, 0x00000030, + 0x020e0514, 0x00000030, + 0x020e0510, 0x00000030, + 0x020e05bc, 0x00000030, + 0x020e05c4, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001F001F, + 0x021b0810, 0x001F001F, + 0x021b480c, 0x001F001F, + 0x021b4810, 0x001F001F, + 0x021b083c, 0x43270338, + 0x021b0840, 0x03200314, + 0x021b483c, 0x431A032F, + 0x021b4840, 0x03200263, + 0x021b0848, 0x4B434748, + 0x021b4848, 0x4445404C, + 0x021b0850, 0x38444542, + 0x021b4850, 0x4935493A, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x09444040, + 0x021b000c, 0x555A7975, + 0x021b0010, 0xFF538F64, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x005A1023, + 0x021b0040, 0x00000027, + 0x021b0000, 0x831A0000, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + +static int mx6qp_dcd_table[] = { + 0x020e0798, 0x000c0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000030, + 0x020e05b0, 0x00000030, + 0x020e0524, 0x00000030, + 0x020e051c, 0x00000030, + 0x020e0518, 0x00000030, + 0x020e050c, 0x00000030, + 0x020e05b8, 0x00000030, + 0x020e05c0, 0x00000030, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000030, + 0x020e0788, 0x00000030, + 0x020e0794, 0x00000030, + 0x020e079c, 0x00000030, + 0x020e07a0, 0x00000030, + 0x020e07a4, 0x00000030, + 0x020e07a8, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e05ac, 0x00000030, + 0x020e05b4, 0x00000030, + 0x020e0528, 0x00000030, + 0x020e0520, 0x00000030, + 0x020e0514, 0x00000030, + 0x020e0510, 0x00000030, + 0x020e05bc, 0x00000030, + 0x020e05c4, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001b001e, + 0x021b0810, 0x002e0029, + 0x021b480c, 0x001b002a, + 0x021b4810, 0x0019002c, + 0x021b083c, 0x43240334, + 0x021b0840, 0x0324031a, + 0x021b483c, 0x43340344, + 0x021b4840, 0x03280276, + 0x021b0848, 0x44383A3E, + 0x021b4848, 0x3C3C3846, + 0x021b0850, 0x2e303230, + 0x021b4850, 0x38283E34, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08c0, 0x24912249, + 0x021b48c0, 0x24914289, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x24444040, + 0x021b000c, 0x555A7955, + 0x021b0010, 0xFF320F64, + 0x021b0014, 0x01ff00db, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x005A1023, + 0x021b0040, 0x00000027, + 0x021b0400, 0x14420000, + 0x021b0000, 0x831A0000, + 0x021b0890, 0x00400C58, + 0x00bb0008, 0x00000000, + 0x00bb000c, 0x2891E41A, + 0x00bb0038, 0x00000564, + 0x00bb0014, 0x00000040, + 0x00bb0028, 0x00000020, + 0x00bb002c, 0x00000020, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + +static void ddr_init(int *table, int size) { - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; + int i; - if (is_mx6dqp()) { - mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr); - } else { - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); - } + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + if (is_mx6dq()) + ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); + else if (is_mx6dqp()) + ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); } void board_init_f(ulong dummy) { + /* DDR initialization */ + spl_dram_init(); + /* setup AIPS and disable watchdog */ arch_cpu_init(); @@ -884,9 +930,6 @@ void board_init_f(ulong dummy) /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); - /* DDR initialization */ - spl_dram_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); -- 2.7.4

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[U-Boot] [PATCH 00/10] sunxi: Add basic PSCI support to enable SMP on the A80's first cluster
by Chen-Yu Tsai 03 Apr '17

03 Apr '17

Hi everyone, This series adds basic PSCI support for the A80 to enable SMP on the first cluster. This at least allows people to use more than one core. The term "basic" is used because the series does not add support for multi-cluster cache and power management. The PSCI code is based on existing code for all the single cluster SoCs, and the kernel patches for MCPM SMP I did some time ago. Unfortunately only SMP works at this time. The last patch does not actually work. While the system is indeed booted non-secure, tested by trying to write to secure SRAM and the results not sticking, reads from the GIC CPU interface shows that it's still returning the secure copy of registers, and since we use a secure monitor FIQ to do core power down, the FIQ gets passed to the kernel. The patch is included so people with in-depth ARM knowledge could probably help work out what is wrong. Regards ChenYu Chen-Yu Tsai (10): ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80 sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80 sunxi: Add base address of secure SRAM B for sun9i/A80 sunxi: Use secure SRAM B for secure RAM for sun9i/A80 sunxi: Add PRCM register definition for sun9i/A80 sunxi: Add CPUCFG register definitions for sun9i/A80 sunxi: Add support for TZPC on sun9i/A80 sunxi: Add basic PSCI implementation for A80 sunxi: Enable PSCI on sun9i/A80 sunxi: Add PSCI core power off support for A80's first cluster arch/arm/cpu/armv7/Kconfig | 1 + arch/arm/cpu/armv7/sunxi/Makefile | 5 + arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 322 +++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/tzpc.c | 6 + arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 5 + arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 51 ++++ arch/arm/include/asm/arch-sunxi/prcm_sun9i.h | 55 +++++ arch/arm/include/asm/arch-sunxi/tzpc.h | 4 + arch/arm/mach-sunxi/board.c | 3 +- board/sunxi/Kconfig | 4 + include/configs/sun9i.h | 4 + 11 files changed, 459 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h -- 2.10.2

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[U-Boot] [PATCH] ARM: dts: uniphier: move aliases node up to make fdtgrep happy
by Masahiro Yamada 03 Apr '17

03 Apr '17

Currently, fdtgrep would not accept uniphier-ph1-ld20-ref.dtb and uniphier-ph1-ld11-ref.dtb unless the aliases node comes the first in the root node. $ make -s uniphier_pxs2_ld6b_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld20-ref [snip] LDS spl/u-boot-spl.lds LD spl/u-boot-spl OBJCOPY spl/u-boot-spl-nodtb.bin FDTGREP spl/u-boot-spl.dtb Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT /aliases node must come before all other nodes Error: FDT_ERR_BADMAGIC make[1]: *** [spl/u-boot-spl.dtb] Error 1 make: *** [spl/u-boot-spl] Error 2 This commit moves the aliases node as the error message from the fdtgrep tool suggests, although this requirement does not sound reasonable to me. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- Simon, I'd like to avoid this patch if possible. Not figured out the root cause of the problem yet? arch/arm/dts/uniphier-ph1-ld11-ref.dts | 18 +++++++++--------- arch/arm/dts/uniphier-ph1-ld20-ref.dts | 18 +++++++++--------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts index a624a49..88e7f53 100644 --- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts @@ -14,15 +14,6 @@ model = "UniPhier PH1-LD11 Reference Board"; compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11"; - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { serial0 = &serial0; serial1 = &serial1; @@ -35,6 +26,15 @@ i2c4 = &i2c4; i2c5 = &i2c5; }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &ethsc { diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts index 108adeb..a55d90c 100644 --- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts @@ -14,15 +14,6 @@ model = "UniPhier PH1-LD20 Reference Board"; compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20"; - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { serial0 = &serial0; serial1 = &serial1; @@ -35,6 +26,15 @@ i2c4 = &i2c4; i2c5 = &i2c5; }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0xc0000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &ethsc { -- 1.9.1

2 4

[U-Boot] [PATCH v2 00/63] x86: Add initial support for 64-bit U-Boot
by Simon Glass 03 Apr '17

03 Apr '17

At present U-Boot runs entirely in 32-bit mode on x86, except for the initial switch from 16-bit mode. On 64-bit machines it is possible to run in 64-bit mode. This series starts the process of adding this support. The main benefit of 64-bit mode for a boot loader is direct access to all available memory. There are also more registers, but this makes very little difference. This feature is implemented by putting all of the 32-bit code in an SPL build. SPL then runs through all the init that has to be done in 32-bit mode, changes to 64-bit mode and then jumps to U-Boot proper. Typically the total code size increases slightly. For example, on link in 32-bit mode, U-Boot has around 480KB of code (admittedly with a large number of features enabled). In 64-bit mode, U-Boot falls to around 460KB, but SPL adds another 60KB, for a net increase of 40KB. Partly this is due to code duplication and partly it is due to the worse code density of 64-bit code on x86. Many major features are not implemented yet, for example: - SDRAM sizing - Booting linux - FSP support - EFI support - SCSI device init - Running video ROMs Still, this is a big step forward towards full 64-bit support. To enable it, select CONFIG_X86_RUN_64BIT. This series is available at u-boot-x86/64-working Changes in v2: - Show the error value in spl_spi_load_image() - Move table-related changes from a later patch - Rebase to mainline - Drop the write_smbios_table_wrapper() function - Drop change to gma.c - Output error code values in debug() statements - Fix cast in bd82x6x_video_probe() also - Fix cast in get_guid_hob_data() also - Move table-related changes to an earlier patch - Add the 'val' parameter to longjmp() - Drop patch 'video: Use ulong for video frame buffer address' - Add a new 64-bit link config instead of changing the existing one Simon Glass (63): console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPL spl: spi: Add a debug message if loading fails spl: Makefile: Define SPL_ earlier spl: Allow CPU drivers to be used in SPL spl: Allow PCI drivers to be used in SPL spl: Allow RTC drivers to be used in SPL spl: Allow timer drivers to be used in SPL spl: Allow PCH drivers to be used in SPL spl: Don't create a BSS padding when it is separate x86: Use unsigned long for address in table generation WIP: x86: Update mpspec to build on 64-bit machines x86: Add basic support for U-Boot as a 64-bit EFI application x86: ivybridge: Declare global data where it is used x86: ivybridge: Add more debugging for failures x86: ivybridge: Fix types for 64-bit compilation x86: dts: Mark serial as needed before relocation x86: fsp: Fix cast for 64-bit compilation x86: lib: Fix types and casts for 64-bit compilation x86: Add Kconfig options to build 64-bit U-Boot x86: Kconfig: Add location options for 16/32-bit init x86: Use X86_16BIT_INIT instead of X86_RESET_VECTOR x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR x86: ivybridge: Allow 32-bit init to move to SPL x86: Add 64-bit start-up code x86: board_f: Update init sequence for 64-bit startup x86: board_r: Set the global data pointer after relocation x86: Do relocation before clearing BSS x86: Refactor relocation to prepare for 64-bit x86: Add support for 64-bit relocation x86: Tidy up use of size_t in relocation x86: Add an SPL implementation x86: Move the i386 code into its own directory x86: Add cpu code for x86_64 x86: Support global_data on x86_64 x86: Fix up CONFIG_X86_64 check x86: Add a link script for 64-bit x86 x86: Add a link script for SPL x86: Add SPL build rules for start-up code x86: Fix up byteorder.h for x86_64 x86: Drop flag_is_changable() on x86_64 x86: Fix up type sizes for 64-bit x86: Mention the MRC region in the README x86: ivybridge: Skipt SATA init in SPL x86: ivybridge: Provide a dummy SDRAM init for 64-bit x86: Don't try to run the VGA BIOS in 64-bit mode x86: Don't build call64 and setjmp on 64-bit x86: Don't build cpu files which are not supported on 64-bit x86: Don't build 32-bit efi files on x86_64 x86: Don't try to boot Linux from SPL x86: Drop interrupt support in 64-bit mode x86: Support jumping from SPL to U-Boot x86: Move pirq_routing_table to global_data x86: Move turbo_state to global_data x86: Change irq_already_routed to a local variable x86: Move call64 to the i386 directory x86: Move setjmp to the i386 directory x86: Add a dummy setjmp implementation for x86_64 x86: link: Add a text base for 64-bit U-Boot x86: link: Add SPL declarations to the binman image x86: link: Set up device tree for SPL x86: link: Add build options for SPL x86: Update compile/link flags to support 64-bit U-Boot x86: link: Add a config for 64-bit U-Boot Makefile | 7 +- arch/x86/Kconfig | 85 ++++ arch/x86/Makefile | 9 +- arch/x86/config.mk | 30 +- arch/x86/cpu/Makefile | 24 +- arch/x86/cpu/config.mk | 8 +- arch/x86/cpu/cpu.c | 504 -------------------- arch/x86/cpu/i386/Makefile | 9 + arch/x86/cpu/{ => i386}/call64.S | 3 + arch/x86/cpu/i386/cpu.c | 599 ++++++++++++++++++++++++ arch/x86/cpu/{interrupts.c => i386/interrupt.c} | 6 +- arch/x86/cpu/{ => i386}/setjmp.S | 0 arch/x86/cpu/intel_common/Makefile | 10 +- arch/x86/cpu/irq.c | 14 +- arch/x86/cpu/ivybridge/Makefile | 9 +- arch/x86/cpu/ivybridge/bd82x6x.c | 2 + arch/x86/cpu/ivybridge/cpu.c | 4 +- arch/x86/cpu/ivybridge/lpc.c | 2 + arch/x86/cpu/ivybridge/model_206ax.c | 2 + arch/x86/cpu/ivybridge/northbridge.c | 2 + arch/x86/cpu/ivybridge/sata.c | 4 +- arch/x86/cpu/ivybridge/sdram.c | 37 +- arch/x86/cpu/ivybridge/sdram_nop.c | 29 ++ arch/x86/cpu/start64.S | 39 ++ arch/x86/cpu/turbo.c | 8 +- arch/x86/cpu/u-boot-64.lds | 76 +++ arch/x86/cpu/u-boot-spl.lds | 74 +++ arch/x86/cpu/u-boot.lds | 2 +- arch/x86/cpu/x86_64/Makefile | 6 + arch/x86/cpu/x86_64/cpu.c | 48 ++ arch/x86/cpu/x86_64/interrupts.c | 30 ++ arch/x86/cpu/x86_64/setjmp.c | 20 + arch/x86/dts/chromebook_link.dts | 15 +- arch/x86/dts/serial.dtsi | 1 + arch/x86/dts/u-boot.dtsi | 19 + arch/x86/include/asm/acpi_table.h | 2 +- arch/x86/include/asm/byteorder.h | 17 +- arch/x86/include/asm/cpu.h | 12 + arch/x86/include/asm/fsp/fsp_hob.h | 4 +- arch/x86/include/asm/global_data.h | 8 +- arch/x86/include/asm/mp.h | 3 + arch/x86/include/asm/mpspec.h | 10 +- arch/x86/include/asm/posix_types.h | 5 + arch/x86/include/asm/sfi.h | 2 +- arch/x86/include/asm/spl.h | 8 + arch/x86/include/asm/tables.h | 2 +- arch/x86/include/asm/types.h | 5 + arch/x86/lib/Makefile | 11 + arch/x86/lib/acpi_table.c | 4 +- arch/x86/lib/bios.c | 4 +- arch/x86/lib/bootm.c | 2 + arch/x86/lib/elf_x86_64_efi.lds | 3 + arch/x86/lib/init_helpers.c | 2 +- arch/x86/lib/interrupts.c | 5 + arch/x86/lib/mpspec.c | 14 +- arch/x86/lib/pinctrl_ich6.c | 2 +- arch/x86/lib/pirq_routing.c | 14 +- arch/x86/lib/reloc_x86_64.c | 90 ++++ arch/x86/lib/relocate.c | 102 +++- arch/x86/lib/sfi.c | 6 +- arch/x86/lib/spl.c | 149 ++++++ arch/x86/lib/tables.c | 11 +- arch/x86/lib/zimage.c | 2 +- board/google/Kconfig | 7 + board/google/chromebook_link/Kconfig | 5 +- board/google/chromebook_link/MAINTAINERS | 7 + common/board_f.c | 14 +- common/board_r.c | 5 + common/console.c | 30 +- common/spl/Kconfig | 47 ++ common/spl/spl_spi.c | 5 +- configs/chromebook_link64_defconfig | 94 ++++ configs/chromebook_link_defconfig | 23 +- doc/README.x86 | 1 + drivers/Makefile | 5 + drivers/misc/qfw.c | 4 +- drivers/pci/pci_rom.c | 2 +- drivers/video/ivybridge_igd.c | 6 +- include/configs/chromebook_link.h | 9 + include/smbios.h | 4 +- lib/smbios.c | 22 +- scripts/Makefile.spl | 18 +- 82 files changed, 1871 insertions(+), 673 deletions(-) create mode 100644 arch/x86/cpu/i386/Makefile rename arch/x86/cpu/{ => i386}/call64.S (98%) create mode 100644 arch/x86/cpu/i386/cpu.c rename arch/x86/cpu/{interrupts.c => i386/interrupt.c} (99%) rename arch/x86/cpu/{ => i386}/setjmp.S (100%) create mode 100644 arch/x86/cpu/ivybridge/sdram_nop.c create mode 100644 arch/x86/cpu/start64.S create mode 100644 arch/x86/cpu/u-boot-64.lds create mode 100644 arch/x86/cpu/u-boot-spl.lds create mode 100644 arch/x86/cpu/x86_64/Makefile create mode 100644 arch/x86/cpu/x86_64/cpu.c create mode 100644 arch/x86/cpu/x86_64/interrupts.c create mode 100644 arch/x86/cpu/x86_64/setjmp.c create mode 100644 arch/x86/include/asm/spl.h create mode 100644 arch/x86/lib/reloc_x86_64.c create mode 100644 arch/x86/lib/spl.c create mode 100644 configs/chromebook_link64_defconfig -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 00/22] dm: Add support for a 'live' device tree
by Simon Glass 01 Apr '17

01 Apr '17

So far U-Boot uses a 'flat' device tree, which means that it is decoded on the fly as needed. This uses the libfdt library and avoids needing extra memory for additional tables. For some time there has been discussion about moving U-Boot to use a 'live' tree, where the device tree is decoded at start-up into a set of hierarchical structures with pointers. The advantages are: - It is somewhat faster to access (in particular scanning and looking for a parent) - It permits the device tree to be changed at run-time (this is not recommended at present since devices store the offset of their device tree node and updating the tree may invalidate that). This could be useful for overlays, for example. - It allows nodes to be referenced by a single pointer, instead of the current device tree pointer plus offset The disadvantages are: - It requires more memory - It takes (a little) time to build the live tree - It adds more complexity under the hood, including an additional abstraction layer This series is an attempt to introduce a useful live tree feature into U-Boot. There are many options and trade-offs. This series is the culmination of quite a bit of thought and experimentation. The approach used in this series is: - Before relocation the flat tree is used, to avoid extra memory usage and time. In general, there is not much access before relocation since most drivers are not started up. So there is little benefit in having a live tree - After relocation the live tree is built. At this point the CPU should be running quickly and there is plenty of memory. All available devices will be bound so the overhead of building the live tree may be outweighed by its greater efficiency. As a simplification, this series supports only one tree or the other. When the live tree is active, the flat tree cannot be used. That makes it easy to know the current state and avoids confusion over mixing offset and node pointers. Some drivers will need to be used both before and after relocation. This means that they must support both the flat and the live tree. To support this, the concept of a node 'reference' is defined. A reference can hold either a node offset (for the flat tree) or a node pointer (for the live tree). This allows drivers to access values from the tree regardless of which tree is in use. In addition, since most device tree access happens in the context of a device (struct udevice), a new 'dev_read' layer is provided to read device tree configuration associated with a device. This encapsulates the details of exactly how this information is read. I have taken the view that code compatibility with Linux is desirable. So the of_access.c file brings in code from Linux with very little modification. As new access methods are needed we should be able to bring in more code and avoid writing it ourselves in U-Boot. Conversion of drivers and subsystems to support the live tree (as well as flat tree) is fairly easy. A patch is included to add support to the GPIO uclass, and the cros_ec device is converted over to provide a driver example. Once I have comments on this series I will update it to build for all boards, to pass current tests and to tidy up the code. I will also add tests for the live tree and finish conversion for sandbox. So for now I am just looking for high-level comments, rather than a detailed code review. Simon Glass (22): dm: core: Set return value first in lists_bind_fdt() dm: core: atmel: Dont export dm_scan_fdt_node() Update WARN_ON() to return a value dm: Add livetree definitions dm: Add livetree access functions dm: Add a function to create a 'live' device tree dm: Build a live tree after relocation dm: Add support for device tree references dm: Add a place to put extra device-tree reading functions dm: core: Add device-based functions to access DT properties dm: core: Allow binding a device from a live tree dm: core: Add a method to find a driver for a livetree node dm: core: Scan the live tree when setting up driver model dm: core: Add a way to find a device by its live-tree node dm: core: Add a way to find a device by node reference dm: gpio: Refactor to prepare for live tree support dm: gpio: Add live tree support dm: gpio: Drop blank line in gpio_xlate_offs_flags() comment dm: gpio: sandbox: Use dm_read...() functions to access DT cros_ec: Fix debug() statement in ec_command_inptr() cros_ec: Convert to support live tree sandbox: Move to use live tree common/board_r.c | 12 ++ configs/sandbox_defconfig | 1 + drivers/core/Makefile | 1 + drivers/core/device.c | 27 +++- drivers/core/lists.c | 80 +++++++++- drivers/core/of_dev.c | 55 +++++++ drivers/core/of_extra.c | 37 +++++ drivers/core/of_ref.c | 218 +++++++++++++++++++++++++ drivers/core/root.c | 61 ++++++- drivers/core/uclass.c | 78 +++++++++ drivers/gpio/atmel_pio4.c | 3 +- drivers/gpio/gpio-uclass.c | 100 ++++++++---- drivers/gpio/sandbox.c | 10 +- drivers/misc/cros_ec.c | 36 ++--- drivers/misc/cros_ec_sandbox.c | 2 +- dts/Kconfig | 11 ++ include/asm-generic/global_data.h | 3 + include/asm-generic/gpio.h | 7 +- include/cros_ec.h | 8 +- include/dm/device-internal.h | 6 + include/dm/device.h | 19 ++- include/dm/lists.h | 5 + include/dm/of.h | 53 ++++++ include/dm/of_access.h | 164 +++++++++++++++++++ include/dm/of_dev.h | 68 ++++++++ include/dm/of_extra.h | 46 ++++++ include/dm/of_ref.h | 306 +++++++++++++++++++++++++++++++++++ include/dm/root.h | 16 -- include/dm/uclass-internal.h | 22 +++ include/dm/uclass.h | 23 +++ include/fdtdec.h | 34 ---- include/linux/compat.h | 8 +- include/livetree.h | 24 +++ lib/Makefile | 1 + lib/fdtdec.c | 32 ---- lib/livetree.c | 320 +++++++++++++++++++++++++++++++++++++ lib/of_access.c | 328 ++++++++++++++++++++++++++++++++++++++ 37 files changed, 2066 insertions(+), 159 deletions(-) create mode 100644 drivers/core/of_dev.c create mode 100644 drivers/core/of_extra.c create mode 100644 drivers/core/of_ref.c create mode 100644 include/dm/of.h create mode 100644 include/dm/of_access.h create mode 100644 include/dm/of_dev.h create mode 100644 include/dm/of_extra.h create mode 100644 include/dm/of_ref.h create mode 100644 include/livetree.h create mode 100644 lib/livetree.c create mode 100644 lib/of_access.c -- 2.11.0.483.g087da7b7c-goog

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Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase
by Yao Yuan 27 Mar '17

27 Mar '17

Hi Jagan, Do you have any comments? Thanks for your work and you know it's important for QSPI with S25FS512S. It seems S25FS512S can't support the SECT_4K, right? And it better to retain the disable_4kb, but we can add a flag in dts to select whether enable it. Best Regards, Yao From: Yao Yuan Sent: Wednesday, November 30, 2016 3:23 PM To: 'Jagan Teki' <jagan(a)openedev.com> Subject: sf: Remove spansion_s25fss_disable_4KB_erase Hi Jagan, I have noticed that you have a patch to: commit 116e005cfd00021424f5f81eeedd355e4ca72f07 Author: Jagan Teki <jagan(a)amarulasolutions.com<mailto:jagan@amarulasolutions.com>> Date: Tue Nov 15 22:57:42 2016 +0530 - Removed spansion_s25fss_disable_4KB_erase code - Add SECT_4K for S25FS512S chip Do you have any test for this patch? Because with this patch, my QSPI driver can't working with S25FS512S. As you said, In spansion S25FS-S family the physical sectors are grouped as normal and parameter sectors. Parameter sectors are 4kB in size with 8 set located at the bottom or top address of a device. Normal sectors are similar to other flash family with sizes of 64kB or 32 kB. Base on the RM and in my understand, not all the erase sectors are 4-kb. In my case regions are: 1. 0-32KiB (8*4KiB) - 4K_ERASE (0x20/0x21) 2. 32 - 256 - SE_CMD (0xd8/0xdc) 3. Rest of the flash SE_CMD (0xd8/0xdc) 4. To erase whole flash you can also use CHIP_ERASE_CMD (0x60/0xC7) command, you just need to add one more mtd partition that will cover whole flash. So we can't add SECT_4K for S25FS512S chip. If we add SECT_4K for S25FS512S chip, that means all the erase sectors are 4-kb. But I think it's not right. And disable 4kb is necessary for me, I also suggestion to add a flag to select whether enable 4-kb. if (of_property_read_bool(np, "spi-nor, disable-4kb")) { spansion_s25fs_disable_4kb_erase(); } else ... In dts: &qspi { qflash0: s25fs512s@0 { compatible = "spansion, s25fs512s"; spi-nor, disable-4kb #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; }; Attachment is the RM for S25FS-S. Thanks. Best Regards, Yao

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[U-Boot] [PATCH v2] Makefile: Fix linking with modern binutils
by Joel Stanley 22 Mar '17

22 Mar '17

Since Binutils 1a9ccd70f9a7[1] u-boot will not link targets that set CONFIG_SYS_TEXT_BASE=0 with the following error: LD u-boot arm-linux-gnueabi-ld.bfd: u-boot: Not enough room for program headers, try linking with -N arm-linux-gnueabi-ld.bfd: final link failed: Bad value The issue can reproduced the bad binutils and the rock2_defconfig target. This issue was also encountered by the powerpc kernel[2], with the fix being to pass --no-dynamic-linker for linkers newer than 2.26 when this flag was introduced. The option tells ld that the PIE or shared lib does not need loaded program headers. Ubuntu Zesty's Binutils 2.27.51.20161202 hits this error. [1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=1a9ccd7… [2] https://git.kernel.org/cgit/linux/kernel/git/powerpc/linux.git/commit/?h=ne… Signed-off-by: Joel Stanley <joel(a)jms.id.au> --- v2: - use ld-option to test for the flag instead of the version, as suggested by Måns - update commit message with clarification from Alan Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index dfed58bec661..c98a8361654a 100644 --- a/Makefile +++ b/Makefile @@ -793,6 +793,10 @@ ALL-y += $(CONFIG_BUILD_TARGET:"%"=%) endif LDFLAGS_u-boot += $(LDFLAGS_FINAL) + +# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards. +LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker) + ifneq ($(CONFIG_SYS_TEXT_BASE),) LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) endif -- 2.11.0

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[U-Boot] Ethernet not detecting on Odroid u3
by Anand Moon 21 Mar '17

21 Mar '17

Hi All, I tried to compile the latest u-boot for Odroid U3. issue is that Ethernet is not able to detected. Please let me know what need to enable USB Ethernet to support tftp boot. Best Regards -Anand ------ U-Boot 2017.01-02075-g4386feb-dirty (Jan 12 2017 - 06:17:08 +0000) CPU: Exynos4412 @ 1 GHz Model: Odroid based on Exynos4412 Board: Odroid based on Exynos4412 Type: u3 DRAM: 2 GiB LDO20(a)VDDQ_EMMC_1.8V: set 1800000 uV; enabling LDO22(a)VDDQ_EMMC_2.8V: set 2800000 uV; enabling LDO21(a)TFLASH_2.8V: set 2800000 uV; enabling MMC: SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1 *** Warning - bad CRC, using default environment Net: No ethernet found. Hit any key to stop autoboot: 0 Odroid # Odroid # Odroid # usb start starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found Odroid # Odroid # Odroid # setenv usbethaddr 02:DE:AD:BE:EF:FF Odroid # usb start Odroid # usb info 1: Hub, USB Revision 2.0 - u-boot EHCI Host Controller - Class: Hub - PacketSize: 64 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 1.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms Odroid # reset

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[U-Boot] [PATCH v3] arm: use common instructions applicable to armv7m & other arm archs
by Vikas Manocha 18 Mar '17

18 Mar '17

This patch cleans the code by using instructions allowed for armv7m as well as other Arm archs. Signed-off-by: Vikas Manocha <vikas.manocha(a)st.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Heiko Schocher <hs(a)denx.de> --- Changes in v3: moved the comment to right location. Changes in v2: reword message commit. Removed info regarding BIC instruction on SP, was creating confusion. arch/arm/lib/crt0.S | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 2f4c14e..d9078aa 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -71,18 +71,12 @@ ENTRY(_main) */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) - ldr sp, =(CONFIG_SPL_STACK) + ldr r0, =(CONFIG_SPL_STACK) #else - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) #endif -#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ - mov r3, sp - bic r3, r3, #7 - mov sp, r3 -#else - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ -#endif - mov r0, sp + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 bl board_init_f_alloc_reserve mov sp, r0 /* set up gd here, outside any C code */ @@ -100,14 +94,9 @@ ENTRY(_main) * 'here' but relocated. */ - ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ -#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ - mov r3, sp - bic r3, r3, #7 - mov sp, r3 -#else - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ -#endif + ldr r0, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ sub r9, r9, #GD_SIZE /* new GD is below bd */ -- 1.9.1

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[U-Boot] [PATCH] usb gadget: increase envstr size in cb_getvar
by Nicolas le bayon 10 Mar '17

10 Mar '17

Hi, I propose you this patch in order to take into account strings larger than actual size (32). I recently faced to 'fastboot.partition-type:userdata' (it was in Android context) but this could be the case for other purposes. I propose to simply double the size. Is it ok for you? Regards --- drivers/usb/gadget/f_fastboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 2160b1c..84e22e4 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -432,7 +432,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) else strcpy(response, "FAILValue not set"); } else { - char envstr[32]; + char envstr[64]; snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd); s = getenv(envstr); -- 1.9.1

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