January 2017 - U-Boot

[U-Boot] [PATCH v2 1/4] mx6qsabreauto: Configure the WEIM controller like the kernel
by Fabio Estevam 03 Feb '17

03 Feb '17

Do the same WEIM initialization as done in the Linux kernel according to arch/arm/boot/dts/imx6qdl-sabreauto.dtsi from kernel 4.9. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- Changes since v1: - None board/freescale/mx6qsabreauto/mx6qsabreauto.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 5fca4d1..13a9b5a 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -221,12 +221,20 @@ static void eimnor_cs_setup(void) { struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; - writel(0x00020181, &weim_regs->cs0gcr1); + /* + * Configure weim like the linux kernel. + * From arch/arm/boot/dts/imx6qdl-sabreauto.dtsi: + * + * fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + * 0x0000c000 0x1404a38e 0x00000000>; + */ + + writel(0x00620081, &weim_regs->cs0gcr1); writel(0x00000001, &weim_regs->cs0gcr2); - writel(0x0a020000, &weim_regs->cs0rcr1); + writel(0x1c022000, &weim_regs->cs0rcr1); writel(0x0000c000, &weim_regs->cs0rcr2); - writel(0x0804a240, &weim_regs->cs0wcr1); - writel(0x00000120, &weim_regs->wcr); + writel(0x1404a38e, &weim_regs->cs0wcr1); + writel(0x00000000, &weim_regs->wcr); set_chipselect_size(CS0_128); } -- 2.7.4

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[U-Boot] [RESEND] video: bcm2835: add support for reading from the video-mode environment variable
by Brian Masney 03 Feb '17

03 Feb '17

The bcm2835 driver polls the monitor and selects the highest resolution that is available. This patch allows optionally setting the video-mode environment variable so that a different video resolution can be used. If the environment variable is not specified, then it will fall back to using the old behavior of using the maximum allowable resolution. This patch is needed to fix an issue booting an upstream Linux kernel on a Raspberry Pi 2 with a Pi Top screen. Previously, the bcm2835 would select the 1366x768 resolution (which is a supported resolution), however the screen would be unreadable. (See https://www.flickr.com/photos/masneyb/30942037416/ for picture). Using this patch, the resolution 1024x768 can be selected and is readable on the screen. Signed-off-by: Brian Masney <masneyb(a)onstation.org> --- Here is a link to my initial submission of this patch that did not receive any feedback: http://lists.denx.de/pipermail/u-boot/2016-November/272760.html I updated the patch to ensure that it applies cleanly to the latest master. doc/README.video | 12 ++++++++++++ drivers/video/Makefile | 2 +- drivers/video/bcm2835.c | 42 +++++++++++++++++++++++++++++------------- 3 files changed, 42 insertions(+), 14 deletions(-) diff --git a/doc/README.video b/doc/README.video index e7ae98a..31ceeab 100644 --- a/doc/README.video +++ b/doc/README.video @@ -76,3 +76,15 @@ The sunxi U-Boot driver supports the following video-mode options: For example to always use the hdmi connector, even if no cable is inserted, using edid info when available and otherwise initalizing it at 1024x768@60Hz, use: "setenv video-mode sunxi:1024x768-24@60,monitor=dvi,hpd=0,edid=1". + + +U-Boot bcm2835 video controller driver +====================================== + +The bcm2835 driver supports polling the monitor for the maximum supported +resolution. This can be changed by using the video-mode environment +variable: + +Example: video-mode=bcm2835:1024x768-16@60 + +Note: The frequency is currently not used by the driver. diff --git a/drivers/video/Makefile b/drivers/video/Makefile index db34904..7c13faf 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -36,7 +36,7 @@ obj-$(CONFIG_S6E8AX0) += s6e8ax0.o obj-$(CONFIG_S6E63D6) += s6e63d6.o obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_SED156X) += sed156x.o -obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o +obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o videomodes.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index cc6454f..90fed68 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -10,6 +10,7 @@ #include <phys2bus.h> #include <asm/arch/mbox.h> #include <asm/global_data.h> +#include "videomodes.h" DECLARE_GLOBAL_DATA_PTR; @@ -45,21 +46,36 @@ void lcd_ctrl_init(void *lcdbase) int ret; u32 w, h; u32 fb_start, fb_end; + const char *options; + unsigned int depth = 0, freq = 0; - debug("bcm2835: Query resolution...\n"); - - BCM2835_MBOX_INIT_HDR(msg_query); - BCM2835_MBOX_INIT_TAG_NO_REQ(&msg_query->physical_w_h, - GET_PHYSICAL_W_H); - ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_query->hdr); - if (ret) { - printf("bcm2835: Could not query display resolution\n"); - /* FIXME: How to disable the LCD to prevent errors? hang()? */ - return; + if (video_get_video_mode(&w, &h, &depth, &freq, &options) != 1) { + debug("bcm2835: video_get_video_mode() unsuccessful; polling monitor for defaults\n"); + w = 0; + h = 0; } - w = msg_query->physical_w_h.body.resp.width; - h = msg_query->physical_w_h.body.resp.height; + if (w == 0 || h == 0) { + debug("bcm2835: Query resolution...\n"); + + BCM2835_MBOX_INIT_HDR(msg_query); + BCM2835_MBOX_INIT_TAG_NO_REQ(&msg_query->physical_w_h, + GET_PHYSICAL_W_H); + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, + &msg_query->hdr); + if (ret) { + printf("bcm2835: Could not query display resolution\n"); + /* + * FIXME: How to disable the LCD to prevent errors? + * hang()? */ + return; + } + + w = msg_query->physical_w_h.body.resp.width; + h = msg_query->physical_w_h.body.resp.height; + + depth = 32; + } debug("bcm2835: Setting up display for %d x %d\n", w, h); @@ -71,7 +87,7 @@ void lcd_ctrl_init(void *lcdbase) msg_setup->virtual_w_h.body.req.width = w; msg_setup->virtual_w_h.body.req.height = h; BCM2835_MBOX_INIT_TAG(&msg_setup->depth, SET_DEPTH); - msg_setup->depth.body.req.bpp = 32; + msg_setup->depth.body.req.bpp = depth; BCM2835_MBOX_INIT_TAG(&msg_setup->pixel_order, SET_PIXEL_ORDER); msg_setup->pixel_order.body.req.order = BCM2835_MBOX_PIXEL_ORDER_RGB; BCM2835_MBOX_INIT_TAG(&msg_setup->alpha_mode, SET_ALPHA_MODE); -- 2.9.3

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[U-Boot] Intel e1000 PHY HW reset timeout reasons?
by Kostya Porotchkin 02 Feb '17

02 Feb '17

Hello, I am currently working on u-boot mainline code supporting Marvell Armada armv8 platforms (80x0, 70x0, 37x0). During this coding and testing cycles I found a very strange issue related to u-boot e1000 network driver. The PCIe e1000 NIC is tested on 2 platforms based on the same SoC (8040). On one of these platforms the e1000 card is properly detected on PCIe bus, but fails to activate the HW due to HW PHY reset timeout. If I bypass the timeout error, the e1000 card continues to work without any problem and I am able to run a full Linux system with root on NFS using this network card. Below is the (ugly) change that solves me the PHY reset timeout problem: diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 3332ad9..a40b009 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -4361,7 +4361,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) if (!timeout) { DEBUGOUT("MNG configuration cycle has not " "completed.\n"); - return -E1000_ERR_RESET; +// return -E1000_ERR_RESET; } break; I have found that the similar issue has already been discussed in this email list, but the driver code was not changed and the timeout seems to happen in some test cases. http://lists.denx.de/pipermail/u-boot/2014-September/188544.html I would be glad to get an idea about such timeout reasons and ways to solve this issue on my development platform. Both my platforms are based on Marvell Armada 8040 SoC. 1. Platform-1: PCIe x1, card reset connected to system reset wire No driver WA required. 2. Platform-2: PCIe x4, card reset connected to GPIO, reset released upon PCIe bus probe. e1000 driver WA required for a normal operation. ============================================== E1000 debug log on Platform-2: ============================================== => pci enum PCIE-0: Link up (Gen1-x1, Bus0) => pci 1 Scanning PCI devices on bus 1 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 01.00.00 0x8086 0x107d Network controller 0x00 => ping 192.168.100.200 e1000: e1000#0: DEBUG: iobase 0xf6000000 e1000_set_mac_type e1000_set_media_type copper interface e1000_reset_hw Masking off all interrupts Issuing a global reset to MAC Masking off all interrupts e1000_init_eeprom_params e1000_read_mac_addr e1000_read_eeprom e1000_is_onboard_nvm_eeprom e1000_acquire_eeprom e1000_swfw_sync_acquire e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_spi_eeprom_ready e1000_release_eeprom e1000_swfw_sync_release e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_read_eeprom e1000_is_onboard_nvm_eeprom e1000_acquire_eeprom e1000_swfw_sync_acquire e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_spi_eeprom_ready e1000_release_eeprom e1000_swfw_sync_release e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_read_eeprom e1000_is_onboard_nvm_eeprom e1000_acquire_eeprom e1000_swfw_sync_acquire e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_spi_eeprom_ready e1000_release_eeprom e1000_swfw_sync_release e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000: 68:05:ca:12:4d:dc Warning: e1000#0 MAC addresses don't match: Address in SROM is 68:05:ca:12:4d:dc Address in environment is 00:00:00:00:51:81 e1000_reset_hw Masking off all interrupts Issuing a global reset to MAC Masking off all interrupts e1000_init_hw e1000_set_media_type Initializing the IEEE VLAN e1000_init_rx_addrs Programming MAC Address into RAR[0] Clearing RAR[1-15] Zeroing the MTA e1000_setup_link e1000_read_eeprom e1000_is_onboard_nvm_eeprom e1000_acquire_eeprom e1000_swfw_sync_acquire e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_spi_eeprom_ready e1000_release_eeprom e1000_swfw_sync_release e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_read_eeprom e1000_is_onboard_nvm_eeprom e1000_acquire_eeprom e1000_swfw_sync_acquire e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_spi_eeprom_ready e1000_release_eeprom e1000_swfw_sync_release e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore After fix-ups FlowControl is now = 3 e1000_setup_copper_link e1000_copper_link_preconfig e1000_detect_gig_phy Phy ID = 2a80380 e1000_set_phy_mode e1000_copper_link_igp_setup e1000_phy_reset e1000_phy_hw_reset Resetting Phy... e1000_swfw_sync_acquire e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_swfw_sync_release e1000_get_hw_eeprom_semaphore e1000_put_hw_eeprom_semaphore e1000_get_phy_cfg_done MNG configuration cycle has not completed. Error Resetting the PHY e1000: e1000#0: ERROR: Hardware Initialization Failed ping failed; host 192.168.100.200 is not alive ============================================== Thank you beforehand for your help. Best Regards Konstantin Porotchkin

2 2

[U-Boot] [PATCH v3 2/3] mmc: meson: add MMC driver for Meson GX (S905)
by Heiner Kallweit 02 Feb '17

02 Feb '17

This driver implements MMC support on Meson GX (S905) based systems. It's based on Carlo Caione's work, changes: - BLK support added - general refactoring Signed-off-by: Carlo Caione <carlo(a)caione.org> Signed-off-by: Andreas Färber <afaerber(a)suse.de> Signed-off-by: Heiner Kallweit <hkallweit1(a)gmail.com> --- v2: - addressed review comments - general refactoring v3: - remove config symbol MMC_MESON_GX_SD_PORT --- arch/arm/include/asm/arch-meson/sd_emmc.h | 89 +++++++++ drivers/mmc/Kconfig | 6 + drivers/mmc/Makefile | 1 + drivers/mmc/meson_gx_mmc.c | 291 ++++++++++++++++++++++++++++++ include/configs/meson-gxbb-common.h | 4 + 5 files changed, 391 insertions(+) create mode 100644 arch/arm/include/asm/arch-meson/sd_emmc.h create mode 100644 drivers/mmc/meson_gx_mmc.c diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h new file mode 100644 index 0000000..25dbf60 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2017 Carlo Caione <carlo(a)caione.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SD_EMMC_H__ +#define __SD_EMMC_H__ + +#include <mmc.h> + +#define SDIO_PORT_A 0 +#define SDIO_PORT_B 1 +#define SDIO_PORT_C 2 + +#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ +#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ + +#define MESON_SD_EMMC_CLOCK 0x00 +#define CLK_MAX_DIV 63 +#define CLK_SRC_24M (0 << 6) +#define CLK_SRC_DIV2 (1 << 6) +#define CLK_CO_PHASE_000 (0 << 8) +#define CLK_CO_PHASE_090 (1 << 8) +#define CLK_CO_PHASE_180 (2 << 8) +#define CLK_CO_PHASE_270 (3 << 8) +#define CLK_TX_PHASE_000 (0 << 10) +#define CLK_TX_PHASE_090 (1 << 10) +#define CLK_TX_PHASE_180 (2 << 10) +#define CLK_TX_PHASE_270 (3 << 10) +#define CLK_ALWAYS_ON BIT(24) + +#define MESON_SD_EMMC_CFG 0x44 +#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) +#define CFG_BUS_WIDTH_1 0 +#define CFG_BUS_WIDTH_4 1 +#define CFG_BUS_WIDTH_8 2 +#define CFG_BL_LEN_MASK GENMASK(7, 4) +#define CFG_BL_LEN_SHIFT 4 +#define CFG_BL_LEN_512 (9 << 4) +#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) +#define CFG_RESP_TIMEOUT_256 (8 << 8) +#define CFG_RC_CC_MASK GENMASK(15, 12) +#define CFG_RC_CC_16 (4 << 12) +#define CFG_SDCLK_ALWAYS_ON BIT(18) +#define CFG_AUTO_CLK BIT(23) + +#define MESON_SD_EMMC_STATUS 0x48 +#define STATUS_MASK GENMASK(15, 0) +#define STATUS_ERR_MASK GENMASK(12, 0) +#define STATUS_RXD_ERR_MASK GENMASK(7, 0) +#define STATUS_TXD_ERR BIT(8) +#define STATUS_DESC_ERR BIT(9) +#define STATUS_RESP_ERR BIT(10) +#define STATUS_RESP_TIMEOUT BIT(11) +#define STATUS_DESC_TIMEOUT BIT(12) +#define STATUS_END_OF_CHAIN BIT(13) + +#define MESON_SD_EMMC_IRQ_EN 0x4c + +#define MESON_SD_EMMC_CMD_CFG 0x50 +#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) +#define CMD_CFG_BLOCK_MODE BIT(9) +#define CMD_CFG_R1B BIT(10) +#define CMD_CFG_END_OF_CHAIN BIT(11) +#define CMD_CFG_TIMEOUT_4S (12 << 12) +#define CMD_CFG_NO_RESP BIT(16) +#define CMD_CFG_DATA_IO BIT(18) +#define CMD_CFG_DATA_WR BIT(19) +#define CMD_CFG_RESP_NOCRC BIT(20) +#define CMD_CFG_RESP_128 BIT(21) +#define CMD_CFG_CMD_INDEX_SHIFT 24 +#define CMD_CFG_OWNER BIT(31) + +#define MESON_SD_EMMC_CMD_ARG 0x54 +#define MESON_SD_EMMC_CMD_DAT 0x58 +#define MESON_SD_EMMC_CMD_RSP 0x5c +#define MESON_SD_EMMC_CMD_RSP1 0x60 +#define MESON_SD_EMMC_CMD_RSP2 0x64 +#define MESON_SD_EMMC_CMD_RSP3 0x68 + +struct meson_mmc_platdata { + struct mmc_config cfg; + struct mmc mmc; + void *regbase; + void *w_buf; +}; + +#endif diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 147e52d..ffae684 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -168,6 +168,12 @@ config ZYNQ_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform +config MMC_MESON_GX + bool "Meson GX EMMC controller support" + depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_MESON + help + Support for EMMC host controller on Meson GX ARM SoCs platform (S905) + config ROCKCHIP_SDHCI bool "Arasan SDHCI controller for Rockchip support" depends on DM_MMC && BLK && DM_MMC_OPS diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 6af7f79..baa6531 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -31,6 +31,7 @@ ifdef CONFIG_SUPPORT_EMMC_BOOT obj-$(CONFIG_GENERIC_MMC) += mmc_boot.o endif obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o +obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o obj-$(CONFIG_MMC_SPI) += mmc_spi.o obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c new file mode 100644 index 0000000..612a81e --- /dev/null +++ b/drivers/mmc/meson_gx_mmc.c @@ -0,0 +1,291 @@ +/* + * (C) Copyright 2017 Carlo Caione <carlo(a)caione.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <malloc.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/arch/sd_emmc.h> +#include <dm/device.h> +#include <linux/log2.h> + +static inline void *get_regbase(const struct mmc *mmc) +{ + struct meson_mmc_platdata *pdata = mmc->priv; + + return pdata->regbase; +} + +static inline uint32_t meson_read(struct mmc *mmc, int offset) +{ + return readl(get_regbase(mmc) + offset); +} + +static inline void meson_write(struct mmc *mmc, uint32_t val, int offset) +{ + writel(val, get_regbase(mmc) + offset); +} + +static void meson_mmc_config_clock(struct mmc *mmc) +{ + uint32_t meson_mmc_clk = 0; + unsigned int clk, clk_src, clk_div; + + /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ + if (mmc->clock > 16000000) { + clk = SD_EMMC_CLKSRC_DIV2; + clk_src = CLK_SRC_DIV2; + } else { + clk = SD_EMMC_CLKSRC_24M; + clk_src = CLK_SRC_24M; + } + clk_div = DIV_ROUND_UP(clk, mmc->clock); + + /* 180 phase core clock */ + meson_mmc_clk |= CLK_CO_PHASE_180; + + /* 180 phase tx clock */ + meson_mmc_clk |= CLK_TX_PHASE_180; + + /* clock settings */ + meson_mmc_clk |= clk_src; + meson_mmc_clk |= clk_div; + + meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK); +} + +static int meson_dm_mmc_set_ios(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + uint32_t meson_mmc_cfg; + + meson_mmc_config_clock(mmc); + + meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG); + + meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK; + if (mmc->bus_width == 1) + meson_mmc_cfg |= CFG_BUS_WIDTH_1; + else if (mmc->bus_width == 4) + meson_mmc_cfg |= CFG_BUS_WIDTH_4; + else if (mmc->bus_width == 8) + meson_mmc_cfg |= CFG_BUS_WIDTH_8; + else + return -EINVAL; + + /* 512 bytes block length */ + meson_mmc_cfg &= ~CFG_BL_LEN_MASK; + meson_mmc_cfg |= CFG_BL_LEN_512; + + /* Response timeout 256 clk */ + meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK; + meson_mmc_cfg |= CFG_RESP_TIMEOUT_256; + + /* Command-command gap 16 clk */ + meson_mmc_cfg &= ~CFG_RC_CC_MASK; + meson_mmc_cfg |= CFG_RC_CC_16; + + meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG); + + return 0; +} + +static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data, + struct mmc_cmd *cmd) +{ + uint32_t meson_mmc_cmd = 0, cfg; + + meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) + meson_mmc_cmd |= CMD_CFG_RESP_128; + + if (cmd->resp_type & MMC_RSP_BUSY) + meson_mmc_cmd |= CMD_CFG_R1B; + + if (!(cmd->resp_type & MMC_RSP_CRC)) + meson_mmc_cmd |= CMD_CFG_RESP_NOCRC; + } else { + meson_mmc_cmd |= CMD_CFG_NO_RESP; + } + + if (data) { + cfg = meson_read(mmc, MESON_SD_EMMC_CFG); + cfg &= ~CFG_BL_LEN_MASK; + cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT; + meson_write(mmc, cfg, MESON_SD_EMMC_CFG); + + if (data->flags == MMC_DATA_WRITE) + meson_mmc_cmd |= CMD_CFG_DATA_WR; + + cfg = CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE | data->blocks; + meson_mmc_cmd |= cfg; + } + + cfg = CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER | CMD_CFG_END_OF_CHAIN; + meson_mmc_cmd |= cfg; + + meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG); +} + +static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data) +{ + struct meson_mmc_platdata *pdata = mmc->priv; + unsigned int data_size; + uint32_t data_addr = 0; + + if (data) { + data_size = data->blocks * data->blocksize; + + if (data->flags == MMC_DATA_READ) { + data_addr = (ulong) data->dest; + invalidate_dcache_range(data_addr, + data_addr + data_size); + } else if (data->flags == MMC_DATA_WRITE) { + pdata->w_buf = calloc(data_size, sizeof(char)); + data_addr = (ulong) pdata->w_buf; + memcpy(pdata->w_buf, data->src, data_size); + flush_dcache_range(data_addr, data_addr + data_size); + } + } + + meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT); +} + +static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd) +{ + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3); + cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2); + cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1); + cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP); + } else { + cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP); + } +} + +static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + struct meson_mmc_platdata *pdata = mmc->priv; + uint32_t status; + ulong start; + int ret = 0; + + /* max block size supported by chip is 512 byte */ + if (data && data->blocksize > 512) + return -EINVAL; + + meson_mmc_setup_cmd(mmc, data, cmd); + meson_mmc_setup_addr(mmc, data); + + meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG); + + /* use 10s timeout */ + start = get_timer(0); + do { + status = meson_read(mmc, MESON_SD_EMMC_STATUS); + } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000); + + if (!(status & STATUS_END_OF_CHAIN)) + ret = -ETIMEDOUT; + else if (status & STATUS_RESP_TIMEOUT) + ret = -ETIMEDOUT; + else if (status & STATUS_ERR_MASK) + ret = -EIO; + + meson_mmc_read_response(mmc, cmd); + + if (data && data->flags == MMC_DATA_WRITE) + free(pdata->w_buf); + + /* reset status bits */ + meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); + + return ret; +} + +static const struct dm_mmc_ops meson_dm_mmc_ops = { + .send_cmd = meson_dm_mmc_send_cmd, + .set_ios = meson_dm_mmc_set_ios, +}; + +static int meson_mmc_ofdata_to_platdata(struct udevice *dev) +{ + struct meson_mmc_platdata *pdata = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + pdata->regbase = (void *)addr; + + return 0; +} + +static int meson_mmc_probe(struct udevice *dev) +{ + struct meson_mmc_platdata *pdata = dev_get_platdata(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = &pdata->mmc; + struct mmc_config *cfg = &pdata->cfg; + uint32_t val; + + cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 | + MMC_VDD_31_32 | MMC_VDD_165_195; + cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | + MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); + cfg->f_max = 100000000; /* 100 MHz */ + cfg->b_max = 256; /* max 256 blocks */ + cfg->name = dev->name; + + mmc->priv = pdata; + upriv->mmc = mmc; + + mmc_set_clock(mmc, cfg->f_min); + + /* reset all status bits */ + meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); + + /* disable interrupts */ + meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN); + + /* enable auto clock mode */ + val = meson_read(mmc, MESON_SD_EMMC_CFG); + val &= ~CFG_SDCLK_ALWAYS_ON; + val |= CFG_AUTO_CLK; + meson_write(mmc, val, MESON_SD_EMMC_CFG); + + return 0; +} + +int meson_mmc_bind(struct udevice *dev) +{ + struct meson_mmc_platdata *pdata = dev_get_platdata(dev); + + return mmc_bind(dev, &pdata->mmc, &pdata->cfg); +} + +static const struct udevice_id meson_mmc_match[] = { + { .compatible = "amlogic,meson-gx-mmc" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(meson_mmc) = { + .name = "meson_gx_mmc", + .id = UCLASS_MMC, + .of_match = meson_mmc_match, + .ops = &meson_dm_mmc_ops, + .probe = meson_mmc_probe, + .bind = meson_mmc_bind, + .ofdata_to_platdata = meson_mmc_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata), +}; diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index 17e81b4..b6dfbcd 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -23,6 +23,10 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x20000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_MMC +#define CONFIG_GENERIC_MMC +#endif + /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xc4301000 #define GICC_BASE 0xc4302000 -- 2.11.0

2 2

[U-Boot] [PATCH 1/2] lib: Add WATCHDOG_RESET to wait_bit.h
by Michal Simek 02 Feb '17

02 Feb '17

wait_for_bit() is missing reset watchdog in case watchdog is configured. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/wait_bit.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/wait_bit.h b/include/wait_bit.h index 066e30c118af..06ad43a122d6 100644 --- a/include/wait_bit.h +++ b/include/wait_bit.h @@ -11,6 +11,7 @@ #include <common.h> #include <console.h> +#include <watchdog.h> #include <linux/errno.h> #include <asm/io.h> @@ -59,6 +60,7 @@ static inline int wait_for_bit(const char *prefix, const u32 *reg, } udelay(1); + WATCHDOG_RESET(); } debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg, mask, -- 1.9.1

3 3

[U-Boot] [PATCH 0/7] Add STMicroelectronics STiH410-B2260 board support
by patrice.chotard＠st.com 02 Feb '17

02 Feb '17

From: Patrice Chotard <patrice.chotard(a)st.com> This boards is a 96boards based on STiH410 SoC. This series adds basic support with serial, mmc and pinctrl support. Patrice Chotard (7): arm: Add support for STMicroelectronics STiH410 soc board: Add STMicroelectronics STiH410-B2260 support STiH410: Add STi serial driver STiH410: Add STi SDHCI driver STiH410: add STi pinctrl driver STiH410-B2260: add device tree STIH410-B2260: Add STiH410-B2260 defconfig arch/arm/Kconfig | 13 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 3 + arch/arm/dts/st-pincfg.h | 71 ++ arch/arm/dts/stih407-clock.dtsi | 326 ++++++ arch/arm/dts/stih407-family.dtsi | 977 +++++++++++++++ arch/arm/dts/stih407-pinctrl.dtsi | 1303 +++++++++++++++++++++ arch/arm/dts/stih410-b2260.dts | 225 ++++ arch/arm/dts/stih410-clock.dtsi | 347 ++++++ arch/arm/dts/stih410-pinctrl.dtsi | 34 + arch/arm/dts/stih410.dtsi | 454 +++++++ arch/arm/include/asm/arch-stih410/gpio.h | 20 + arch/arm/include/asm/arch-stih410/sdhci.h | 69 ++ arch/arm/include/asm/arch-stih410/sti.h | 25 + arch/arm/include/asm/arch-stih410/syscfg.h | 87 ++ arch/arm/mach-sti/Kconfig | 31 + arch/arm/mach-sti/Makefile | 8 + arch/arm/mach-sti/cpu.c | 16 + arch/arm/mach-sti/timer.c | 47 + board/st/stih410-b2260/Kconfig | 19 + board/st/stih410-b2260/MAINTAINERS | 6 + board/st/stih410-b2260/Makefile | 8 + board/st/stih410-b2260/board.c | 44 + configs/stih410-b2260_defconfig | 22 + drivers/mmc/Kconfig | 7 + drivers/mmc/Makefile | 1 + drivers/mmc/sti_sdhci.c | 137 +++ drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-sti.c | 311 +++++ drivers/serial/Kconfig | 7 + drivers/serial/Makefile | 1 + drivers/serial/serial_sti_asc.c | 219 ++++ include/configs/stih410-b2260.h | 61 + include/dm/platform_data/serial_sti_asc.h | 17 + include/dm/platform_data/sti_sdhci.h | 17 + include/dt-bindings/clock/stih407-clks.h | 90 ++ include/dt-bindings/clock/stih410-clks.h | 25 + include/dt-bindings/interrupt-controller/irq-st.h | 30 + include/dt-bindings/mfd/st-lpc.h | 16 + include/dt-bindings/reset/stih407-resets.h | 65 + 41 files changed, 5171 insertions(+) create mode 100644 arch/arm/dts/st-pincfg.h create mode 100644 arch/arm/dts/stih407-clock.dtsi create mode 100644 arch/arm/dts/stih407-family.dtsi create mode 100644 arch/arm/dts/stih407-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410-b2260.dts create mode 100644 arch/arm/dts/stih410-clock.dtsi create mode 100644 arch/arm/dts/stih410-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410.dtsi create mode 100644 arch/arm/include/asm/arch-stih410/gpio.h create mode 100644 arch/arm/include/asm/arch-stih410/sdhci.h create mode 100644 arch/arm/include/asm/arch-stih410/sti.h create mode 100644 arch/arm/include/asm/arch-stih410/syscfg.h create mode 100644 arch/arm/mach-sti/Kconfig create mode 100644 arch/arm/mach-sti/Makefile create mode 100644 arch/arm/mach-sti/cpu.c create mode 100644 arch/arm/mach-sti/timer.c create mode 100644 board/st/stih410-b2260/Kconfig create mode 100644 board/st/stih410-b2260/MAINTAINERS create mode 100644 board/st/stih410-b2260/Makefile create mode 100644 board/st/stih410-b2260/board.c create mode 100644 configs/stih410-b2260_defconfig create mode 100644 drivers/mmc/sti_sdhci.c create mode 100644 drivers/pinctrl/pinctrl-sti.c create mode 100644 drivers/serial/serial_sti_asc.c create mode 100644 include/configs/stih410-b2260.h create mode 100644 include/dm/platform_data/serial_sti_asc.h create mode 100644 include/dm/platform_data/sti_sdhci.h create mode 100644 include/dt-bindings/clock/stih407-clks.h create mode 100644 include/dt-bindings/clock/stih410-clks.h create mode 100644 include/dt-bindings/interrupt-controller/irq-st.h create mode 100644 include/dt-bindings/mfd/st-lpc.h create mode 100644 include/dt-bindings/reset/stih407-resets.h -- 1.9.1

4 12

[U-Boot] [UBOOT v2 00/15] Add support for SD3.0 and eMMC HS200
by Siva Durga Prasad Paladugu 02 Feb '17

02 Feb '17

This patch series adds support SD3.0 and eMMC HS200 modes for ZynqMP. This series also contains changes in mmc and sdhci framework to support SD3.0 and HS200. Siva Durga Prasad Paladugu (15): mmc: sdhci: Update host capabilities about host controller mmc: Add support for SD3.0 mmc: sdhci: Add SD3.0 support mmc: sdhci: Add support for platform/board specific tuning mmc: sdhci: Add support for platform specific delay mmc: sdhci: Make sdhci_ops of host as modifiable zynqmp: Define routines for mmio write and read mmc: sdhci: zynq: Define private structure arasan_sdhci_priv mmc: sdhci: zynqmp: Add support of SD3.0 mmc: sdhci: Add quirk for 1.8v switching not supported mmc: zynq_sdhci: Update quirk if 1.8v switching not supported mmc: sdhci: Add support for eMMC HS200 mode mmc: sdhci: Update execute tuning and set clock for HS200 mmc: sdhci: zynqmp: Set tapdelays for eMMC HS200 mode mmc: Change frequency while accessing to boot partition arch/arm/cpu/armv8/zynqmp/cpu.c | 51 ++++++ arch/arm/include/asm/arch-zynqmp/sys_proto.h | 3 + board/xilinx/zynqmp/Makefile | 1 + board/xilinx/zynqmp/tap_delays.c | 250 +++++++++++++++++++++++++++ drivers/mmc/mmc-uclass.c | 52 ++++++ drivers/mmc/mmc.c | 218 +++++++++++++++++++++-- drivers/mmc/sdhci.c | 205 +++++++++++++++++++++- drivers/mmc/zynq_sdhci.c | 170 +++++++++++++++++- include/mmc.h | 74 +++++++- include/sdhci.h | 18 +- include/zynqmp_tap_delay.h | 20 +++ 11 files changed, 1040 insertions(+), 22 deletions(-) create mode 100644 board/xilinx/zynqmp/tap_delays.c create mode 100644 include/zynqmp_tap_delay.h -- 2.7.4

2 16

[U-Boot] [PATCH v4 0/3] Add a config for AM335x High Security EVM
by Andrew F. Davis 02 Feb '17

02 Feb '17

Hello all, This series is [0] and [1] together due to a dependency. Both are modified as suggested in the comments. Thanks, Andrew [0]: https://patchwork.ozlabs.org/patch/713945/ [1]: https://patchwork.ozlabs.org/patch/715820/ Changes from v3: - Reworked v2 as per Tom's comments Andrew F. Davis (3): malloc_simple: Add debug statements to memalign_simple spl: Remove overwrite of relocated malloc limit defconfig: Add a config for AM335x High Security EVM MAINTAINERS | 1 + common/malloc_simple.c | 6 +++- common/spl/spl.c | 7 ++++- configs/am335x_hs_evm_defconfig | 62 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 74 insertions(+), 2 deletions(-) create mode 100644 configs/am335x_hs_evm_defconfig -- 2.11.0

5 13

[U-Boot] [PATCH 1/5][v7] arch: powerpc: Move CONFIG_FSL_IFC to Kconfig
by Prabhakar Kushwaha 02 Feb '17

02 Feb '17

Enable IFC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v5: Added first time Changes for v6: Sending as it is Changes for v7: Sending as it is arch/powerpc/cpu/mpc85xx/Kconfig | 17 +++++++++++++++++ include/configs/B4860QDS.h | 1 - include/configs/BSC9131RDB.h | 1 - include/configs/BSC9132QDS.h | 1 - include/configs/C29XPCIE.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/T102xQDS.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T1040QDS.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/t4qds.h | 1 - 14 files changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 38ea4c1..a3db014 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -374,6 +374,7 @@ config ARCH_B4420 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_B4860 bool @@ -398,6 +399,7 @@ config ARCH_B4860 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_BSC9131 bool @@ -410,6 +412,7 @@ config ARCH_BSC9131 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select FSL_IFC config ARCH_BSC9132 bool @@ -426,6 +429,7 @@ config ARCH_BSC9132 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_IFC config ARCH_C29X bool @@ -438,6 +442,7 @@ config ARCH_C29X select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_6 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_IFC config ARCH_MPC8536 bool @@ -553,6 +558,7 @@ config ARCH_P1010 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_IFC config ARCH_P1011 bool @@ -795,6 +801,7 @@ config ARCH_T1023 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T1024 bool @@ -811,6 +818,7 @@ config ARCH_T1024 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T1040 bool @@ -828,6 +836,7 @@ config ARCH_T1040 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T1042 bool @@ -845,6 +854,7 @@ config ARCH_T1042 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T2080 bool @@ -866,6 +876,7 @@ config ARCH_T2080 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_T2081 bool @@ -885,6 +896,7 @@ config ARCH_T2081 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_T4160 bool @@ -905,6 +917,7 @@ config ARCH_T4160 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_T4240 bool @@ -928,6 +941,7 @@ config ARCH_T4240 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config BOOKE bool @@ -1260,6 +1274,9 @@ config SYS_PPC64 config SYS_PPC_E500_USE_DEBUG_TLB bool +config FSL_IFC + bool + config SYS_PPC_E500_DEBUG_TLB int "Temporary TLB entry for external debugger" depends on SYS_PPC_E500_USE_DEBUG_TLB diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index fc99b96..2fdb869 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -63,7 +63,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 77f0927..4116234 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -46,7 +46,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_TSEC_ENET diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index f336f28..b2c8b03 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index e1ce7ad..8f68748 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 1d01e7f..3594e56 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -130,7 +130,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 2c3b660..0319f18 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 79c34ef..459435f 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 15a29cb..9de6185 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 45aaf90..b778ace 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -162,7 +162,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 606c928..d6f647a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -33,7 +33,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 825bf25..53bd684 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index be18f66..2b03801 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -73,7 +73,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 15c0e89..7803a84 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -- 2.7.4

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[U-Boot] [GIT PULL] Please pull u-boot-mmc master
by Jaehoon Chung 01 Feb '17

01 Feb '17

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