January 2017 - U-Boot

[U-Boot] [PATCH v2 0/7] arm64: mvebu: Add support for A8K community board
by kostap＠marvell.com 06 Feb '17

06 Feb '17

From: Konstantin Porotchkin <kostap(a)marvell.com> This patch series adds initil support for A8K community board MACCHIATOBin manufactured by SolidRun. It should be applied on top of Stefan Roese patches adding support for SD/eMMC devices on Marvell A37x0/A80x0/A70x0 SoCs. The top level patch is called: "arm64: mvebu: Enable SDHCI/MMC support for the db-88f7040/8040" The default board DTS file is based on the original work of Rabeeh Khory from SolidRun. Changes for v2: - Move PCIe reset GPIO support from board-specific function to mvebu PCIe driver - Move VBUS GPIO support from board-specific function to mvebu XHCI driver - Allow MMC support for "bubt" command with and without CONFIG_BLK Konstantin Porotchkin (6): arm64: mvebu: Update bubt command MMC block device access arm64: mvebu: gpio: Add GPIO nodes to A8K family devices arm64: mvebu: dts: Add i2c1 pin definitions to CPM mvebu: usb: xhci: Add support for VBUS controlled by GPIO mvebu: pcie: Add support for GPIO reset for PCIe device arm64: mvebu: Add default configuraton for MACCHIATOBin board Rabeeh Khoury (1): arm64: mvebu: dts: Add DTS file for MACCHIATOBin board arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-7040.dtsi | 1 + arch/arm/dts/armada-8040-mcbin.dts | 253 ++++++++++++++++++++++ arch/arm/dts/armada-8040.dtsi | 1 + arch/arm/dts/armada-ap806.dtsi | 8 + arch/arm/dts/armada-cp110-master.dtsi | 22 ++ arch/arm/dts/armada-cp110-slave.dtsi | 18 ++ cmd/mvebu/bubt.c | 25 ++- configs/mvebu_mcbin-88f8040_defconfig | 65 ++++++ doc/device-tree-bindings/pci/armada8k-pcie.txt | 49 +++++ doc/device-tree-bindings/usb/marvell.xhci-usb.txt | 29 +++ drivers/pci/pcie_dw_mvebu.c | 20 ++ drivers/usb/host/xhci-mvebu.c | 14 ++ 13 files changed, 503 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/armada-8040-mcbin.dts create mode 100644 configs/mvebu_mcbin-88f8040_defconfig create mode 100644 doc/device-tree-bindings/pci/armada8k-pcie.txt create mode 100644 doc/device-tree-bindings/usb/marvell.xhci-usb.txt -- 2.7.4

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[U-Boot] [PATCH 1/2][v4] board: freescale: ls1012a: Enable secure DDR on LS1012A platforms
by Prabhakar Kushwaha 06 Feb '17

06 Feb '17

PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Sending as it is Changes for v3: Rebased top of the tree Changes for v4: incorporated York's comments arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ board/freescale/ls1012afrdm/ls1012afrdm.c | 29 +++++++++++++++++++++++ board/freescale/ls1012aqds/ls1012aqds.c | 29 +++++++++++++++++++++++ board/freescale/ls1012ardb/ls1012ardb.c | 29 +++++++++++++++++++++++ include/configs/ls1012a_common.h | 1 + 5 files changed, 91 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 8c426af..83f5501 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -192,6 +192,9 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + #elif defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index b03bdb8..c2432c3 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -85,3 +85,32 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +void dram_init_banksize(void) +{ + /* + * gd->arch.secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } +} diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 88fb4ce..bdd9529 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif + +void dram_init_banksize(void) +{ + /* + * gd->arch.secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } +} diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 65fa94c..2dece02 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +void dram_init_banksize(void) +{ + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } +} diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 81f8d62..0965afa 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -29,6 +29,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL /* Generic Timer Definitions */ #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */ -- 2.7.4

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[U-Boot] [PATCH] armv8: ls1046a: Enable workaround for erratum A-008336
by York Sun 06 Feb '17

06 Feb '17

Erratum A-008336 applies to LS1046A per latest SoC document. Signed-off-by: York Sun <york.sun(a)nxp.com> CC: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ba411e2..2caeee7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -30,6 +30,7 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 -- 2.7.4

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[U-Boot] [PATCH] armv7: ls1021aqds: Set cpo_sample for erratum A-009942
by York Sun 06 Feb '17

06 Feb '17

Set cpo_sample as suggested by the driver "WARN: pls set popts->cpo_sample = 0x58 in <board>/ddr.c to optimize cpo". Signed-off-by: York Sun <york.sun(a)nxp.com> CC: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- board/freescale/ls1021aqds/ddr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 6435bf9..2f66ba9 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -96,6 +96,9 @@ found: #else popts->cswl_override = DDR_CSWL_CS0; + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x58; + /* DHC_EN =1, ODT = 75 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -- 2.7.4

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[U-Boot] [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in DPC
by Bogdan Purcareata 06 Feb '17

06 Feb '17

Fixup port_mac_address property in MC DPC with values from the u-boot environment. Since u-boot already reads the environment MAC addresses when probing the PHYs, use these values. The u-boot environment MAC addresses take precedence over any eventual ones defined in the DPC, except for the case where they are randomly assigned (no u-boot env value declared for port). The patch assumes the "/board_info/ports/" node is present in the DPC. Signed-off-by: Bogdan Purcareata <bogdan.purcareata(a)nxp.com> --- drivers/net/fsl-mc/mc.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 101 insertions(+), 2 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 2a2d3e5..cca579a 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -7,6 +7,7 @@ #include <errno.h> #include <asm/io.h> #include <libfdt.h> +#include <net.h> #include <fdt_support.h> #include <fsl-mc/fsl_mc.h> #include <fsl-mc/fsl_mc_sys.h> @@ -197,10 +198,81 @@ static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr, return 0; } +static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id, + struct eth_device *eth_dev) +{ + int nodeoffset, err = 0; + char mac_name[10]; + const char link_type_mode[] = "FIXED_LINK"; + unsigned char env_enetaddr[6]; + + sprintf(mac_name, "mac@%d", dpmac_id); + + /* node not found - create it */ + nodeoffset = fdt_subnode_offset(blob, noff, (const char *) mac_name); + if (nodeoffset < 0) { + err = fdt_increase_size(blob, 200); + if (err) { + printf("fdt_increase_size: err=%s\n", + fdt_strerror(err)); + return err; + } + + nodeoffset = fdt_add_subnode(blob, noff, mac_name); + + /* add default property of fixed link */ + err = fdt_appendprop_string(blob, nodeoffset, + "link_type", link_type_mode); + if (err) { + printf("fdt_appendprop_string: err=%s\n", + fdt_strerror(err)); + return err; + } + } + + /* port_mac_address property present in DPC */ + if (fdt_get_property(blob, nodeoffset, "port_mac_address", NULL)) { + /* MAC addr randomly assigned - leave the one in DPC */ + eth_getenv_enetaddr_by_index("eth", eth_dev->index, + env_enetaddr); + if (is_zero_ethaddr(env_enetaddr)) + return err; + + /* replace DPC MAC address with u-boot env one */ + err = fdt_setprop(blob, nodeoffset, "port_mac_address", + eth_dev->enetaddr, 6); + if (err) { + printf("fdt_setprop mac: err=%s\n", fdt_strerror(err)); + return err; + } + + return 0; + } + + /* append port_mac_address property to mac node in DPC */ + err = fdt_increase_size(blob, 80); + if (err) { + printf("fdt_increase_size: err=%s\n", fdt_strerror(err)); + return err; + } + + err = fdt_appendprop(blob, nodeoffset, + "port_mac_address", eth_dev->enetaddr, 6); + if (err) { + printf("fdt_appendprop: err=%s\n", fdt_strerror(err)); + return err; + } + + return err; +} + static int mc_fixup_dpc(u64 dpc_addr) { void *blob = (void *)dpc_addr; - int nodeoffset; + int nodeoffset, err = 0; + char ethname[10]; + struct eth_device *eth_dev; + int i; /* delete any existing ICID pools */ nodeoffset = fdt_path_offset(blob, "/resources/icid_pools"); @@ -222,9 +294,36 @@ static int mc_fixup_dpc(u64 dpc_addr) FSL_DPAA2_STREAM_ID_END - FSL_DPAA2_STREAM_ID_START + 1, 1); + /* fixup MAC addresses for dpmac ports */ + nodeoffset = fdt_path_offset(blob, "/board_info/ports"); + if (nodeoffset < 0) + goto out; + + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { + /* port not enabled */ + if ((wriop_is_enabled_dpmac(i) != 1) || + (wriop_get_phy_address(i) == -1)) + continue; + + sprintf(ethname, "DPMAC%d@%s", i, + phy_interface_strings[wriop_get_enet_if(i)]); + + eth_dev = eth_get_dev_by_name(ethname); + if (eth_dev == NULL) + continue; + + err = mc_fixup_dpc_mac_addr(blob, nodeoffset, i, eth_dev); + if (err) { + printf("mc_fixup_dpc_mac_addr failed: err=%s\n", + fdt_strerror(err)); + goto out; + } + } + +out: flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob)); - return 0; + return err; } static int load_mc_dpc(u64 mc_ram_aligned_base_addr, size_t mc_ram_size, -- 1.9.1

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[U-Boot] [PATCH 1/2] armv8: ls1046a: added usb nodes in dts
by yuantian.tang＠nxp.com 06 Feb '17

06 Feb '17

From: Tang Yuantian <Yuantian.Tang(a)nxp.com> The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang(a)nxp.com> --- arch/arm/dts/fsl-ls1046a.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index aaf0ae9..408e81e 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -217,6 +217,27 @@ status = "disabled"; }; + usb0: usb@2f00000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 4>; + dr_mode = "host"; + }; + + usb1: usb@3000000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <0 61 4>; + dr_mode = "host"; + }; + + usb2: usb@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 63 4>; + dr_mode = "host"; + }; + pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] armv8: ls1046aqds: added usb feature support
by yuantian.tang＠nxp.com 06 Feb '17

06 Feb '17

From: Tang Yuantian <Yuantian.Tang(a)nxp.com> The LS1046AQDS processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang(a)nxp.com> --- v2: - fix compiling warning. include/configs/ls1046aqds.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 3618a06..b995cd2 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -135,6 +135,18 @@ unsigned long get_board_ddr_clk(void); #define CFG_LPUART_EN 0x2 #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_HCD +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/3] arc: introduce timer driver and update device tree
by Vlad Zakharov 06 Feb '17

06 Feb '17

ARC cores may have up to 2 built-in timers: timer0 and timer1, usually at least one of them exists. They both are driven by the same core clock. They are controlled through auxiliary registers and so we don't have to remap their control registers as we used to do with MMIO registers of external peripheral devices. This patch series replaces legacy approach to access ARC timer via specific code in "arch/arc/lib/time.c" and uses timer driver instead. We want to have common device tree blobs for both Linux and U-Boot. To achieve this the patch updates arc device trees with the following: 1. Separate axs10x.dts device tree in order to reflect the real structure of AXS101 and AXS103 development boards. 2. Add timer device to skeleton ARC device tree. 3. Add core_clk devices to all ARC boards as it is referenced from timer device. Vlad Zakharov (3): drivers: timer: Introduce ARC timer driver arc: dts: separate single axs10x.dts file arc: use timer driver for ARC boards arch/Kconfig | 3 + arch/arc/Kconfig | 9 ++- arch/arc/dts/Makefile | 3 +- arch/arc/dts/abilis_tb100.dts | 12 +++- arch/arc/dts/axc001.dtsi | 19 +++++ arch/arc/dts/axc003.dtsi | 19 +++++ arch/arc/dts/axs101.dts | 19 +++++ arch/arc/dts/axs103.dts | 19 +++++ arch/arc/dts/axs10x.dts | 57 --------------- arch/arc/dts/axs10x_mb.dtsi | 66 +++++++++++++++++ arch/arc/dts/nsim.dts | 12 +++- arch/arc/dts/skeleton.dtsi | 19 ++++- arch/arc/include/asm/arcregs.h | 4 ++ board/synopsys/axs10x/Kconfig | 2 +- configs/axs101_defconfig | 4 +- configs/axs103_defconfig | 3 +- doc/device-tree-bindings/timer/arc_timer.txt | 24 +++++++ drivers/timer/Kconfig | 9 +++ drivers/timer/Makefile | 1 + drivers/timer/arc_timer.c | 103 +++++++++++++++++++++++++++ include/configs/axs10x.h | 2 - include/configs/nsim.h | 5 -- include/configs/tb100.h | 5 -- 23 files changed, 334 insertions(+), 85 deletions(-) create mode 100644 arch/arc/dts/axc001.dtsi create mode 100644 arch/arc/dts/axc003.dtsi create mode 100644 arch/arc/dts/axs101.dts create mode 100644 arch/arc/dts/axs103.dts delete mode 100644 arch/arc/dts/axs10x.dts create mode 100644 arch/arc/dts/axs10x_mb.dtsi create mode 100644 doc/device-tree-bindings/timer/arc_timer.txt create mode 100644 drivers/timer/arc_timer.c -- 2.7.4

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[U-Boot] [RFC PATCH 00/11] extend FIT loading support (plus Pine64/ATF support)
by Andre Przywara 06 Feb '17

06 Feb '17

Currently the FIT format is not used to its full potential in the SPL: It only loads the first image from the /images node and appends the proper FDT. Some boards and platforms would benefit from loading more images before starting U-Boot proper, notably Allwinner A64 and ARMv8 Rockchip boards, which use an ARM Trusted Firmware (ATF) image to be executed before U-Boot. This series tries to solve this in a board agnostic and generic way: We extend the SPL FIT loading scheme to allow loading multiple images. So apart from loading the image which is referenced by the "firmware" property in the respective configuration node and placing the DTB right behind it, we iterate over all strings in the "loadable" property. Each image referenced there will be loaded to its specified load address. The entry point U-Boot eventually branches to will be taken from the first image to explicitly provide the "entry" property, or, if none of them does so, from the load address of the "firmware" image. This keeps the scheme compatible with the FIT images our Makefile creates automatically at the moment. Apart from the already mentioned ATF scenario this opens up more usage scenarios, of which the commit message of patch 04/11 lists some. The first three patches rework the SPL FIT support to be more flexible and to allow easier usage in the fourth patch, which introduces the multiple-image loading facility. The remaining patches enable that support for the Pine64 board to make its SPL support finally useful and to demonstrate usage of this scheme: patches 5-7 extend the usable SPL size by about 4 KB to allow AArch64 compilation of the SPL with FIT support enabled. Patch 8 implements the board selector routine, which selects either the Pine64 or Pine64+ DTB depending on the detected DRAM size. Patch 9 enables SPL FIT support in the Pine64 defconfig. To demonstrate the usage, patch 10 provides a FIT source file, which loads and executes ATF before the U-Boot proper. Users are expected to compile this with "mkimage -f boards/sunxi/pine64_atf.its -E pine64.itb", then write the resulting file behind the SPL on an SD card (or any other U-Boot supported boot media, for that matter). Patch 11 then adds FIT support to the sunxi SPL SPI loading routine, which allows to load ATF on boards with SPI flash as well. Questions: 1) Is this scheme the right one (usage of "firmware" and "loadables", determination of entry point)? Shall we make use of the "setup" property? 2) Shall we extend mkimage to allow supplying "loadable" files on the command line, which would allow to build the .itb file automatically? 3) Is providing the .its source file for a (family of) boards the right way? 4) Does this break any boards which already use SPL FIT loading? And for the Pine64 part: 5) Is extending the usable SPL size like in patch 5-7 acceptable? I have a more generic solution for the .dtb selection in mind: Based on some patch from Siarhei we store the .dtb filename in the SPL header and select the .dtb from the FIT image by simply matching the name. This would allow _one_ build supporting multiple boards. The actual board name would need to written into the SPL header or could be copied from there when updating the image. I can provide the patches once we agreed upon this series. Please let me know what you think! Cheers, Andre. Andre Przywara (11): SPL: FIT: refactor FDT loading SPL: FIT: rework U-Boot image loading SPL: FIT: factor out spl_load_fit_image() SPL: FIT: allow loading multiple images tools: mksunxiboot: allow larger SPL binaries sunxi: A64: SPL: allow large SPL binary sunxi: A64: move SPL stack to end of SRAM A2 sunxi: SPL: add FIT config selector for Pine64 boards sunxi: Pine64: defconfig: enable SPL FIT support sunxi: Pine64: add FIT image source SPL: SPI: sunxi: add SPL FIT image support board/sunxi/board.c | 13 +++ board/sunxi/pine64_atf.its | 54 +++++++++ common/spl/spl_fit.c | 241 +++++++++++++++++++++++----------------- configs/pine64_plus_defconfig | 5 + drivers/mtd/spi/sunxi_spi_spl.c | 39 +++++-- include/configs/sunxi-common.h | 6 +- scripts/Makefile.spl | 7 +- tools/mksunxiboot.c | 51 ++++++--- 8 files changed, 290 insertions(+), 126 deletions(-) create mode 100644 board/sunxi/pine64_atf.its -- 2.8.2

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[U-Boot] [RFC PATCH v3 00/11] IPv6 support
by Chris Packham 06 Feb '17

06 Feb '17

This series adds basic IPv6 support to U-boot. It is a reboot of my earlier work on this[1]. This latest version is itself a reboot of work that was last posted to the list in late 2015. Right now I've just rebased against master so functionally it is little different to what was last posted. Most of this is ported from Allied Telesis' additions to u-boot[2]. (Note that I am employed by Allied Telesis[3]). The hard work was done some time ago by Angga, I've cleaned it up and made some improvements with the hope of getting it accepted upstream. A few open issues 1) rxhand_f currently takes an struct in_addr. TFTP doesn't use this (I haven't looked at other users). To support V6 this may need to be a new union, a void * with some kind of flag or nothing if no rxhandler actually cares. It has been suggested that this parameter be removed and any users that care can re-parse the packet. 2) Unit tests. This code needs them. The testing so-far has been ad-hoc manual testing using qemu-x86. 3) Fancy v6 feature xyz. There are a lot of things that _could_ be implemented on top of this (DHCPV6 and SLAAC are two obvious things that stick out). For now I want to concentrate on getting the core code stable and accepted, if anyone else wants to work on either of those features that'd be great. -- [1] - http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/151390 [2] - http://www.alliedtelesis.co.nz/support/gpl/other.html [3] - some of this has been done on work time, other parts have been done in my personal time. Since I'm subscribed to the list using my gmail account I've signed using that. Changes in v3: - Add brief testing section Changes in v2: - Split environment variables from main implementation - remove "prefixlength6" environment variable. The prefix length is now set when specifying the address i.e. setenv ip6addr 2001:db8::1/64. - split ping6 support into separate patch - split environment variables into separate patch - change ip6_ndisc_* to ndisc_*, fix CamelCase - split ping6 support into it's own patch - Support parsing the server address from the command parameter. Chris Packham (11): Initial net6.h lib: vsprintf: add IPv6 compressed format %pI6c lib: net_utils: add string_to_ip6 net: add definition of udp_hdr net: IPv6 skeleton and environment variables net: IPv6 support net: Add ping6 command and implementation net: TFTP over IPv6 net: IPv6 documentation net: e1000 enable multicast reception net: tsec: enable promiscuous mode README | 3 + cmd/Kconfig | 15 ++ cmd/net.c | 41 +++++ doc/README.ipv6 | 55 ++++++ drivers/net/e1000.c | 5 + drivers/net/tsec.c | 4 + include/env_callback.h | 8 + include/env_flags.h | 9 + include/net.h | 18 +- include/net6.h | 262 ++++++++++++++++++++++++++++ lib/net_utils.c | 121 +++++++++++++ lib/vsprintf.c | 154 ++++++++++++++--- net/Kconfig | 6 +- net/Makefile | 3 + net/ndisc.c | 266 ++++++++++++++++++++++++++++ net/ndisc.h | 25 +++ net/net.c | 40 ++++- net/net6.c | 459 +++++++++++++++++++++++++++++++++++++++++++++++++ net/ping6.c | 111 ++++++++++++ net/tftp.c | 58 +++++++ 20 files changed, 1635 insertions(+), 28 deletions(-) create mode 100644 doc/README.ipv6 create mode 100644 include/net6.h create mode 100644 net/ndisc.c create mode 100644 net/ndisc.h create mode 100644 net/net6.c create mode 100644 net/ping6.c -- 2.11.0.24.ge6920cf

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