August 2016 - U-Boot

[U-Boot] [PATCH 1/3] mmc: dw_mmc: remove the duplicated header file
by Jaehoon Chung 05 Aug '16

05 Aug '16

<asm-generic/errno.h> is already included in <errno.h>. It can use <errno.h> instead of <asm-generic/errno.h> Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/dw_mmc.c | 1 - drivers/mmc/exynos_dw_mmc.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 2cf7bae..8687368 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -13,7 +13,6 @@ #include <memalign.h> #include <mmc.h> #include <dwmmc.h> -#include <asm-generic/errno.h> #define PAGE_SIZE 4096 diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 283befc..57271f1 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -10,12 +10,12 @@ #include <fdtdec.h> #include <libfdt.h> #include <malloc.h> +#include <errno.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clk.h> #include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/gpio.h> -#include <asm-generic/errno.h> #define DWMMC_MAX_CH_NUM 4 #define DWMMC_MAX_FREQ 52000000 -- 1.9.1

3 9

[U-Boot] [PATCH 1/2] mmc: sdhci: set to INT_DATA_END when there are data
by Jaehoon Chung 05 Aug '16

05 Aug '16

There is no data, it doesn't needs to wait for completing data transfer. (It seems that it can be removed.) Almost all timeout error is occured from stop command without data. After applied this patch, I hope that we don't need to increase timeout value anymore. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 604f18d..0a38a56 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -175,7 +175,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, flags = SDHCI_CMD_RESP_LONG; else if (cmd->resp_type & MMC_RSP_BUSY) { flags = SDHCI_CMD_RESP_SHORT_BUSY; - mask |= SDHCI_INT_DATA_END; + if (data) + mask |= SDHCI_INT_DATA_END; } else flags = SDHCI_CMD_RESP_SHORT; -- 1.9.1

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[U-Boot] [PATCH v2] mmc: sdhci: clean up timeout detection
by Masahiro Yamada 05 Aug '16

05 Aug '16

The current timeout detection logic is not very nice; it calls get_timer(start) in the while() loop, and then calls it again after the loop to check if a timeout error happened. Because of the time difference between the two calls of get_timer(), the timeout detected after the loop may not be true. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> Acked-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- Changes in v2: - Fix a typo : get_time() -> get_timer() in git-log drivers/mmc/sdhci.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 604f18d..0a1882d 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -243,17 +243,17 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) break; - } while (((stat & mask) != mask) && - (get_timer(start) < SDHCI_READ_STATUS_TIMEOUT)); - if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { - if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) - return 0; - else { - printf("%s: Timeout for status update!\n", __func__); - return TIMEOUT; + if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { + if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { + return 0; + } else { + printf("%s: Timeout for status update!\n", + __func__); + return TIMEOUT; + } } - } + } while ((stat & mask) != mask); if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { sdhci_cmd_done(host, cmd); -- 1.9.1

2 1

[U-Boot] [PATCH v2 1/2] mmc: sdhci: remove the unused argument for sdhci_setup_cfg
by Jaehoon Chung 05 Aug '16

05 Aug '16

buswidth isn't used anywhere in sdhci_setup_cfg. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Reviewed-by: Minkyu Kang <mk7.kang(a)samsung.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes for V2: - None drivers/mmc/msm_sdhci.c | 4 ++-- drivers/mmc/sdhci.c | 4 ++-- drivers/mmc/zynq_sdhci.c | 2 +- include/sdhci.h | 3 +-- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 70a8d96..e90a044 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -144,8 +144,8 @@ static int msm_sdc_probe(struct udevice *dev) host->version = sdhci_readw(host, SDHCI_HOST_VERSION); caps = sdhci_readl(host, SDHCI_CAPABILITIES); - ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width, - caps, 0, 0, host->version, host->quirks, 0); + ret = sdhci_setup_cfg(&plat->cfg, dev->name, caps, + 0, 0, host->version, host->quirks, 0); host->mmc = &plat->mmc; if (ret) return ret; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 4112223..c275314 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -511,7 +511,7 @@ static const struct mmc_ops sdhci_ops = { }; #endif -int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, +int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, uint caps, u32 max_clk, u32 min_clk, uint version, uint quirks, uint host_caps) { @@ -582,7 +582,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) } #endif - if (sdhci_setup_cfg(&host->cfg, host->name, host->bus_width, caps, + if (sdhci_setup_cfg(&host->cfg, host->name, caps, max_clk, min_clk, SDHCI_GET_VERSION(host), host->quirks, host->host_caps)) { printf("%s: Hardware doesn't specify base clock frequency\n", diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index bcd154a..69d6151 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -40,7 +40,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host->version = sdhci_readw(host, SDHCI_HOST_VERSION); caps = sdhci_readl(host, SDHCI_CAPABILITIES); - ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width, + ret = sdhci_setup_cfg(&plat->cfg, dev->name, caps, CONFIG_ZYNQ_SDHCI_MAX_FREQ, CONFIG_ZYNQ_SDHCI_MIN_FREQ, host->version, host->quirks, 0); diff --git a/include/sdhci.h b/include/sdhci.h index c4d3b55..693ecc1 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -368,7 +368,6 @@ static inline u8 sdhci_readb(struct sdhci_host *host, int reg) * * @cfg: Configuration structure to fill in (generally &plat->mmc) * @name: Device name (normally dev->name) - * @buswidth: Bus width (in bits, such as 4 or 8) * @caps: Host capabilities (MMC_MODE_...) * @max_clk: Maximum supported clock speed in HZ (0 for default) * @min_clk: Minimum supported clock speed in HZ (0 for default) @@ -377,7 +376,7 @@ static inline u8 sdhci_readb(struct sdhci_host *host, int reg) * @quirks: Quick flags (SDHCI_QUIRK_...) * @host_caps: Additional host capabilities (0 if none) */ -int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, +int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, uint caps, u32 max_clk, u32 min_clk, uint version, uint quirks, uint host_caps); -- 1.9.1

1 1

[U-Boot] rockchip: SecureBoot Support?
by Gregory Ray 05 Aug '16

05 Aug '16

Hello, Is SecureBoot from the manufacturers u-boot distribution operational? When I try to sign the loader using the SBC it complains "Sign loader failed!" I did a standard make: CROSS_COMPILE=/Developer/arm-eabi-4.8/bin/arm-eabi- make O=firefly firefly-rk3288_defconfig all Then generated the loader binary for SecureBootConsole by trying these combinations, all failed with same error: ./firefly/tools/mkimage -n rk3288 -T rkimage -d \ ./firefly/spl/u-boot-spl-nodtb.bin out && \ cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 > sbc_in.bin ./firefly/tools/mkimage -n rk3288 -T rkspi -d \ ./firefly/spl/u-boot-spl-nodtb.bin out && \ cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 > sbc_in.bin I also tried using the boot_merger tool from the manufacturer distribution using the RK3288.ini with PATH=./firefly/spl/u-boot-spl-nodtb.bin. This still failed with same error. If this feature is not yet functional, is it on the roadmap? Thanks, Gregory Ray

3 2

[U-Boot] [PATCH 1/5] pci: tegra: port to standard clock/reset/pwr domain APIs
by Stephen Warren 05 Aug '16

05 Aug '16

From: Stephen Warren <swarren(a)nvidia.com> Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so that it can operate with either set of APIs. On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming. Consequently, this logic is disabled too. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- This whole series builds on the other Tegra186 series that I just sent. drivers/pci/Kconfig | 1 + drivers/pci/pci_tegra.c | 154 ++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 150 insertions(+), 5 deletions(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 26aa2b0930a0..669e37bb5dc5 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -31,6 +31,7 @@ config PCI_SANDBOX config PCI_TEGRA bool "Tegra PCI support" depends on TEGRA + depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186) help Enable support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 352cdef56ab4..a6785ad0bbee 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -13,22 +13,26 @@ #define pr_fmt(fmt) "tegra-pcie: " fmt #include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> #include <pci.h> +#include <power-domain.h> +#include <reset.h> #include <asm/io.h> #include <asm/gpio.h> +#include <linux/list.h> + +#ifndef CONFIG_TEGRA186 #include <asm/arch/clock.h> #include <asm/arch/powergate.h> #include <asm/arch-tegra/xusb-padctl.h> - -#include <linux/list.h> - #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -103,6 +107,9 @@ DECLARE_GLOBAL_DATA_PTR; #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20) #define AFI_FUSE 0x104 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) @@ -110,6 +117,7 @@ DECLARE_GLOBAL_DATA_PTR; #define AFI_PEX0_CTRL 0x110 #define AFI_PEX1_CTRL 0x118 #define AFI_PEX2_CTRL 0x128 +#define AFI_PEX2_CTRL_T186 0x19c #define AFI_PEX_CTRL_RST (1 << 0) #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) @@ -173,6 +181,7 @@ enum tegra_pci_id { TEGRA30_PCIE, TEGRA124_PCIE, TEGRA210_PCIE, + TEGRA186_PCIE, }; struct tegra_pcie_port { @@ -189,6 +198,7 @@ struct tegra_pcie_soc { unsigned int num_ports; unsigned long pads_pll_ctl; unsigned long tx_ref_sel; + unsigned long afi_pex2_ctrl; u32 pads_refclk_cfg0; u32 pads_refclk_cfg1; bool has_pex_clkreq_en; @@ -209,7 +219,17 @@ struct tegra_pcie { unsigned long xbar; const struct tegra_pcie_soc *soc; + +#ifdef CONFIG_TEGRA186 + struct clk clk_afi; + struct clk clk_pex; + struct reset_ctl reset_afi; + struct reset_ctl reset_pex; + struct reset_ctl reset_pcie_x; + struct power_domain pwrdom; +#else struct tegra_xusb_phy *phy; +#endif }; static void afi_writel(struct tegra_pcie *pcie, unsigned long value, @@ -229,10 +249,12 @@ static void pads_writel(struct tegra_pcie *pcie, unsigned long value, writel(value, pcie->pads.start + offset); } +#ifndef CONFIG_TEGRA186 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) { return readl(pcie->pads.start + offset); } +#endif static unsigned long rp_readl(struct tegra_pcie_port *port, unsigned long offset) @@ -400,6 +422,24 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return 0; } break; + case TEGRA186_PCIE: + switch (lanes) { + case 0x0010004: + debug("x4 x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401; + return 0; + + case 0x0010102: + debug("x2 x1 x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211; + return 0; + + case 0x0010101: + debug("x1 x1 x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111; + return 0; + } + break; default: break; } @@ -471,6 +511,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return err; } +#ifndef CONFIG_TEGRA186 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); if (pcie->phy) { err = tegra_xusb_phy_prepare(pcie->phy); @@ -479,6 +520,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return err; } } +#endif fdt_for_each_subnode(fdt, subnode, node) { unsigned int index = 0, num_lanes = 0; @@ -523,6 +565,44 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return 0; } +#ifdef CONFIG_TEGRA186 +static int tegra_pcie_power_on(struct tegra_pcie *pcie) +{ + int ret; + + ret = power_domain_on(&pcie->pwrdom); + if (ret) { + error("power_domain_on() failed: %d\n", ret); + return ret; + } + + ret = clk_enable(&pcie->clk_afi); + if (ret) { + error("clk_enable(afi) failed: %d\n", ret); + return ret; + } + + ret = clk_enable(&pcie->clk_pex); + if (ret) { + error("clk_enable(pex) failed: %d\n", ret); + return ret; + } + + ret = reset_deassert(&pcie->reset_afi); + if (ret) { + error("reset_deassert(afi) failed: %d\n", ret); + return ret; + } + + ret = reset_deassert(&pcie->reset_pex); + if (ret) { + error("reset_deassert(pex) failed: %d\n", ret); + return ret; + } + + return 0; +} +#else static int tegra_pcie_power_on(struct tegra_pcie *pcie) { const struct tegra_pcie_soc *soc = pcie->soc; @@ -639,6 +719,7 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) return 0; } +#endif static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) { @@ -647,7 +728,11 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) u32 value; int err; +#ifdef CONFIG_TEGRA186 + { +#else if (pcie->phy) { +#endif value = afi_readl(pcie, AFI_PLLE_CONTROL); value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; @@ -675,6 +760,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) afi_writel(pcie, value, AFI_FUSE); +#ifndef CONFIG_TEGRA186 if (pcie->phy) err = tegra_xusb_phy_enable(pcie->phy); else @@ -684,9 +770,18 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) error("failed to power on PHY: %d\n", err); return err; } +#endif /* take the PCIEXCLK logic out of reset */ +#ifdef CONFIG_TEGRA186 + err = reset_deassert(&pcie->reset_pcie_x); + if (err) { + error("reset_deassert(pcie_x) failed: %d\n", err); + return err; + } +#else reset_set_enable(PERIPH_ID_PCIEXCLK, 0); +#endif /* finally enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); @@ -787,7 +882,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) break; case 2: - ret = AFI_PEX2_CTRL; + ret = port->pcie->soc->afi_pex2_ctrl; break; } @@ -945,6 +1040,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .num_ports = 3, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .afi_pex2_ctrl = AFI_PEX2_CTRL, .pads_refclk_cfg0 = 0xfa5cfa5c, .pads_refclk_cfg1 = 0xfa5cfa5c, .has_pex_clkreq_en = true, @@ -972,7 +1068,16 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .has_cml_clk = true, .has_gen2 = true, .force_pca_enable = true, - } + }, + [TEGRA186_PCIE] = { + .num_ports = 3, + .afi_pex2_ctrl = AFI_PEX2_CTRL_T186, + .pads_refclk_cfg0 = 0x80b880b8, + .pads_refclk_cfg1 = 0x000480b8, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_gen2 = true, + }, }; static int pci_tegra_ofdata_to_platdata(struct udevice *dev) @@ -996,6 +1101,44 @@ static int pci_tegra_probe(struct udevice *dev) struct tegra_pcie *pcie = dev_get_priv(dev); int err; +#ifdef CONFIG_TEGRA186 + err = clk_get_by_name(dev, "afi", &pcie->clk_afi); + if (err) { + debug("clk_get_by_name(afi) failed: %d\n", err); + return err; + } + + err = clk_get_by_name(dev, "pex", &pcie->clk_pex); + if (err) { + debug("clk_get_by_name(pex) failed: %d\n", err); + return err; + } + + err = reset_get_by_name(dev, "afi", &pcie->reset_afi); + if (err) { + debug("reset_get_by_name(afi) failed: %d\n", err); + return err; + } + + err = reset_get_by_name(dev, "pex", &pcie->reset_pex); + if (err) { + debug("reset_get_by_name(pex) failed: %d\n", err); + return err; + } + + err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x); + if (err) { + debug("reset_get_by_name(pcie_x) failed: %d\n", err); + return err; + } + + err = power_domain_get(dev, &pcie->pwrdom); + if (err) { + debug("power_domain_get() failed: %d\n", err); + return err; + } +#endif + err = tegra_pcie_power_on(pcie); if (err < 0) { error("failed to power on"); @@ -1033,6 +1176,7 @@ static const struct udevice_id pci_tegra_ids[] = { { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE }, { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE }, { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE }, + { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE }, { } }; -- 2.9.2

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[U-Boot] [PATCH 1/2] fdt_support: fdt_translate_address() blob const correctness
by Stephen Warren 05 Aug '16

05 Aug '16

From: Stephen Warren <swarren(a)nvidia.com> The next patch will call fdt_translate_address() from somewhere with a "const void *blob" rather than a "void *blob", so fdt_translate_address() must accept a const pointer too. Constify the minimum number of function parameters to achieve this. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- common/fdt_support.c | 19 ++++++++++--------- include/fdt_support.h | 5 +++-- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 5d8eb12f1073..da59f2c8cc07 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -997,8 +997,8 @@ static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { } struct of_bus { const char *name; const char *addresses; - int (*match)(void *blob, int parentoffset); - void (*count_cells)(void *blob, int parentoffset, + int (*match)(const void *blob, int parentoffset); + void (*count_cells)(const void *blob, int parentoffset, int *addrc, int *sizec); u64 (*map)(fdt32_t *addr, const fdt32_t *range, int na, int ns, int pna); @@ -1006,7 +1006,7 @@ struct of_bus { }; /* Default translator (generic bus) */ -void of_bus_default_count_cells(void *blob, int parentoffset, +void of_bus_default_count_cells(const void *blob, int parentoffset, int *addrc, int *sizec) { const fdt32_t *prop; @@ -1066,7 +1066,7 @@ static int of_bus_isa_match(void *blob, int parentoffset) return !strcmp(name, "isa"); } -static void of_bus_isa_count_cells(void *blob, int parentoffset, +static void of_bus_isa_count_cells(const void *blob, int parentoffset, int *addrc, int *sizec) { if (addrc) @@ -1126,7 +1126,7 @@ static struct of_bus of_busses[] = { }, }; -static struct of_bus *of_match_bus(void *blob, int parentoffset) +static struct of_bus *of_match_bus(const void *blob, int parentoffset) { struct of_bus *bus; @@ -1148,7 +1148,7 @@ static struct of_bus *of_match_bus(void *blob, int parentoffset) return NULL; } -static int of_translate_one(void * blob, int parent, struct of_bus *bus, +static int of_translate_one(const void *blob, int parent, struct of_bus *bus, struct of_bus *pbus, fdt32_t *addr, int na, int ns, int pna, const char *rprop) { @@ -1211,8 +1211,8 @@ static int of_translate_one(void * blob, int parent, struct of_bus *bus, * that can be mapped to a cpu physical address). This is not really specified * that way, but this is traditionally the way IBM at least do things */ -static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in_addr, - const char *rprop) +static u64 __of_translate_address(const void *blob, int node_offset, + const fdt32_t *in_addr, const char *rprop) { int parent; struct of_bus *bus, *pbus; @@ -1284,7 +1284,8 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in return result; } -u64 fdt_translate_address(void *blob, int node_offset, const fdt32_t *in_addr) +u64 fdt_translate_address(const void *blob, int node_offset, + const fdt32_t *in_addr) { return __of_translate_address(blob, node_offset, in_addr, "ranges"); } diff --git a/include/fdt_support.h b/include/fdt_support.h index 731809874f48..e9f3497ab642 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -180,7 +180,8 @@ static inline void fdt_fixup_mtdparts(void *fdt, void *node_info, #endif void fdt_del_node_and_alias(void *blob, const char *alias); -u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr); +u64 fdt_translate_address(const void *blob, int node_offset, + const __be32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); int fdt_alloc_phandle(void *blob); @@ -239,7 +240,7 @@ static inline u64 of_read_number(const fdt32_t *cell, int size) return r; } -void of_bus_default_count_cells(void *blob, int parentoffset, +void of_bus_default_count_cells(const void *blob, int parentoffset, int *addrc, int *sizec); int ft_verify_fdt(void *fdt); int arch_fixup_memory_node(void *blob); -- 2.9.2

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[U-Boot] [PATCH v4 00/11] MIPS Boston Development Board Support
by Paul Burton 05 Aug '16

05 Aug '16

This series introduces initial support for the MIPS Boston, and FPGA based development board & successor to the older Malta board. Further peripheral work is needed but this introduces the basics. This can be tested in a currently out-of-tree QEMU port if desired, which can be found in the boston branch of: git://git.linux-mips.org/pub/scm/paul/qemu.git QEMU can be used to run U-Boot like this: ./configure --target-list=mips64el-softmmu make ./mips64el-softmmu/qemu-system-mips64el -M boston -m 2G \ -bios u-boot.bin -serial stdio Paul Burton (11): serial: ns16550: Support clocks via phandle dt-bindings: Add interrupt-controller/mips-gic.h header pci: xilinx: Add a driver for Xilinx AXI to PCIe bridge pci: Flip condition for detecting non-PCI parent devices net: pch_gbe: Use dm_pci_map_bar to discover MMIO base net: pch_gbe: Make 64 bit safe dm: regmap: Implement simple regmap_read & regmap_write dm: core: Match compatible strings in order of priority dm: syscon: Provide a generic syscon driver clk: boston: Providea simple driver for Boston board clocks boston: Introduce support for the MIPS Boston development board arch/mips/Kconfig | 16 ++ arch/mips/dts/Makefile | 1 + arch/mips/dts/img,boston.dts | 216 ++++++++++++++++++++ board/imgtec/boston/Kconfig | 16 ++ board/imgtec/boston/MAINTAINERS | 6 + board/imgtec/boston/Makefile | 9 + board/imgtec/boston/boston-lcd.h | 21 ++ board/imgtec/boston/boston-regs.h | 47 +++++ board/imgtec/boston/checkboard.c | 29 +++ board/imgtec/boston/ddr.c | 30 +++ board/imgtec/boston/lowlevel_init.S | 56 ++++++ configs/boston32r2_defconfig | 40 ++++ configs/boston32r2el_defconfig | 41 ++++ configs/boston64r2_defconfig | 40 ++++ configs/boston64r2el_defconfig | 41 ++++ doc/README.boston | 39 ++++ drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk_boston.c | 97 +++++++++ drivers/core/lists.c | 83 ++++---- drivers/core/regmap.c | 20 ++ drivers/core/syscon-uclass.c | 11 ++ drivers/net/pch_gbe.c | 28 ++- drivers/pci/Kconfig | 7 + drivers/pci/Makefile | 1 + drivers/pci/pci-uclass.c | 2 +- drivers/pci/pcie_xilinx.c | 219 +++++++++++++++++++++ drivers/serial/ns16550.c | 19 +- include/configs/boston.h | 68 +++++++ include/dt-bindings/clock/boston-clock.h | 13 ++ .../dt-bindings/interrupt-controller/mips-gic.h | 9 + 31 files changed, 1173 insertions(+), 61 deletions(-) create mode 100644 arch/mips/dts/img,boston.dts create mode 100644 board/imgtec/boston/Kconfig create mode 100644 board/imgtec/boston/MAINTAINERS create mode 100644 board/imgtec/boston/Makefile create mode 100644 board/imgtec/boston/boston-lcd.h create mode 100644 board/imgtec/boston/boston-regs.h create mode 100644 board/imgtec/boston/checkboard.c create mode 100644 board/imgtec/boston/ddr.c create mode 100644 board/imgtec/boston/lowlevel_init.S create mode 100644 configs/boston32r2_defconfig create mode 100644 configs/boston32r2el_defconfig create mode 100644 configs/boston64r2_defconfig create mode 100644 configs/boston64r2el_defconfig create mode 100644 doc/README.boston create mode 100644 drivers/clk/clk_boston.c create mode 100644 drivers/pci/pcie_xilinx.c create mode 100644 include/configs/boston.h create mode 100644 include/dt-bindings/clock/boston-clock.h create mode 100644 include/dt-bindings/interrupt-controller/mips-gic.h -- 2.9.0

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[U-Boot] [PATCH v2] arm: cache: always flush cache line size for page table
by Stefan Agner 05 Aug '16

05 Aug '16

From: Stefan Agner <stefan.agner(a)toradex.com> The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: Stefan Agner <stefan.agner(a)toradex.com> --- Changes since v1: - Move cache line alignment from mmu_page_table_flush to mmu_set_region_dcache_behaviour arch/arm/lib/cache-cp15.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 1121dc3..bf79edd 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -62,6 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { u32 *page_table = (u32 *)gd->arch.tlb_addr; + phys_addr_t startpt, stoppt; unsigned long upto, end; end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; @@ -70,7 +71,17 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, option); for (upto = start; upto < end; upto++) set_section_dcache(upto, option); - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); + + /* + * Make sure range is cache line aligned + * Only CPU maintains page tables, hence it is save to always + * flush complete cache lines... + */ + startpt = (phys_addr_t)&page_table[start]; + startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); + stoppt = (phys_addr_t)&page_table[end]; + stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE); + mmu_page_table_flush(startpt, stoppt); } __weak void dram_bank_mmu_setup(int bank) -- 2.9.0

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[U-Boot] pine64 and "sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80"
by Tom Rini 04 Aug '16

04 Aug '16

Hey guys, I just started trying out my Pine64 1GB and mainline U-Boot and I've found that: commit 1a83fb4a17d959d7b037999ab7ed7e62429abe34 Author: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> Date: Tue May 31 01:48:06 2016 +0300 sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80 is breaking boot for me. boot0 seems to run fine and then the last bit of output that I get is: boot0: start load other image boot0: Loading BL3-1 Loading file 0 at address 0x40000000,size 0x00000200 success boot0: Loading scp Loading file 2 at address 0x00040000,size 0x0000c200 success set arisc reset to de-assert state Ready to disable icache. Jump to secend Boot. NOTICE: BL3-1: Running in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):d697594 NOTICE: BL3-1: Built : 09:15:57, Aug 4 2016 NOTICE: Configuring AXP PMIC NOTICE: PMIC: already configured for RSB NOTICE: PMIC: setup successful INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9 I'm using d697594 from https://github.com/apritzel/arm-trusted-firmware.git for ATF and boot0.img from the 20160701 Debian "longsleep" image. Any ideas? Thanks! -- Tom

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