August 2016 - U-Boot

[U-Boot] [PATCH 0/6] sh4: fix and simplify cache manipulation
by Vladimir Zapolskiy 08 Aug '16

08 Aug '16

In my tests I experience that sometimes SH4 does not properly fetch instructions after immediate jump to a code loaded by means of rtl8139, the problem is gone if "icache off" is executed after load or if cache invalidation and write-back is used on data load instead of just cache invalidation, which is apparently an improper backbone of flush_dcache_range() function. The changeset contains a couple of bugfixes and a general simplification of the code related to cache manipulation. Note that while caches are found on SH2 and SH3 for long time they were inactive in U-Boot, because I don't have SH2/SH3 hardware for testing I don't spread SH4 cache fixes to those cpus, however generally it should be the same, in that case arch/sh/cpu/sh4/cache.c file can be moved to arch/sh/lib folder For 3/6 patch there is a minor patch application dependency on one change https://patchwork.ozlabs.org/patch/656383/ , so formally it might be easier to apply the series after the series, which switches SH architectures to generic board. Vladimir Zapolskiy (6): sh4: cache: correct dcache flush to invalidate with write-back sh4: cache: correct flush_cache() to writeback and invalidate sh3: remove unused cache.c file from being built sh: cache use jump_to_P2() and back_to_P1() from asm/system.h sh: cache: don't modify CCR from P1 area sh4: cache: move exported cache manipulation functions into cache.c arch/sh/cpu/sh3/Makefile | 2 +- arch/sh/cpu/sh3/cache.c | 96 --------------------------------------------- arch/sh/cpu/sh4/cache.c | 88 ++++++++++++++++++++--------------------- arch/sh/cpu/sh4/cpu.c | 34 ---------------- arch/sh/include/asm/cache.h | 2 - 5 files changed, 43 insertions(+), 179 deletions(-) delete mode 100644 arch/sh/cpu/sh3/cache.c -- 2.8.1

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[U-Boot] [PATCH V4 1/4] clock: add Tegra186 clock driver
by Stephen Warren 08 Aug '16

08 Aug '16

From: Stephen Warren <swarren(a)nvidia.com> In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- v4: Adapt to new misc_call() return code. v3: Use misc class call op. v2: This patch wasn't posted. --- arch/arm/mach-tegra/Kconfig | 2 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 2 + drivers/clk/tegra/Kconfig | 6 +++ drivers/clk/tegra/Makefile | 5 ++ drivers/clk/tegra/tegra186-clk.c | 104 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 120 insertions(+) create mode 100644 drivers/clk/tegra/Kconfig create mode 100644 drivers/clk/tegra/Makefile create mode 100644 drivers/clk/tegra/tegra186-clk.c diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index ec2d8ac6a1a3..e8186d515856 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -64,9 +64,11 @@ config TEGRA210 config TEGRA186 bool "Tegra186 family" + select CLK select DM_MAILBOX select MISC select TEGRA186_BPMP + select TEGRA186_CLOCK select TEGRA186_GPIO select TEGRA_ARMV8_COMMON select TEGRA_HSP diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 6eee8eb369bf..7dd56738b06a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,6 +20,7 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper. +source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 3cbdd54f4f3e..463b1d647dc6 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,5 +10,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o + +obj-y += tegra/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig new file mode 100644 index 000000000000..659fe022c2af --- /dev/null +++ b/drivers/clk/tegra/Kconfig @@ -0,0 +1,6 @@ +config TEGRA186_CLOCK + bool "Enable Tegra186 BPMP-based clock driver" + depends on TEGRA186_BPMP + help + Enable support for manipulating Tegra's on-SoC clocks via IPC + requests to the BPMP (Boot and Power Management Processor). diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile new file mode 100644 index 000000000000..f32998ccc27d --- /dev/null +++ b/drivers/clk/tegra/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o diff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c new file mode 100644 index 000000000000..075cb464cf6f --- /dev/null +++ b/drivers/clk/tegra/tegra186-clk.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <misc.h> +#include <asm/arch-tegra/bpmp_abi.h> + +static ulong tegra186_clk_get_rate(struct clk *clk) +{ + struct mrq_clk_request req; + struct mrq_clk_response resp; + int ret; + + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id; + + ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + return resp.clk_get_rate.rate; +} + +static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate) +{ + struct mrq_clk_request req; + struct mrq_clk_response resp; + int ret; + + debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate, + clk->dev, clk->id); + + req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id; + req.clk_set_rate.rate = rate; + + ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + return resp.clk_set_rate.rate; +} + +static int tegra186_clk_en_dis(struct clk *clk, + enum mrq_reset_commands cmd) +{ + struct mrq_clk_request req; + struct mrq_clk_response resp; + int ret; + + req.cmd_and_id = (cmd << 24) | clk->id; + + ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + return 0; +} + +static int tegra186_clk_enable(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE); +} + +static int tegra186_clk_disable(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE); +} + +static struct clk_ops tegra186_clk_ops = { + .get_rate = tegra186_clk_get_rate, + .set_rate = tegra186_clk_set_rate, + .enable = tegra186_clk_enable, + .disable = tegra186_clk_disable, +}; + +static int tegra186_clk_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +U_BOOT_DRIVER(tegra186_clk) = { + .name = "tegra186_clk", + .id = UCLASS_CLK, + .probe = tegra186_clk_probe, + .ops = &tegra186_clk_ops, +}; -- 2.9.2

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[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 08 Aug '16

08 Aug '16

The following changes since commit 2863a9bfc29092be37f8beee230883367b057065: Merge git://git.denx.de/u-boot-rockchip (2016-08-06 11:38:14 -0400) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to 5405817a6e7a6538c4bcb1c3076ddc83fe5d03f9: spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value (2016-08-07 21:54:21 +0200) ---------------------------------------------------------------- Chin Liang See (1): spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value Masahiro Yamada (1): ARM: socfpga: use the default CONFIG_BOOTDELAY=2 configs/socfpga_arria5_defconfig | 1 - configs/socfpga_cyclone5_defconfig | 1 - configs/socfpga_de0_nano_soc_defconfig | 1 - configs/socfpga_is1_defconfig | 1 - configs/socfpga_mcvevk_defconfig | 1 - configs/socfpga_sockit_defconfig | 1 - configs/socfpga_socrates_defconfig | 1 - configs/socfpga_sr1500_defconfig | 1 - drivers/spi/cadence_qspi_apb.c | 7 +++++-- 9 files changed, 5 insertions(+), 10 deletions(-)

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[U-Boot] [PATCH 1/6] sf: Simplify fastest read cmd code
by Jagan Teki 08 Aug '16

08 Aug '16

Fastest read command code look for fastest read command taking inputs from spi->mode_rx and flags from param table and controller mode_rx is always been a priority. Since mode_rx is always set from controller side this optimized code doesn't require much and this code required exctra overhead like 1) Maintain e_rx_cmd in param table 2) Maintain mode_rx in spi_slave {} Hence removed this code, and look for read command from normal spi->mode from spi_slave{} and params->flags Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Cc: Vignesh R <vigneshr(a)ti.com> Cc: Mugunthan V N <mugunthanvnm(a)ti.com> Signed-off-by: Jagan Teki <jteki(a)openedev.com> --- drivers/mtd/spi/sf_internal.h | 4 ++++ drivers/mtd/spi/spi_flash.c | 28 ++++++++++------------------ 2 files changed, 14 insertions(+), 18 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index da2bb7b..c5cb791 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -46,6 +46,10 @@ enum { E_FSR = BIT(2), SST_WR = BIT(3), WR_QPP = BIT(4), + RD_QUAD = BIT(5), + RD_DUAL = BIT(6), + RD_QUADIO = BIT(7), + RD_DUALIO = BIT(8), }; enum spi_nor_option_flags { diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 64d4e0f..5fd408c 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -1013,15 +1013,8 @@ int spi_flash_scan(struct spi_flash *flash) struct spi_slave *spi = flash->spi; const struct spi_flash_params *params; u16 jedec, ext_jedec; - u8 cmd, idcode[5]; + u8 idcode[5]; int ret; - static u8 spi_read_cmds_array[] = { - CMD_READ_ARRAY_SLOW, - CMD_READ_ARRAY_FAST, - CMD_READ_DUAL_OUTPUT_FAST, - CMD_READ_QUAD_OUTPUT_FAST, - CMD_READ_DUAL_IO_FAST, - CMD_READ_QUAD_IO_FAST }; /* Read the ID codes */ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); @@ -1177,17 +1170,16 @@ int spi_flash_scan(struct spi_flash *flash) /* Now erase size becomes valid sector size */ flash->sector_size = flash->erase_size; - /* Look for the fastest read cmd */ - cmd = fls(params->e_rd_cmd & spi->mode_rx); - if (cmd) { - cmd = spi_read_cmds_array[cmd - 1]; - flash->read_cmd = cmd; - } else { - /* Go for default supported read cmd */ - flash->read_cmd = CMD_READ_ARRAY_FAST; - } + /* Look for read commands */ + flash->read_cmd = CMD_READ_ARRAY_FAST; + if (spi->mode_rx & SPI_RX_SLOW) + flash->read_cmd = CMD_READ_ARRAY_SLOW; + else if (spi->mode_rx & SPI_RX_QUAD && params->flags & RD_QUAD) + flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST; + else if (spi->mode_rx & SPI_RX_DUAL && params->flags & RD_DUAL) + flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST; - /* Not require to look for fastest only two write cmds yet */ + /* Look for write commands */ if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD) flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; else -- 2.7.4

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[U-Boot] [PATCH 1/2] warp7: Modify fdt_file environment variable
by Breno Lima 08 Aug '16

08 Aug '16

Use imx7s-warp.dts as fdt_file because this is the name that upstream kernel will deploy. Signed-off-by: Breno Lima <breno.lima(a)nxp.com> --- include/configs/warp7.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/warp7.h b/include/configs/warp7.h index e59b16c..91009a8 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -39,7 +39,7 @@ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx7d-warp.dtb\0" \ + "fdt_file=imx7s-warp.dtb\0" \ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ -- 2.7.4

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[U-Boot] [PATCH] cmd: dfu: Add error handling for failed registration
by Sanchayan Maity 08 Aug '16

08 Aug '16

Without this, if g_dnl_register() fails, DFU code continues on blindly and crashes. This fix makes it simply print an error message instead. Signed-off-by: Sanchayan Maity <maitysanchayan(a)gmail.com> --- cmd/dfu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/cmd/dfu.c b/cmd/dfu.c index d8aae26..e19d69c 100644 --- a/cmd/dfu.c +++ b/cmd/dfu.c @@ -54,7 +54,12 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int controller_index = simple_strtoul(usb_controller, NULL, 0); board_usb_init(controller_index, USB_INIT_DEVICE); g_dnl_clear_detach(); - g_dnl_register("usb_dnl_dfu"); + ret = g_dnl_register("usb_dnl_dfu"); + if (ret) { + error("g_dnl_register failed"); + return CMD_RET_FAILURE; + } + while (1) { if (g_dnl_detach()) { /* -- 2.9.2

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Re: [U-Boot] [PATCH] net: e1000: Allow to use e1000 SPI command with DM
by Yaroslav K. 08 Aug '16

08 Aug '16

Hi Joe. You should probably just take Alban's patch. I don't care about my SOB. -- Yaroslav

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[U-Boot] [PATCH] net: e1000: Allow to use e1000 SPI command with DM
by Yaroslav K. 08 Aug '16

08 Aug '16

Fix compile errors when enabling CONFIG_DM_ETH, CONFIG_CMD_E1000 and CONFIG_E1000_SPI. Signed-off-by: Yaroslav K. <yar444(a)gmail.com> --- drivers/net/e1000.c | 6 ++++- drivers/net/e1000_spi.c | 60 ++++++++++++++++++++++++------------------------- 2 files changed, 35 insertions(+), 31 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 196989b..09d6870 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5513,7 +5513,8 @@ static int do_e1000(cmd_tbl_t *cmdtp, int flag, struct udevice *dev; char name[30]; int ret; -#else +#endif +#if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI) struct e1000_hw *hw; #endif int cardnum; @@ -5532,6 +5533,9 @@ static int do_e1000(cmd_tbl_t *cmdtp, int flag, plat = dev_get_platdata(dev); mac = plat->enetaddr; } +#ifdef CONFIG_E1000_SPI + hw = dev_get_priv(dev); +#endif #else hw = e1000_find_card(cardnum); if (hw) diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index 576ddb8..78f4f15 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -94,29 +94,29 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, /* Make sure it has an SPI chip */ if (hw->eeprom.type != e1000_eeprom_spi) { - E1000_ERR(hw->nic, "No attached SPI EEPROM found!\n"); + E1000_ERR(hw, "No attached SPI EEPROM found!\n"); return NULL; } /* Argument sanity checks */ if (cs != 0) { - E1000_ERR(hw->nic, "No such SPI chip: %u\n", cs); + E1000_ERR(hw, "No such SPI chip: %u\n", cs); return NULL; } if (mode != SPI_MODE_0) { - E1000_ERR(hw->nic, "Only SPI MODE-0 is supported!\n"); + E1000_ERR(hw, "Only SPI MODE-0 is supported!\n"); return NULL; } /* TODO: Use max_hz somehow */ - E1000_DBG(hw->nic, "EEPROM SPI access requested\n"); + E1000_DBG(hw, "EEPROM SPI access requested\n"); return &hw->spi; } void spi_free_slave(struct spi_slave *spi) { __maybe_unused struct e1000_hw *hw = e1000_hw_from_spi(spi); - E1000_DBG(hw->nic, "EEPROM SPI access released\n"); + E1000_DBG(hw, "EEPROM SPI access released\n"); } int spi_claim_bus(struct spi_slave *spi) @@ -124,7 +124,7 @@ int spi_claim_bus(struct spi_slave *spi) struct e1000_hw *hw = e1000_hw_from_spi(spi); if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); return -1; } @@ -342,41 +342,41 @@ static int do_e1000_spi_show(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Extra sanity checks */ if (!length) { - E1000_ERR(hw->nic, "Requested zero-sized dump!\n"); + E1000_ERR(hw, "Requested zero-sized dump!\n"); return 1; } if ((0x10000 < length) || (0x10000 - length < offset)) { - E1000_ERR(hw->nic, "Can't dump past 0xFFFF!\n"); + E1000_ERR(hw, "Can't dump past 0xFFFF!\n"); return 1; } /* Allocate a buffer to hold stuff */ buffer = malloc(length); if (!buffer) { - E1000_ERR(hw->nic, "Out of Memory!\n"); + E1000_ERR(hw, "Out of Memory!\n"); return 1; } /* Acquire the EEPROM and perform the dump */ if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); free(buffer); return 1; } err = e1000_spi_eeprom_dump(hw, buffer, offset, length, true); e1000_release_eeprom(hw); if (err) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); free(buffer); return 1; } /* Now hexdump the result */ printf("%s: ===== Intel e1000 EEPROM (0x%04hX - 0x%04hX) =====", - hw->nic->name, offset, offset + length - 1); + hw->name, offset, offset + length - 1); for (i = 0; i < length; i++) { if ((i & 0xF) == 0) - printf("\n%s: %04hX: ", hw->nic->name, offset + i); + printf("\n%s: %04hX: ", hw->name, offset + i); else if ((i & 0xF) == 0x8) printf(" "); printf(" %02hx", buffer[i]); @@ -407,29 +407,29 @@ static int do_e1000_spi_dump(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Extra sanity checks */ if (!length) { - E1000_ERR(hw->nic, "Requested zero-sized dump!\n"); + E1000_ERR(hw, "Requested zero-sized dump!\n"); return 1; } if ((0x10000 < length) || (0x10000 - length < offset)) { - E1000_ERR(hw->nic, "Can't dump past 0xFFFF!\n"); + E1000_ERR(hw, "Can't dump past 0xFFFF!\n"); return 1; } /* Acquire the EEPROM */ if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); return 1; } /* Perform the programming operation */ if (e1000_spi_eeprom_dump(hw, dest, offset, length, true) < 0) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; } e1000_release_eeprom(hw); - printf("%s: ===== EEPROM DUMP COMPLETE =====\n", hw->nic->name); + printf("%s: ===== EEPROM DUMP COMPLETE =====\n", hw->name); return 0; } @@ -452,19 +452,19 @@ static int do_e1000_spi_program(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Acquire the EEPROM */ if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); return 1; } /* Perform the programming operation */ if (e1000_spi_eeprom_program(hw, source, offset, length, true) < 0) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; } e1000_release_eeprom(hw); - printf("%s: ===== EEPROM PROGRAMMED =====\n", hw->nic->name); + printf("%s: ===== EEPROM PROGRAMMED =====\n", hw->name); return 0; } @@ -488,19 +488,19 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, length = sizeof(uint16_t) * (EEPROM_CHECKSUM_REG + 1); buffer = malloc(length); if (!buffer) { - E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n"); + E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); return 1; } /* Acquire the EEPROM */ if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); return 1; } /* Read the EEPROM */ if (e1000_spi_eeprom_dump(hw, buffer, 0, length, true) < 0) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; } @@ -514,14 +514,14 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Verify it! */ if (checksum_reg == checksum) { printf("%s: INFO: EEPROM checksum is correct! (0x%04hx)\n", - hw->nic->name, checksum); + hw->name, checksum); e1000_release_eeprom(hw); return 0; } /* Hrm, verification failed, print an error */ - E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n"); - E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n", + E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); + E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", checksum_reg, checksum); /* If they didn't ask us to update it, just return an error */ @@ -531,11 +531,11 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, } /* Ok, correct it! */ - printf("%s: Reprogramming the EEPROM checksum...\n", hw->nic->name); + printf("%s: Reprogramming the EEPROM checksum...\n", hw->name); buffer[i] = cpu_to_le16(checksum); if (e1000_spi_eeprom_program(hw, &buffer[i], i * sizeof(uint16_t), sizeof(uint16_t), true)) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; } @@ -554,7 +554,7 @@ int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Make sure it has an SPI chip */ if (hw->eeprom.type != e1000_eeprom_spi) { - E1000_ERR(hw->nic, "No attached SPI EEPROM found!\n"); + E1000_ERR(hw, "No attached SPI EEPROM found!\n"); return 1; } -- 1.9.1

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[U-Boot] [PATCH 1/3] mmc: fsl: reset to normal boot mode when eMMC fast boot
by Peng Fan 08 Aug '16

08 Aug '16

When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: York Sun <york.sun(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/mmc/fsl_esdhc.c | 38 +++++++++++++++++++++++++++++--------- include/fsl_esdhc.h | 6 ++++++ 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 65ecff5..15cd419 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -57,21 +57,27 @@ struct fsl_esdhc { uint fevt; /* Force event register */ uint admaes; /* ADMA error status register */ uint adsaddr; /* ADMA system address register */ - char reserved2[100]; /* reserved */ - uint vendorspec; /* Vendor Specific register */ - char reserved3[56]; /* reserved */ + char reserved2[4]; + uint dllctrl; + uint dllstat; + uint clktunectrlstatus; + char reserved3[84]; + uint vendorspec; + uint mmcboot; + uint vendorspec2; + char reserved4[48]; uint hostver; /* Host controller version register */ - char reserved4[4]; /* reserved */ - uint dmaerraddr; /* DMA error address register */ char reserved5[4]; /* reserved */ - uint dmaerrattr; /* DMA error attribute register */ + uint dmaerraddr; /* DMA error address register */ char reserved6[4]; /* reserved */ + uint dmaerrattr; /* DMA error attribute register */ + char reserved7[4]; /* reserved */ uint hostcapblt2; /* Host controller capabilities register 2 */ - char reserved7[8]; /* reserved */ + char reserved8[8]; /* reserved */ uint tcr; /* Tuning control register */ - char reserved8[28]; /* reserved */ + char reserved9[28]; /* reserved */ uint sddirctl; /* SD direction control register */ - char reserved9[712]; /* reserved */ + char reserved10[712];/* reserved */ uint scr; /* eSDHC control register */ }; @@ -618,6 +624,20 @@ static int esdhc_init(struct mmc *mmc) while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout) udelay(1000); +#if defined(CONFIG_FSL_USDHC) + /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ + esdhc_write32(&regs->mmcboot, 0x0); + /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ + esdhc_write32(&regs->mixctrl, 0x0); + esdhc_write32(&regs->clktunectrlstatus, 0x0); + + /* Put VEND_SPEC to default value */ + esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT); + + /* Disable DLL_CTRL delay line */ + esdhc_write32(&regs->dllctrl, 0x0); +#endif + #ifndef ARCH_MXC /* Enable cache snooping */ esdhc_write32(&regs->scr, 0x00000040); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index fa760a5..78c67c8 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -35,6 +35,12 @@ #define SYSCTL_RSTC 0x02000000 #define SYSCTL_RSTD 0x04000000 +#define VENDORSPEC_CKEN 0x00004000 +#define VENDORSPEC_PEREN 0x00002000 +#define VENDORSPEC_HCKEN 0x00001000 +#define VENDORSPEC_IPGEN 0x00000800 +#define VENDORSPEC_INIT 0x20007809 + #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) #define IRQSTAT_AC12E (0x01000000) -- 2.6.2

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[U-Boot] Prospective contributer
by nilan chamara 08 Aug '16

08 Aug '16

Hi All, I have been working as a Software/Firmware engineer for 10 years now, and keen to contribute to UBoot code base with some peripheral device driver patches. I would like to know the procedure to follow, and where should I create my patches (from main git repo or Custodians <http://www.denx.de/wiki/U-Boot/Custodians> repo). To start with I am expecting to submit patches which support LED driver chip / Temperature Sensor / Battery fuel gauge to UBoot. Any information or help would be highly appreciated. Thanks Nilan

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