August 2016 - U-Boot

[U-Boot] [PATCH v1 1/4] usb: host: ehci-vf: Migrate Vybrid USB to driver model
by Sanchayan Maity 09 Aug '16

09 Aug '16

Add driver model support for Vybrid USB driver. Signed-off-by: Sanchayan Maity <maitysanchayan(a)gmail.com> --- Hello, I am trying to migrate the Vybrid USB driver to driver model. Patches are based on top of uboot master branch. With this implementation, host works perfectly fine on both USB ports but I have problems using it in client mode. I tried DFU to test client mode and I get the following Colibri VFxx # version U-Boot 2016.09-rc1-00235-g4e8c122 (Aug 03 2016 - 17:07:48 +0530) arm-linux-gnueabihf-gcc (Linaro GCC 5.2-2015.11-2) 5.2.1 20151005 GNU ld (GNU Binutils) 2.25.0 Linaro 2015_10 Colibri VFxx # dfu 0 nand 4 using id 'nand0,0' using id 'nand0,1' using id 'nand0,3' g_dnl_register: failed!, error: -19 data abort pc : [<8ff80f18>] lr : [<8ff612a9>] reloc pc : [<3f431f18>] lr : [<3f4122a9>] sp : 8fd15000 ip : 00000000 fp : 00002710 r10: 8ffb50cc r9 : 8fd16ee8 r8 : 8ffbc574 r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000 r3 : 0000f4b9 r2 : 80000000 r1 : 00000001 r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... It seems to return ENODEV from usb_setup_ehci_gadget after calling uclass_find_device_by_seq. I am not sure what I am missing in the current implementation. Can someone point me in the correct direction? Since host works on both ports I would assume the device tree nodes are correct. Tried to look in documentation and usb-info.txt mentions that gadget framework does not use driver model. Does this imply I cannot use any usb gadget functionality if I am using USB DM? However the function usb_gadget_register_driver in ci_udc.c does have a CONFIG_DM_USB and calls into usb_setup_ehci_gadget which is in usb-uclass.c. Regards, Sanchayan. --- drivers/usb/host/ehci-vf.c | 123 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 117 insertions(+), 6 deletions(-) diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 61789dd..8c5c593 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <dm.h> #include <usb.h> #include <errno.h> #include <linux/compiler.h> @@ -131,6 +132,24 @@ int __weak board_ehci_hcd_init(int port) return 0; } +int ehci_vf_common_init(struct usb_ehci *ehci, int index) +{ + int ret; + + /* Do board specific initialisation */ + ret = board_ehci_hcd_init(index); + if (ret) + return ret; + + usb_power_config(index); + usb_oc_config(index); + usb_internal_phy_clock_gate(index); + usb_phy_enable(index, ehci); + + return 0; +} + +#ifndef CONFIG_DM_USB int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { @@ -143,12 +162,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, ehci = (struct usb_ehci *)nc_reg_bases[index]; /* Do board specific initialisation */ - board_ehci_hcd_init(index); - - usb_power_config(index); - usb_oc_config(index); - usb_internal_phy_clock_gate(index); - usb_phy_enable(index, ehci); + ret = ehci_vf_common_init(index); + if (ret) + return ret; *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); *hcor = (struct ehci_hcor *)((uint32_t)*hccr + @@ -175,3 +191,98 @@ int ehci_hcd_stop(int index) { return 0; } +#else +struct ehci_vf_priv_data { + struct ehci_ctrl ctrl; + struct usb_ehci *ehci; + enum usb_init_type init_type; + int portnr; +}; + +static int vf_init_after_reset(struct ehci_ctrl *dev) +{ + struct ehci_vf_priv_data *priv = dev->priv; + enum usb_init_type type = priv->init_type; + struct usb_ehci *ehci = priv->ehci; + int ret; + + ret = ehci_vf_common_init(priv->ehci, priv->portnr); + if (ret) + return ret; + + if (type == USB_INIT_DEVICE) + return 0; + + setbits_le32(&ehci->usbmode, CM_HOST); + writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc); + setbits_le32(&ehci->portsc, USB_EN); + + mdelay(10); + + return 0; +} + +static const struct ehci_ops vf_ehci_ops = { + .init_after_reset = vf_init_after_reset +}; + +static int ehci_usb_probe(struct udevice *dev) +{ + struct usb_platdata *plat = dev_get_platdata(dev); + struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev); + struct ehci_vf_priv_data *priv = dev_get_priv(dev); + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + int ret; + + priv->ehci = ehci; + priv->portnr = dev->seq; + priv->init_type = plat->init_type; + + ret = ehci_vf_common_init(ehci, priv->portnr); + if (ret) + return ret; + + if (priv->init_type == USB_INIT_HOST) { + setbits_le32(&ehci->usbmode, CM_HOST); + writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc); + setbits_le32(&ehci->portsc, USB_EN); + } + + mdelay(10); + + hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t)hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, &vf_ehci_ops, 0, plat->init_type); +} + +static int ehci_usb_remove(struct udevice *dev) +{ + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id vf_usb_ids[] = { + { .compatible = "fsl,vf610-usb" }, + { } +}; + +U_BOOT_DRIVER(usb_ehci) = { + .name = "ehci_vf", + .id = UCLASS_USB, + .of_match = vf_usb_ids, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_vf_priv_data), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif -- 2.9.2

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[U-Boot] [PATCH v2 0/3] Fix loading kernel on RK3288 Radxa Rock2 Square
by Sandy Patterson 09 Aug '16

09 Aug '16

I wasn't able to load the linux kernel using a Rock2 board using the latest master branch. The board hangs after it has handed executing over to the kernel. I found that the latest release that worked was v2016.03. This patchset fixes kernel loading on rk3288 rock2 square board. I tested with with 3.14 adn 4.7-rc6 kernels. I used gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabi. Before fixing, the console output was: Starting kernel ... ### ERROR ### Please RESET the board ### Changes for v2: - Remove patch to change to high mem limit. - Rebase to u-boot/master. Sandy Patterson (3): Revert "arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL) with asm code" Revert "arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL) with asm code" CONFIG_EFI_LOADER breaks rock2 kernel loading arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/cache_v7.c | 134 ++++++++++++++++++++++- arch/arm/cpu/armv7/cache_v7_asm.S | 154 --------------------------- arch/arm/mach-uniphier/arm32/lowlevel_init.S | 67 +++++++++++- configs/rock2_defconfig | 1 + 5 files changed, 198 insertions(+), 160 deletions(-) delete mode 100644 arch/arm/cpu/armv7/cache_v7_asm.S -- 1.9.1

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[U-Boot] Pull request: u-boot-spi/master
by Jagan Teki 09 Aug '16

09 Aug '16

Hi Tom, Please pull this request. thanks! Jagan. The following changes since commit 08887ed4505ec14ee94ab32c482dc4dec5ddc1e4: ARM: am57xx_evm: Enable QSPI support (2016-07-30 00:15:07 +0530) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 53208741d6c3448b7a7f5260d52c28f912ff6453: dm: at91: Add driver model support for the spi driver (2016-07-31 17:03:33 +0530) ---------------------------------------------------------------- Lad, Prabhakar (1): spi: zynq_spi: Fix infinite looping while xfer Wenyou Yang (1): dm: at91: Add driver model support for the spi driver drivers/spi/Kconfig | 7 ++ drivers/spi/atmel_spi.c | 295 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/zynq_spi.c | 2 +- 3 files changed, 303 insertions(+), 1 deletion(-)

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[U-Boot] [PATCH v3 1/2] eth: asix88179: Prepare supporting the driver model
by Alban Bedel 09 Aug '16

09 Aug '16

Change the prototype of a few functions to allow resuing the code for the driver model. Signed-off-by: Alban Bedel <alban.bedel(a)avionic-design.de> --- Changelog: v3: * Don't break the build without driver model --- drivers/usb/eth/asix88179.c | 75 ++++++++++++++++++++++++++++----------------- 1 file changed, 47 insertions(+), 28 deletions(-) diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 81eae04e3402..f3179bcf1e2e 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -259,36 +259,32 @@ static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, return len == size ? 0 : ECOMM; } -static int asix_read_mac(struct eth_device *eth) +static int asix_read_mac(struct ueth_data *dev, uint8_t *enetaddr) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - u8 buf[ETH_ALEN]; + int ret; - asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf); - debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n", - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + ret = asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, enetaddr); + if (ret < 0) + debug("Failed to read MAC address: %02x\n", ret); - memcpy(eth->enetaddr, buf, ETH_ALEN); - - return 0; + return ret; } -static int asix_write_mac(struct eth_device *eth) +static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; int ret; ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, - ETH_ALEN, eth->enetaddr); + ETH_ALEN, enetaddr); if (ret < 0) debug("Failed to set MAC address: %02x\n", ret); return ret; } -static int asix_basic_reset(struct ueth_data *dev) +static int asix_basic_reset(struct ueth_data *dev, + struct asix_private *dev_priv) { - struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; u8 buf[5]; u16 *tmp16; u8 *tmp; @@ -387,13 +383,9 @@ static int asix_wait_link(struct ueth_data *dev) } } -/* - * Asix callbacks - */ -static int asix_init(struct eth_device *eth, bd_t *bd) +static int asix_init_common(struct ueth_data *dev, + struct asix_private *dev_priv) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; u8 buf[2], tmp[5], link_sts; u16 *tmp16, mode; @@ -411,7 +403,7 @@ static int asix_init(struct eth_device *eth, bd_t *bd) if (asix_wait_link(dev) != 0) { /*reset device and try again*/ printf("Reset Ethernet Device\n"); - asix_basic_reset(dev); + asix_basic_reset(dev, dev_priv); if (asix_wait_link(dev) != 0) goto out_err; } @@ -463,11 +455,10 @@ out_err: return -1; } -static int asix_send(struct eth_device *eth, void *packet, int length) +static int asix_send_common(struct ueth_data *dev, + struct asix_private *dev_priv, + void *packet, int length) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; - int err; u32 packet_len, tx_hdr2; int actual_len, framesize; @@ -504,6 +495,32 @@ static int asix_send(struct eth_device *eth, void *packet, int length) return err; } +/* + * Asix callbacks + */ +static int asix_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; + + return asix_init_common(dev, dev_priv); +} + +static int asix_write_hwaddr(struct eth_device *eth) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + + return asix_write_mac(dev, eth->enetaddr); +} + +static int asix_send(struct eth_device *eth, void *packet, int length) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; + + return asix_send_common(dev, dev_priv, packet, length); +} + static int asix_recv(struct eth_device *eth) { struct ueth_data *dev = (struct ueth_data *)eth->priv; @@ -693,6 +710,8 @@ int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, struct eth_device *eth) { + struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv; + if (!eth) { debug("%s: missing parameter.\n", __func__); return 0; @@ -702,14 +721,14 @@ int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, eth->send = asix_send; eth->recv = asix_recv; eth->halt = asix_halt; - eth->write_hwaddr = asix_write_mac; + eth->write_hwaddr = asix_write_hwaddr; eth->priv = ss; - if (asix_basic_reset(ss)) + if (asix_basic_reset(ss, dev_priv)) return 0; /* Get the MAC address */ - if (asix_read_mac(eth)) + if (asix_read_mac(ss, eth->enetaddr)) return 0; debug("MAC %pM\n", eth->enetaddr); -- 2.9.2

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[U-Boot] [PATCH] tools: kwboot: patch destaddr only for SoCs with header version 1
by Simon Baatz 09 Aug '16

09 Aug '16

Commit f4db6c976cf ("arm: mvebu: Add runtime detection of UART (xmodem) boot-mode") added a change to hdr->destaddr when dynamically patching an image for UART boot mode. With this change, kwboot ceases to work on Kirkwood. Thus, let's change hdr->destaddr only when we are patching an image with header version 1 (Orion and Kirkwood use header version 0). Signed-off-by: Simon Baatz <gmbnomis(a)gmail.com> Fixes: f4db6c976cf ("arm: mvebu: Add runtime detection of UART (xmodem) boot-mode") Cc: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Kevin Smith <kevin.smith(a)elecsyscorp.com> --- Hi, this patch makes kwboot work again on Kirkwood for me. However, I could not verify whether Armada XP / 38x still works, since I don't have such hardware. - Simon tools/kwboot.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tools/kwboot.c b/tools/kwboot.c index e00958a..4160e5b 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -655,14 +655,6 @@ kwboot_img_patch_hdr(void *img, size_t size) hdr->blockid = IBR_HDR_UART_ID; - /* - * Subtract mkimage header size from destination address - * as this header is not expected by the Marvell BootROM. - * This way, the execution address is identical to the - * one the image is compiled for (TEXT_BASE). - */ - hdr->destaddr = hdr->destaddr - sizeof(struct image_header); - if (image_ver == 0) { struct main_hdr_v0 *hdr_v0 = img; @@ -672,6 +664,14 @@ kwboot_img_patch_hdr(void *img, size_t size) hdr_v0->srcaddr = hdr_v0->ext ? sizeof(struct kwb_header) : sizeof(*hdr_v0); + } else { + /* + * Subtract mkimage header size from destination address + * as this header is not expected by the Marvell BootROM. + * This way, the execution address is identical to the + * one the image is compiled for (TEXT_BASE). + */ + hdr->destaddr = hdr->destaddr - sizeof(struct image_header); } hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum; -- 2.7.4

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[U-Boot] [PATCH] marvell: add support for Synology DS109 board
by Walter Schweizer 09 Aug '16

09 Aug '16

>From 842431a0cc2acb336f5c57a3ca822ba0673e712d Mon Sep 17 00:00:00 2001 From: Walter Schweizer <swwa(a)users.sourceforge.net> Date: Sat, 18 Jun 2016 12:56:37 +0200 Subject: [PATCH] add support for Synology DS109 board Synology DS109 is based on MV88F6281. The code is based on Dreamplug code with modificatons from Synologys open source repository. Signed-off-by: Walter Schweizer <swwa(a)users.sourceforge.net> --- arch/arm/mach-kirkwood/Kconfig | 4 + board/Synology/ds109/Kconfig | 12 +++ board/Synology/ds109/Makefile | 9 ++ board/Synology/ds109/ds109.c | 169 ++++++++++++++++++++++++++++++++++++++ board/Synology/ds109/ds109.h | 44 ++++++++++ board/Synology/ds109/kwbimage.cfg | 147 +++++++++++++++++++++++++++++++++ board/Synology/ds109/openocd.cfg | 115 ++++++++++++++++++++++++++ configs/ds109_defconfig | 16 ++++ include/configs/ds109.h | 118 ++++++++++++++++++++++++++ 9 files changed, 634 insertions(+) create mode 100644 board/Synology/ds109/Kconfig create mode 100644 board/Synology/ds109/Makefile create mode 100644 board/Synology/ds109/ds109.c create mode 100644 board/Synology/ds109/ds109.h create mode 100644 board/Synology/ds109/kwbimage.cfg create mode 100644 board/Synology/ds109/openocd.cfg create mode 100644 configs/ds109_defconfig create mode 100644 include/configs/ds109.h diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 9205b1e..9c24921 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -10,6 +10,9 @@ config TARGET_OPENRD config TARGET_DREAMPLUG bool "DreamPlug Board" +config TARGET_DS109 + bool "Synology DS109" + config TARGET_GURUPLUG bool "GuruPlug Board" @@ -59,6 +62,7 @@ config SYS_SOC source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" +source "board/Synology/ds109/Kconfig" source "board/Marvell/guruplug/Kconfig" source "board/Marvell/sheevaplug/Kconfig" source "board/buffalo/lsxl/Kconfig" diff --git a/board/Synology/ds109/Kconfig b/board/Synology/ds109/Kconfig new file mode 100644 index 0000000..a7c75ae --- /dev/null +++ b/board/Synology/ds109/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DS109 + +config SYS_BOARD + default "ds109" + +config SYS_VENDOR + default "Synology" + +config SYS_CONFIG_NAME + default "ds109" + +endif diff --git a/board/Synology/ds109/Makefile b/board/Synology/ds109/Makefile new file mode 100644 index 0000000..eeeb64d --- /dev/null +++ b/board/Synology/ds109/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ds109.o diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c new file mode 100644 index 0000000..8ab1387 --- /dev/null +++ b/board/Synology/ds109/ds109.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <luka(a)openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include "ds109.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(DS109_OE_VAL_LOW, + DS109_OE_VAL_HIGH, + DS109_OE_LOW, DS109_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_SPI_SCn, /* SPI Flash */ + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_GPIO, + MPP5_GPO, + MPP6_SYSRST_OUTn, /* Reset signal */ + MPP7_GPO, + MPP8_TW_SDA, /* I2C */ + MPP9_TW_SCK, /* I2C */ + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, + MPP13_UART1_TXD, + MPP14_UART1_RXD, + MPP15_GPIO, + MPP16_GPIO, + MPP17_GPIO, + MPP18_GPO, + MPP19_GPO, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, /* HDD2 FAIL LED */ + MPP23_GPIO, /* HDD1 FAIL LED */ + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, /* HDD2 */ + MPP32_GPIO, /* FAN A */ + MPP33_GPIO, /* FAN B */ + MPP34_GPIO, /* FAN C */ + MPP35_GPIO, /* FAN SENSE */ + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +/* Synology reset uses UART */ +#include <ns16550.h> +#define SOFTWARE_SHUTDOWN 0x31 +#define SOFTWARE_REBOOT 0x43 +#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE +void reset_misc(void) +{ + int b_d; + printf("Synology reset..."); + udelay(50000); + + b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2, + CONFIG_SYS_NS16550_CLK, 9600); + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d); + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT); +} + +/* Support old kernels */ +void setup_board_tags(struct tag **in_params) +{ + unsigned int boardId; + struct tag *params; + struct tag_mv_uboot *t; + + printf("Synology board tags..."); + params = *in_params; + t = (struct tag_mv_uboot *)&params->u; + + t->uboot_version = VER_NUM; + + boardId = SYNO_DS109_ID; + t->uboot_version |= boardId; + + t->tclk = CONFIG_SYS_TCLK; + t->sysclk = CONFIG_SYS_TCLK*2; + + params->hdr.tag = ATAG_MV_UBOOT; + params->hdr.size = tag_size(tag_mv_uboot); + params = tag_next(params); + *in_params = params; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { + printf("Error: 88E1116 could not read PHY dev address\n"); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Synology/ds109/ds109.h b/board/Synology/ds109/ds109.h new file mode 100644 index 0000000..95d924c --- /dev/null +++ b/board/Synology/ds109/ds109.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <luka(a)openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DS109_H +#define __DS109_H + +#define DS109_OE_LOW (~(0)) +#define DS109_OE_HIGH (~(0)) +#define DS109_OE_VAL_LOW ((1 << 22)|(1 << 23)) +#define DS109_OE_VAL_HIGH ((1 << 1)|1) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_MAC_CTRL2_REG 21 + +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +/* Marvell uboot parameters */ +#define ATAG_MV_UBOOT 0x41000403 +#define VER_NUM 0x03040400 /* 3.4.4 */ +#define BOARD_ID_BASE 0x0 +#define SYNO_DS109_ID (BOARD_ID_BASE+0x15) + +struct tag_mv_uboot { + u32 uboot_version; + u32 tclk; + u32 sysclk; + u32 isusbhost; + char macaddr[4][6]; + u16 mtu[4]; + u32 fw_image_base; + u32 fw_image_size; +}; + +#endif /* __DS109_H */ diff --git a/board/Synology/ds109/kwbimage.cfg b/board/Synology/ds109/kwbimage.cfg new file mode 100644 index 0000000..19d77e3 --- /dev/null +++ b/board/Synology/ds109/kwbimage.cfg @@ -0,0 +1,147 @@ +# +# (C) Copyright 2011 +# Jason Cooper <u-boot(a)lakedaemon.net> +# +# Based on work by: +# Marvell Semiconductor <www.marvell.com> +# Written-by: Siddarth Gore <gores(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b9b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000cc # DDR Address Control +# bit1-0: 01, Cs0width=x8 +# bit3-2: 10, Cs0size=1Gb +# bit5-4: 01, Cs1width=x8 +# bit7-6: 10, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/Synology/ds109/openocd.cfg b/board/Synology/ds109/openocd.cfg new file mode 100644 index 0000000..baa512a --- /dev/null +++ b/board/Synology/ds109/openocd.cfg @@ -0,0 +1,115 @@ +# Synology DS109 + +interface ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x000b +ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040 + +adapter_khz 2000 + +# length of reset signal: [ms] +adapter_nsrst_assert_width 1000 + +# don't talk to JTAG after reset for: [ms] +adapter_nsrst_delay 200 + +source [find target/feroceon.cfg] + +reset_config trst_and_srst srst_nogate + +proc ds109_init { } { + + # We need to assert DBGRQ while holding nSRST down. + # However DBGACK will be set only when nSRST is released. + # Furthermore, the JTAG interface doesn't respond at all when + # the CPU is in the WFI (wait for interrupts) state, so it is + # possible that initial tap examination failed. So let's + # re-examine the target again here when nSRST is asserted which + # should then succeed. + jtag_reset 0 1 + feroceon.cpu arp_examine + halt 0 + jtag_reset 0 0 + wait_halt + #reset run + #soft_reset_halt + + arm mcr 15 0 0 1 0 0x00052078 + + mww 0xD00100e0 0x1b1b1b9b ;# + mww 0xD0020134 0xbbbbbbbb ;# + mww 0xD0020138 0x00bbbbbb ;# + mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register + mww 0xD0001404 0x39743000 ;# Dunit Control Low Register + mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register + mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register + mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register + mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register + mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register + mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register + mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register + mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register + mww 0xD0001428 0x00085520 ;# Dunit Control High Register + mww 0xD000147c 0x00008552 ;# Dunit Control High Register + mww 0xD0001500 0x00000000 ;# + mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register + mww 0xD0001508 0x10000000 ;# CS1n Base Register + mww 0xD000150C 0x00000000 ;# CS1n Size Register + mww 0xD0001510 0x20000000 ;# + mww 0xD0001514 0x00000000 ;# CS2n Size Register + mww 0xD000151C 0x00000000 ;# CS3n Size Register + mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register + mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister + mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register + mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register + mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + + mww 0xD0010000 0x01111111 ;# MPP 0 to 7 + mww 0xD0010004 0x11113322 ;# MPP 8 to 15 + mww 0xD0010008 0x00001111 ;# MPP 16 to 23 +} + +proc ds109_load { } { + # load u-Boot into RAM and execute it + ds109_init + load_image u-boot.bin 0x00600000 bin + resume 0x00600000 +} diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig new file mode 100644 index 0000000..34a4673 --- /dev/null +++ b/configs/ds109_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_DS109=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/include/configs/ds109.h b/include/configs/ds109.h new file mode 100644 index 0000000..987038f --- /dev/null +++ b/include/configs/ds109.h @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2011 + * Jason Cooper <u-boot(a)lakedaemon.net> + * + * Based on work by: + * Marvell Semiconductor <www.marvell.com> + * Written-by: Siddarth Gore <gores(a)marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_DS109_H +#define _CONFIG_DS109_H + +/* + * FIXME: This belongs in mach-types.h. However, we only pull mach-types + * from Linus' kernel.org tree. This hasn't been updated primarily due to + * the recent arch/arm reshuffling. So, in the meantime, we'll place it + * here. + */ +#include <asm/mach-types.h> +#ifdef MACH_TYPE_SYNOLOGY +#error "MACH_TYPE_SYNOLOGY has been defined properly, please remove this." +#else +#define MACH_TYPE_SYNOLOGY 527 +#endif + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nDS109" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_MACH_TYPE MACH_TYPE_SYNOLOGY + +/* + * Commands configuration + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * mv-plug-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-plug-common.h" + +/* + * Environment variables configurations + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif + +#ifdef CONFIG_CMD_SF +#define CONFIG_HARD_SPI 1 +#define CONFIG_KIRKWOOD_SPI 1 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */ +#endif + +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_ADDR 0x3d0000 +#define CONFIG_ENV_OFFSET 0x3d0000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ + "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "bootm 0x6400000;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "x_bootcmd_ethernet=ping 192.168.1.2\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ + "x_bootargs=console=ttyS0,115200\0" \ + "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \ + "ipaddr=192.168.1.5\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */ +#define CONFIG_PHY_BASE_ADR 8 +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ + +#endif /* _CONFIG_DS109_H */ + +/* + * * RTC driver configuration + * */ +#ifdef CONFIG_CMD_DATE +#undef CONFIG_RTC_MV +#define CONFIG_RTC_RS5C372A +#endif /* CONFIG_CMD_DATE */ + + -- 2.1.4

2 1

[U-Boot] p4080ds UPM Mode Enable
by yyurtcan 09 Aug '16

09 Aug '16

Hi, How I can enable UPMA mode in u-boot in the P4080DS board? (By defualt it is gpcm mode.) Best regards. -- View this message in context: http://u-boot.10912.n7.nabble.com/p4080ds-UPM-Mode-Enable-tp263781.html Sent from the U-Boot mailing list archive at Nabble.com.

1 0

[U-Boot] p4080ds UPM Mode Enable
by yyurtcan 09 Aug '16

09 Aug '16

Hi, How I can enable UPMA mode in u-boot in the P408DS board? (By defualt it is gpcm mode.) Best regards. -- View this message in context: http://u-boot.10912.n7.nabble.com/p4080ds-UPM-Mode-Enable-tp263780.html Sent from the U-Boot mailing list archive at Nabble.com.

1 0

[U-Boot] [PATCH][v2] board: ls1012afrdm: overwrite CONFIG_EXTRA_ENV_SETTINGS
by Pratiyush Mohan Srivastava 09 Aug '16

09 Aug '16

From: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> LS1012AFRDM has 512MB of DDR. So update Kernel load address as 0x96000000 instead of default 0xa0000000. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)nxp.com> --- Changes for v2: Incorporated York's comments - Removed ramdisk_addr, ramdisk_size - Updated UART baud-rate. include/configs/ls1012afrdm.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index ad81142..f2c6ca8 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -39,4 +39,18 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "initrd_high=0xffffffff\0" \ + "verify=no\0" \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0xa00000\0" \ + "kernel_load=0x96000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyAMA0,115200n8\0" + #endif /* __LS1012ARDB_H__ */ -- 1.9.1

4 7

[U-Boot] [PATCH] drivers: net: cpsw: always flush cache with cache line aligned
by Lokesh Vutla 09 Aug '16

09 Aug '16

cpsw tries to flush dcache which is not in the range of cache line size. Because of this the following warning comes while flushing: CACHE: Misaligned operation at range [dffecec0, dffed016] Fix it by flushing cache range which is cache line size aligned. Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- drivers/net/cpsw.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 2ce4ec6..631544a 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -905,9 +905,14 @@ static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) void *buffer; int len; int timeout = CPDMA_TIMEOUT; + unsigned long pstart, pend; - flush_dcache_range((unsigned long)packet, - (unsigned long)packet + length); + /* + * Make sure range is cache line aligned. + */ + pstart = (unsigned long)packet & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + pend = ALIGN((unsigned long)packet + length, CONFIG_SYS_CACHELINE_SIZE); + flush_dcache_range(pstart, pend); /* first reap completed packets */ while (timeout-- && -- 2.9.2

2 2