August 2016 - U-Boot

[U-Boot] how to combine new default env in new u-boot with current saved?
by Robert P. J. Day 16 Aug '16

16 Aug '16

i'm wondering if "env import" and "env export" are the solutions to this question -- i want to be able to install a new u-boot binary, then combine the factory defaults in that new binary with what is currently saved, such that the current, saved values take precedence if the same variable appears in both places. i'd like to think that can't be hard, but i've been surprised before. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH] Please pull u-boot-mmc
by Jaehoon Chung 16 Aug '16

16 Aug '16

Dear Tom, Sorry for confusing..Could you pull these patches on u-boot/master? If there are other problems, let me know, plz. Rebased on latest u-boot/master. (Wenyou's patches was applied on u-boot-atmel.) Sorry for late.. Best Regards, Jaehoon Chung The following changes since commit 4cc9699be7ffc6072482240f5ba208488abe1090: common: env_nand: Ensure that we have nand_info[0] prior to use (2016-08-15 18:46:41 -0400) are available in the git repository at: http://git.denx.de/u-boot-mmc.git master for you to fetch changes up to 177381a9f9e956353deaa56d86bec47e02995ff3: mmc: mmc_legacy: fix the compiler error with disabled CONFIG_DM_MMC_OPS (2016-08-16 10:27:24 +0900) ---------------------------------------------------------------- Jaehoon Chung (1): mmc: mmc_legacy: fix the compiler error with disabled CONFIG_DM_MMC_OPS Sekhar Nori (4): drivers: mmc: omap_hsmmc: fix build breakage ARM: dts: K2G: Add support for MMC controller ARM: dts: k2g-evm: enable mmc/sd suppport defconfig: k2g_evm_defconfig: Enable mmc driver model Yangbo Lu (1): mmc: send CMD0 before CMD1 for some MMC cards arch/arm/dts/k2g-evm.dts | 8 ++++++++ arch/arm/dts/k2g.dtsi | 23 +++++++++++++++++++++++ configs/k2g_evm_defconfig | 1 + drivers/mmc/mmc.c | 3 +++ drivers/mmc/mmc_legacy.c | 9 +++++++-- drivers/mmc/omap_hsmmc.c | 2 ++ 6 files changed, 44 insertions(+), 2 deletions(-)

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[U-Boot] test.py and tftp crc32 test?
by Tom Rini 16 Aug '16

16 Aug '16

Hey guys, Is anyone else running the crc32 tftp tests with test.py? I'm trying to do it locally but even with a 2MiB file it looks like somehow the crc32 is never captured in the output. I've already made sure that the crc32 value is in lowercase to match the U-Boot output and running the test steps in console gives me the expected output. And the rest of the network tests pass, any ideas? Thanks! -- Tom

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[U-Boot] [PATCH] clk.h: inline clk_get_by_name()
by Andreas Bießmann 16 Aug '16

16 Aug '16

Fix compile warning for non OF_CONTROL builds: ---8<--- In file included from /Volumes/devel/u-boot/drivers/gpio/atmel_pio4.c:10:0: /Volumes/devel/u-boot/include/clk.h:107:12: warning: 'clk_get_by_name' defined but not used [-Wunused-function] --->8--- Signed-off-by: Andreas Bießmann <andreas(a)biessmann.org> --- include/clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/clk.h b/include/clk.h index 161bc28..dc18b03 100644 --- a/include/clk.h +++ b/include/clk.h @@ -104,7 +104,7 @@ static inline int clk_get_by_index(struct udevice *dev, int index, return -ENOSYS; } -static int clk_get_by_name(struct udevice *dev, const char *name, +static inline int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) { return -ENOSYS; -- 2.7.4 (Apple Git-66)

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[U-Boot] [PATCH 0/5] ARM: Enable CMD_TIME on all TI platforms
by Lokesh Vutla 16 Aug '16

16 Aug '16

This series enables CMD_TIME on all TI platforms. Lokesh Vutla (5): configs: am335x: Enable CMD_TIME configs: am43xx: Enable CMD_TIME configs: am57xx: Enable CMD_TIME configs: dra7xx: Enable CMD_TIME configs: ks2: Enable CMD_TIME configs/am335x_boneblack_defconfig | 1 + configs/am335x_evm_defconfig | 1 + configs/am335x_evm_nor_defconfig | 1 + configs/am335x_evm_norboot_defconfig | 1 + configs/am335x_evm_spiboot_defconfig | 1 + configs/am335x_evm_usbspl_defconfig | 1 + configs/am43xx_evm_defconfig | 1 + configs/am43xx_evm_ethboot_defconfig | 1 + configs/am43xx_evm_qspiboot_defconfig | 1 + configs/am43xx_evm_usbhost_boot_defconfig | 1 + configs/am43xx_hs_evm_defconfig | 1 + configs/am57xx_evm_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + configs/dra7xx_hs_evm_defconfig | 1 + configs/k2e_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + 19 files changed, 19 insertions(+) -- 2.9.2

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[U-Boot] [PATCH 1/2 v4] x86: Add DFI BT700 BayTrail board support
by Stefan Roese 16 Aug '16

16 Aug '16

This patch adds support for the DFI BayTrail BT700 QSeven SoM installed on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton NCT6102D Super IO chip providing the UART as console. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- v4: - Remove dfi-bt700-internal-uart_defconfig - Add missing entry to MAINTAINERS v3: - Change comment Winbond > Nuvoton - Remove unneeded compatible property in HS-UART DTS node v2: - Added missing text to Kconfig entry arch/x86/Kconfig | 4 + arch/x86/dts/Makefile | 1 + arch/x86/dts/dfi-bt700-q7x-151.dts | 22 +++ arch/x86/dts/dfi-bt700.dtsi | 308 +++++++++++++++++++++++++++++++++ board/dfi/Kconfig | 29 ++++ board/dfi/dfi-bt700/Kconfig | 28 +++ board/dfi/dfi-bt700/MAINTAINERS | 8 + board/dfi/dfi-bt700/Makefile | 8 + board/dfi/dfi-bt700/acpi/mainboard.asl | 13 ++ board/dfi/dfi-bt700/dfi-bt700.c | 30 ++++ board/dfi/dfi-bt700/dsdt.asl | 14 ++ board/dfi/dfi-bt700/start.S | 9 + configs/dfi-bt700-q7x-151_defconfig | 63 +++++++ include/configs/dfi-bt700.h | 74 ++++++++ 14 files changed, 611 insertions(+) create mode 100644 arch/x86/dts/dfi-bt700-q7x-151.dts create mode 100644 arch/x86/dts/dfi-bt700.dtsi create mode 100644 board/dfi/Kconfig create mode 100644 board/dfi/dfi-bt700/Kconfig create mode 100644 board/dfi/dfi-bt700/MAINTAINERS create mode 100644 board/dfi/dfi-bt700/Makefile create mode 100644 board/dfi/dfi-bt700/acpi/mainboard.asl create mode 100644 board/dfi/dfi-bt700/dfi-bt700.c create mode 100644 board/dfi/dfi-bt700/dsdt.asl create mode 100644 board/dfi/dfi-bt700/start.S create mode 100644 configs/dfi-bt700-q7x-151_defconfig create mode 100644 include/configs/dfi-bt700.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 29d1120..5193ee7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -17,6 +17,9 @@ config VENDOR_CONGATEC config VENDOR_COREBOOT bool "coreboot" +config VENDOR_DFI + bool "dfi" + config VENDOR_EFI bool "efi" @@ -35,6 +38,7 @@ endchoice source "board/advantech/Kconfig" source "board/congatec/Kconfig" source "board/coreboot/Kconfig" +source "board/dfi/Kconfig" source "board/efi/Kconfig" source "board/emulation/Kconfig" source "board/google/Kconfig" diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 4f07f41..ca086bd 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -9,6 +9,7 @@ dtb-y += bayleybay.dtb \ conga-qeval20-qa3-e3845.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ + dfi-bt700-q7x-151.dtb \ efi.dtb \ galileo.dtb \ minnowmax.dtb \ diff --git a/arch/x86/dts/dfi-bt700-q7x-151.dts b/arch/x86/dts/dfi-bt700-q7x-151.dts new file mode 100644 index 0000000..31d9679 --- /dev/null +++ b/arch/x86/dts/dfi-bt700-q7x-151.dts @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "dfi-bt700.dtsi" + +#include "serial.dtsi" + +/ { + model = "DFI-BT700"; + compatible = "dfi,bt700", "intel,baytrail"; + + aliases { + serial0 = &serial; + spi0 = &spi; + }; +}; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi new file mode 100644 index 0000000..75ee6ad --- /dev/null +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -0,0 +1,308 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +#include "skeleton.dtsi" +#include "rtc.dtsi" +#include "tsc_timer.dtsi" + +/ { + config { + silent_console = <0>; + }; + + pch_pinctrl { + compatible = "intel,x86-pinctrl"; + reg = <0 0>; + + /* Add UART1 PAD configuration (SIO HS-UART) */ + uart1_txd@0 { + pad-offset = <0x10>; + mode-func = <1>; + }; + + uart1_rxd@0 { + pad-offset = <0x20>; + mode-func = <1>; + }; + + /* + * As of today, the latest version FSP (gold4) for BayTrail + * misses the PAD configuration of the SD controller's Card + * Detect signal. The default PAD value for the CD pin sets + * the pin to work in GPIO mode, which causes card detect + * status cannot be reflected by the Present State register + * in the SD controller (bit 16 & bit 18 are always zero). + * + * Configure this pin to function 1 (SD controller). + */ + sdmmc3_cd@0 { + pad-offset = <0x3a0>; + mode-func = <1>; + }; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + }; + + pci { + compatible = "intel,pci-baytrail", "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pciuart0: uart@1e,3 { + compatible = "pci8086,0f0a.00", + "pci8086,0f0a", + "pciclass,070002", + "pciclass,0700", + "ns16550"; + u-boot,dm-pre-reloc; + reg = <0x0200f310 0x0 0x0 0x0 0x0>; + reg-shift = <2>; + clock-frequency = <58982400>; + current-speed = <115200>; + }; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "pci8086,0f1c", "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,actl-addr = <0>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* + * PCIe root ports downstream + * interrupts + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + + spi: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9-spi"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "stmicro,n25q064a", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; + }; + }; + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <1>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart0; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-lpe; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + fsp,enable-memory-down; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <2>; /* 2=1333MHz */ + fsp,dram-type = <1>; /* 1=DDR3L */ + fsp,dimm-0-enable; + fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ + fsp,dimm-density = <3>; /* 3=8Gbit */ + fsp,dimm-bus-width = <3>; /* 3=64bits */ + fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ + + /* These following values might need a re-visit */ + fsp,dimm-tcl = <8>; + fsp,dimm-trpt-rcd = <8>; + fsp,dimm-twr = <8>; + fsp,dimm-twtr = <4>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <4>; + fsp,dimm-tfaw = <22>; + }; + }; + + microcode { + update@0 { +#include "microcode/m0130673325.dtsi" + }; + update@1 { +#include "microcode/m0130679907.dtsi" + }; + }; +}; diff --git a/board/dfi/Kconfig b/board/dfi/Kconfig new file mode 100644 index 0000000..25d0a11 --- /dev/null +++ b/board/dfi/Kconfig @@ -0,0 +1,29 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_DFI + +choice + prompt "Mainboard model" + optional + +config TARGET_DFI_BT700 + bool "DFI BT700 BayTrail" + help + This is the DFI Q7X-151 baseboard equipped with the + DFI BayTrail Bt700 SoM. It contains an Atom E3845 with + Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2, + USB 3, SATA, serial console and DisplayPort video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + +endchoice + +source "board/dfi/dfi-bt700/Kconfig" + +endif diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig new file mode 100644 index 0000000..3f0acb3 --- /dev/null +++ b/board/dfi/dfi-bt700/Kconfig @@ -0,0 +1,28 @@ +if TARGET_DFI_BT700 + +config SYS_BOARD + default "dfi-bt700" + +config SYS_VENDOR + default "dfi" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "dfi-bt700" + +config SYS_TEXT_BASE + default 0xfff00000 if !EFI_STUB + default 0x01110000 if EFI_STUB + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR if !EFI_STUB + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/dfi/dfi-bt700/MAINTAINERS b/board/dfi/dfi-bt700/MAINTAINERS new file mode 100644 index 0000000..9c3d699 --- /dev/null +++ b/board/dfi/dfi-bt700/MAINTAINERS @@ -0,0 +1,8 @@ +congatec DFI-BT700 +M: Stefan Roese <sr(a)denx.de> +S: Maintained +F: board/dfi/dfi-bt700 +F: include/configs/dfi-bt700.h +F: configs/dfi-bt700-q7x-151_defconfig +F: arch/x86/dts/dfi-bt700.dtsi +F: arch/x86/dts/dfi-bt700-q7x-151.dts diff --git a/board/dfi/dfi-bt700/Makefile b/board/dfi/dfi-bt700/Makefile new file mode 100644 index 0000000..8052f5e --- /dev/null +++ b/board/dfi/dfi-bt700/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += dfi-bt700.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/dfi/dfi-bt700/acpi/mainboard.asl b/board/dfi/dfi-bt700/acpi/mainboard.asl new file mode 100644 index 0000000..544a049 --- /dev/null +++ b/board/dfi/dfi-bt700/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} + +/* TODO: Need add Nuvoton SuperIO chipset NCT6102D ASL codes */ diff --git a/board/dfi/dfi-bt700/dfi-bt700.c b/board/dfi/dfi-bt700/dfi-bt700.c new file mode 100644 index 0000000..8645bdc --- /dev/null +++ b/board/dfi/dfi-bt700/dfi-bt700.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nuvoton_nct6102d.h> +#include <asm/gpio.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> + +int board_early_init_f(void) +{ +#ifdef CONFIG_INTERNAL_UART + /* Disable the legacy UART which is enabled per default */ + nct6102d_uarta_disable(); +#else + /* + * The FSP enables the BayTrail internal legacy UART (again). + * Disable it again, so that the Nuvoton one can be used. + */ + setup_internal_uart(0); +#endif + + /* Disable the watchdog which is enabled per default */ + nct6102d_wdt_disable(); + + return 0; +} diff --git a/board/dfi/dfi-bt700/dsdt.asl b/board/dfi/dfi-bt700/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/dfi/dfi-bt700/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/dfi/dfi-bt700/start.S b/board/dfi/dfi-bt700/start.S new file mode 100644 index 0000000..2c941a4 --- /dev/null +++ b/board/dfi/dfi-bt700/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig new file mode 100644 index 0000000..6f00004 --- /dev/null +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -0,0 +1,63 @@ +CONFIG_X86=y +CONFIG_DM_I2C=y +CONFIG_VENDOR_DFI=y +CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151" +CONFIG_TARGET_DFI_BT700=y +CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SEABIOS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_NUVOTON_NCT6102D=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_114=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h new file mode 100644 index 0000000..23d8a0a --- /dev/null +++ b/include/configs/dfi-bt700.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#ifndef CONFIG_INTERNAL_UART +/* Use BayTrail internal HS UART which is memory-mapped */ +#undef CONFIG_SYS_NS16550_PORT_MAPPED +#endif + +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA + +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_RTL8152 + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO +#define CONFIG_CMD_BMP + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x006ef000 + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_BOOTARGS \ + "root=/dev/sda1 ro quiet" +#define CONFIG_BOOTCOMMAND \ + "load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \ + "load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;" \ + "run boot" + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel-ver=4.4.0-24\0" \ + "boot=zboot 03000000 0 04000000 ${filesize}\0" \ + "upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \ + "sf probe;sf update 100000 0 800000;saveenv\0" + +#define CONFIG_PREBOOT + +#endif /* __CONFIG_H */ -- 2.9.3

2 1

[U-Boot] [PATCH 2/2 v2] x86: Add theadorable-x86-dfi-bt700 board support
by Stefan Roese 16 Aug '16

16 Aug '16

This patch adds support for the BayTrail based theadorable-x86-dfi-bt700 board which uses the DFI BT700 BayTrail Qseven SoM on a custom baseboard. The main difference to the DFI baseboard is, that it isn't equipped with a Super IO chip and uses the internal HS SIO UART (memory mapped PCI based) as the console UART. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- v2: - Add missing MAINTAINERS entry arch/x86/dts/Makefile | 1 + arch/x86/dts/theadorable-x86-dfi-bt700.dts | 21 ++++++++++ board/dfi/dfi-bt700/MAINTAINERS | 2 + configs/theadorable-x86-dfi-bt700_defconfig | 60 +++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+) create mode 100644 arch/x86/dts/theadorable-x86-dfi-bt700.dts create mode 100644 configs/theadorable-x86-dfi-bt700_defconfig diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index ca086bd..3f534ad 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -15,6 +15,7 @@ dtb-y += bayleybay.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \ + theadorable-x86-dfi-bt700.dtb \ broadwell_som-6896.dtb \ baytrail_som-db5800-som-6867.dtb diff --git a/arch/x86/dts/theadorable-x86-dfi-bt700.dts b/arch/x86/dts/theadorable-x86-dfi-bt700.dts new file mode 100644 index 0000000..75f9ffa --- /dev/null +++ b/arch/x86/dts/theadorable-x86-dfi-bt700.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "dfi-bt700.dtsi" + +/ { + model = "theadorable-x86-DFI-BT700"; + compatible = "anonymous,theadorable-x86-dfi-bt700", "dfi,bt700", + "intel,baytrail"; + + aliases { + serial0 = &pciuart0; + spi0 = &spi; + }; +}; diff --git a/board/dfi/dfi-bt700/MAINTAINERS b/board/dfi/dfi-bt700/MAINTAINERS index 9c3d699..6639787 100644 --- a/board/dfi/dfi-bt700/MAINTAINERS +++ b/board/dfi/dfi-bt700/MAINTAINERS @@ -4,5 +4,7 @@ S: Maintained F: board/dfi/dfi-bt700 F: include/configs/dfi-bt700.h F: configs/dfi-bt700-q7x-151_defconfig +F: configs/theadorable-x86-dfi-bt700_defconfig F: arch/x86/dts/dfi-bt700.dtsi F: arch/x86/dts/dfi-bt700-q7x-151.dts +F: arch/x86/dts/theadorable-x86-dfi-bt700.dts diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig new file mode 100644 index 0000000..3aba157 --- /dev/null +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -0,0 +1,60 @@ +CONFIG_X86=y +CONFIG_DM_I2C=y +CONFIG_VENDOR_DFI=y +CONFIG_DEFAULT_DEVICE_TREE="theadorable-x86-dfi-bt700" +CONFIG_TARGET_DFI_BT700=y +CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SEABIOS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_NUVOTON_NCT6102D=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_114=y +CONFIG_USE_PRIVATE_LIBGCC=y -- 2.9.3

2 1

[U-Boot] [PATCH] x86: conga-qeval20-qa3: Add missing MAINTERNERS entry
by Stefan Roese 16 Aug '16

16 Aug '16

Add entry for the missing internal UART defconfig to the MAINTAINERS file. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Bin Meng <bmeng.cn(a)gmail.com> CC: Simon Glass <sjg(a)chromium.org> --- board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS index 5a4d4dc..3d7e8e2 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS +++ b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS @@ -4,4 +4,5 @@ S: Maintained F: board/congatec/conga-qeval20-qa3-e3845 F: include/configs/conga-qeval20-qa3-e3845.h F: configs/conga-qeval20-qa3-e3845_defconfig +F: configs/conga-qeval20-qa3-e3845-internal-uart_defconfig F: arch/x86/dts/conga-qeval20-qa3-e3845.dts -- 2.9.3

2 2

Re: [U-Boot] [PATCH v3 00/27] spi/sf: Updates on flash detection
by york sun 16 Aug '16

16 Aug '16

On 08/11/2016 08:12 AM, york.sun(a)nxp.com wrote: > On 08/11/2016 01:15 AM, Jagan Teki wrote: >> >> Tested on microzed and sandbox >> >> Tested-by: Jagan Teki <jteki(a)openedev.com> >> >> I've some host issues while running buildman, can anyone please run >> buildman? >> > > I can compile for power and (limited) arm for you. > I can't compile test your v3 patch. They are not in mailing list, or patchwork. I only got some of them. York

4 10

[U-Boot] [PATCH] driver: spi: add spansion s25fs-s family protect/unprotect
by Yunhui Cui 16 Aug '16

16 Aug '16

From: Yunhui Cui <yunhui.cui(a)nxp.com> In order to support spansion s25fs512s flash protect/unprotect: [1] Fill callbak flash->lock/unlock/is_locked by spansion_lock/ unlock/is_locked. [2] Achieve protect/unprotected by operating sr1nv, cr1nv. Signed-off-by: Yunhui Cui <yunhui.cui(a)nxp.com> --- drivers/mtd/spi/spi_flash.c | 195 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 64d4e0f..446e6e3 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -839,6 +839,194 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) } #endif +#if defined(CONFIG_SPI_FLASH_SPANSION) +/* + * Return 1 if the entire region is locked, 0 otherwise + */ +static int spansion_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len, + u8 sr) +{ + loff_t lock_offs; + u64 lock_len; + + stm_get_locked_range(flash, sr, &lock_offs, &lock_len); + + return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); +} + +/* + * Check if a region of the flash is (completely) locked. See spansion_lock() + * for more info. + * + * Returns 1 if entire region is locked, 0 if any portion is unlocked, and + * negative on errors. + */ +int spansion_is_locked(struct spi_flash *flash, u32 ofs, size_t len) +{ + u8 cmd[4]; + u32 sr1nv_offset = 0x0; + u8 sr1nv; + int ret; + + cmd[0] = CMD_SPANSION_RDAR; + cmd[1] = sr1nv_offset >> 16; + cmd[2] = sr1nv_offset >> 8; + cmd[3] = sr1nv_offset >> 0; + + ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1); + if (ret) + return -EIO; + + return spansion_is_locked_sr(flash, ofs, len, sr1nv); +} + +/* + * Lock a region of the flash. Compatible with Spansion s25fs-s family flash. + * Supports only the block protection bits BP{0,1,2} in the Status Register-1 + * Non-Volatile(SR1NV). + * + * Sample table portion for 64MB flash (S25FS512S): + * Configuration Register-1 Non-Volatile(CR1NV[5])== 0 + * + * | BP2 | BP1 | BP0 | Prot Length | Protected Portion + * ------------------------------------------------------------ + * | 0 | 0 | 0 | NONE | NONE + * | 0 | 0 | 1 | 1 MB | Upper 1/64 + * | 0 | 1 | 0 | 2 MB | Upper 1/32 + * | 0 | 1 | 1 | 4 MB | Upper 1/16 + * | 1 | 0 | 0 | 8 MB | Upper 1/8 + * | 1 | 0 | 1 | 16 MB | Upper 1/4 + * | 1 | 1 | 0 | 32 MB | Upper 1/2 + * | 1 | 1 | 1 | 64 MB | ALL + * + * When CR1NV[5] == 1, the Lower memory array are protected. + * + * Returns negative on errors, 0 on success. + */ +int spansion_lock(struct spi_flash *flash, u32 ofs, size_t len) +{ + u8 status_old, status_new; + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; + u8 shift = ffs(mask) - 1, pow, val; + int ret; + u8 cmd[4]; + u32 sr1nv_offset = 0x0; + u8 sr1nv; + + cmd[0] = CMD_SPANSION_RDAR; + cmd[1] = sr1nv_offset >> 16; + cmd[2] = sr1nv_offset >> 8; + cmd[3] = sr1nv_offset >> 0; + + ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1); + if (ret) + return -EIO; + status_old = sr1nv; + + /* SPI NOR always locks to the end */ + if (ofs + len != flash->size) { + /* Does combined region extend to end? */ + if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len, + status_old)) + return -EINVAL; + len = flash->size - ofs; + } + + /* + * Need smallest pow such that: + * + * 1 / (2^pow) <= (len / size) + * + * so (assuming power-of-2 size) we do: + * + * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) + */ + pow = ilog2(flash->size) - ilog2(len); + val = mask - (pow << shift); + if (val & ~mask) + return -EINVAL; + + /* Don't "lock" with no region! */ + if (!(val & mask)) + return -EINVAL; + + status_new = (status_old & ~mask) | val; + + /* Only modify protection if it will not unlock other areas */ + if ((status_new & mask) <= (status_old & mask)) + return -EINVAL; + + cmd[0] = CMD_SPANSION_WRAR; + ret = spi_flash_cmd_write(flash->spi, cmd, 4, &status_new, 1); + if (ret) + return -EIO; + + return 0; +} + +/* + * Unlock a region of the flash. See spansion_lock() for more info + * + * Returns negative on errors, 0 on success. + */ +int spansion_unlock(struct spi_flash *flash, u32 ofs, size_t len) +{ + uint8_t status_old, status_new; + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; + u8 shift = ffs(mask) - 1, pow, val; + int ret; + + u8 cmd[4]; + u32 sr1nv_offset = 0x0; + u8 sr1nv; + + cmd[0] = CMD_SPANSION_RDAR; + cmd[1] = sr1nv_offset >> 16; + cmd[2] = sr1nv_offset >> 8; + cmd[3] = sr1nv_offset >> 0; + + ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1); + if (ret) + return -EIO; + status_old = sr1nv; + + /* Cannot unlock; would unlock larger region than requested */ + if (spansion_is_locked_sr(flash, ofs - flash->erase_size, + flash->erase_size, status_old)) + return -EINVAL; + /* + * Need largest pow such that: + * + * 1 / (2^pow) >= (len / size) + * + * so (assuming power-of-2 size) we do: + * + * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) + */ + pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len)); + if (ofs + len == flash->size) { + val = 0; /* fully unlocked */ + } else { + val = mask - (pow << shift); + /* Some power-of-two sizes are not supported */ + if (val & ~mask) + return -EINVAL; + } + status_new = (status_old & ~mask) | val; + + /* Only modify protection if it will not lock other areas */ + if ((status_new & mask) >= (status_old & mask)) + return -EINVAL; + + cmd[0] = CMD_SPANSION_WRAR; + ret = spi_flash_cmd_write(flash->spi, cmd, 4, &status_new, 1); + if (ret) + return -EIO; + + return 0; +} +#endif + #ifdef CONFIG_SPI_FLASH_MACRONIX static int macronix_quad_enable(struct spi_flash *flash) @@ -1134,6 +1322,13 @@ int spi_flash_scan(struct spi_flash *flash) flash->flash_is_locked = stm_is_locked; #endif break; +#if defined(CONFIG_SPI_FLASH_SPANSION) + case SPI_FLASH_CFI_MFR_SPANSION: + flash->flash_lock = spansion_lock; + flash->flash_unlock = spansion_unlock; + flash->flash_is_locked = spansion_is_locked; +#endif + break; default: debug("SF: Lock ops not supported for %02x flash\n", idcode[0]); } -- 2.1.0.27.g96db324

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